stats: Bump stats for the regressions using the minor CPU
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 28 Jul 2014 05:48:21 +0000 (01:48 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 28 Jul 2014 05:48:21 +0000 (01:48 -0400)
Updating the stats to match the current behaviour.

12 files changed:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt

index ef75c7c72ebef2c402a25c6e30b5105168911687..401e8a6303450a2121046b586f3af2e9c0321cc1 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1884223823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 205086                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 329500                       # Number of bytes of host memory used
-host_op_rate                                   205086                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   273.72                       # Real time elapsed on the host
-host_tick_rate                             6883774376                       # Simulator tick rate (ticks/s)
+sim_seconds                                  1.884209                       # Number of seconds simulated
+sim_ticks                                1884208734500                       # Number of ticks simulated
+final_tick                               1884208734500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56136190                       # Number of instructions simulated
-sim_ops                                      56136190                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.884224                       # Number of seconds simulated
-sim_ticks                                1884223823500                       # Number of ticks simulated
+host_inst_rate                                 147223                       # Simulator instruction rate (inst/s)
+host_op_rate                                   147223                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4942377286                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320260                       # Number of bytes of host memory used
+host_seconds                                   381.24                       # Real time elapsed on the host
+sim_insts                                    56126572                       # Number of instructions simulated
+sim_ops                                      56126572                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst          25914048                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28566400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1052800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1052800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7560448                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7560448                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             404907                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                446350                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118132                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118132                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             13753279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1407674                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15160953                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          558749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             558749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4012532                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4012532                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4012532                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            13753279                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1407674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19173485                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        446350                       # Number of read requests accepted
+system.physmem.writeReqs                       118132                       # Number of write requests accepted
+system.physmem.readBursts                      446350                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118132                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28559040                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7558400                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28566400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7560448                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs            154                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28089                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28219                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28571                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28273                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27775                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27529                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               27274                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               26987                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27827                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27514                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              28065                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              27430                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27510                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28401                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28311                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28460                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7814                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7677                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8054                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7732                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7319                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6955                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6788                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6406                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7235                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6877                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7390                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6865                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7046                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8008                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7991                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7943                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1884200137500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  446350                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                 118132                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402858                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      3909                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2828                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1301                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      2032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4354                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3963                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2519                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2152                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2100                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1643                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1621                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1890                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1850                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     2123                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      877                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1024                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4947                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5379                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5861                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1615                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     2004                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65499                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      551.419716                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     340.219574                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.619626                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14326     21.87%     21.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10638     16.24%     38.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5049      7.71%     45.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3016      4.60%     50.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2484      3.79%     54.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2116      3.23%     57.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1384      2.11%     59.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1595      2.44%     62.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24891     38.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65499                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6964                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        64.074383                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       16.502018                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2530.928651                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6961     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6964                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6964                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.958644                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.733261                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.741198                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5665     81.35%     81.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 36      0.52%     81.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                854     12.26%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 55      0.79%     94.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 10      0.14%     95.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 13      0.19%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 23      0.33%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 94      1.35%     96.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 12      0.17%     97.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 41      0.59%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 13      0.19%     97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 17      0.24%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 13      0.19%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 12      0.17%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.04%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 21      0.30%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  7      0.10%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  2      0.03%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  2      0.03%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.03%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  3      0.04%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  3      0.04%     99.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  2      0.03%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  8      0.11%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  7      0.10%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  3      0.04%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  1      0.01%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  1      0.01%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.01%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  7      0.10%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  2      0.03%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.01%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  4      0.06%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  1      0.01%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  9      0.13%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                  8      0.11%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58                  4      0.06%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::59                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6964                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7297586750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15664493000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2231175000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16353.69                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  35103.69                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.16                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.97                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     402726                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96110                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.36                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3337927.76                       # Average gap between requests
+system.physmem.pageHitRate                      88.39                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     1774702818500                       # Time in different power states
+system.physmem.memoryStateTime::REF       62917660000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       46582219000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     19215856                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              295757                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295741                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
+system.membus.trans_dist::Writeback            118132                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              156                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             156                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            158094                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           158094                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887017                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920147                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1044827                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30817728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30862044                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            36171164                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36171164                       # Total data (bytes)
+system.membus.snoop_data_through_bus            35520                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            29834000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy          1588295250                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy               22000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3825084824                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy          376625999                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.iocache.tags.replacements                41685                       # number of replacements
+system.iocache.tags.tagsinuse                1.295855                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1728026399000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.295855                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.080991                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.080991                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
+system.iocache.overall_misses::total            41725                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21134133                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21134133                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  12414876231                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12414876231                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  12436010364                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12436010364                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  12436010364                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12436010364                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122162.618497                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 298779.270095                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 298046.982960                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 298046.982960                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        364154                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28275                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.879010                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137133                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12137133                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10251971233                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10251971233                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10264108366                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10264108366                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10264108366                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10264108366                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 245994.208892                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 245994.208892                       # average overall mshr miss latency
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
+system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
+system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
+system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
+system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
+system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
+system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
+system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
+system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
+system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu.branchPred.lookups                14968340                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12984271                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            377638                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10101234                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5190890                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             52.670853                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 5198600                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups              9869975                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect              32078                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect            374087                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          13023618                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                15007194                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                  808258                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    56136190                       # Number of instructions committed
-system.cpu.committedOps                      56136190                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               3.109494                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13395.968165                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13395.968165                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11388.427222                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.427222                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182878                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182878                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    229754250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    229754250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.085743                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085743                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17151                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17151                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    195288750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    195288750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.085728                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085728                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17148                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17148                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::cpu.inst      9013279                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9013279                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25759.364421                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25759.364421                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25018.369561                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25018.369561                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::cpu.inst      7812296                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7812296                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  30936558760                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  30936558760                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133246                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133246                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      1200983                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1200983                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127128                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127128                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26866101245                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26866101245                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119141                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119141                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1073855                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1073855                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423421000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423421000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       199007                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199007                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       199007                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199007                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst      6151468                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6151468                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36155.340979                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36155.340979                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33789.156794                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33789.156794                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::cpu.inst      5578034                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5578034                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20732701799                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20732701799                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093219                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093219                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       573434                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       573434                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269372                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       269372                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10273998593                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10273998593                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049429                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049429                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304062                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304062                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2002985000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2002985000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     15164747                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15164747                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29119.006727                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29119.006727                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26953.800438                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26953.800438                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      13390330                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13390330                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  51669260559                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51669260559                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.117009                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117009                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      1774417                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1774417                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       396500                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       396500                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37140099838                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37140099838                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090863                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090863                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1377917                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1377917                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     15164747                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15164747                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29119.006727                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29119.006727                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26953.800438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26953.800438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::cpu.inst     13390330                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13390330                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  51669260559                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51669260559                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.117009                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117009                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      1774417                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1774417                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       396500                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       396500                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37140099838                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37140099838                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090863                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090863                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1377917                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1377917                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426406000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426406000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs              9.872403                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         63650159                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982305                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999965                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           1394513                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           1395025                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          63650159                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse           511.982305                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13772249                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          86814250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       837448                       # number of writebacks
-system.cpu.dcache.writebacks::total            837448                       # number of writebacks
-system.cpu.discardedOps                       2565798                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                  1069353                       # DTB accesses
-system.cpu.dtb.data_acv                           370                       # DTB access violations
-system.cpu.dtb.data_hits                     15629370                       # DTB hits
-system.cpu.dtb.data_misses                      21396                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.branchPred.BTBHitPct             51.388672                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  808188                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              32062                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                   770885                       # DTB read accesses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                      9240282                       # DTB read hits
+system.cpu.dtb.read_misses                      17901                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_hits                      9243246                       # DTB read hits
-system.cpu.dtb.read_misses                      19107                       # DTB read misses
-system.cpu.dtb.write_accesses                  298468                       # DTB write accesses
+system.cpu.dtb.read_accesses                   766280                       # DTB read accesses
+system.cpu.dtb.write_hits                     6385567                       # DTB write hits
+system.cpu.dtb.write_misses                      2310                       # DTB write misses
 system.cpu.dtb.write_acv                          159                       # DTB write access violations
-system.cpu.dtb.write_hits                     6386124                       # DTB write hits
-system.cpu.dtb.write_misses                      2289                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     20425038                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20425038                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.021807                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13727.021807                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.006480                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.006480                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     18964885                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18964885                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20043552072                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20043552072                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071488                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071488                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst      1460153                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1460153                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17115922928                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17115922928                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071488                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071488                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1460153                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1460153                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     20425038                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20425038                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.021807                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13727.021807                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.006480                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.006480                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      18964885                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18964885                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst  20043552072                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20043552072                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071488                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071488                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst      1460153                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1460153                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17115922928                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17115922928                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071488                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.071488                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1460153                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1460153                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     20425038                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20425038                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.021807                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13727.021807                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.006480                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.006480                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     18964885                       # number of overall hits
-system.cpu.icache.overall_hits::total        18964885                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst  20043552072                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20043552072                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071488                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071488                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst      1460153                       # number of overall misses
-system.cpu.icache.overall_misses::total       1460153                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17115922928                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17115922928                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071488                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.071488                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1460153                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1460153                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          386                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs             12.989850                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         21885191                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.631985                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995375                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995375                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements           1459466                       # number of replacements
-system.cpu.icache.tags.sampled_refs           1459977                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          21885191                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           509.631985                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18964882                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       31504045250                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        90671171                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.321596                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                 4018394                       # ITB accesses
-system.cpu.itb.fetch_acv                          700                       # ITB acv
-system.cpu.itb.fetch_hits                     4011544                       # ITB hits
-system.cpu.itb.fetch_misses                      6850                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.write_accesses                  298488                       # DTB write accesses
+system.cpu.dtb.data_hits                     15625849                       # DTB hits
+system.cpu.dtb.data_misses                      20211                       # DTB misses
+system.cpu.dtb.data_acv                           370                       # DTB access violations
+system.cpu.dtb.data_accesses                  1064768                       # DTB accesses
+system.cpu.itb.fetch_hits                     4001359                       # ITB hits
+system.cpu.itb.fetch_misses                      6809                       # ITB misses
+system.cpu.itb.fetch_acv                          657                       # ITB acv
+system.cpu.itb.fetch_accesses                 4008168                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175531     91.22%     93.43% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
-system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
-system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192418                       # number of callpals executed
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.numCycles                        176815826                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    56126572                       # Number of instructions committed
+system.cpu.committedOps                      56126572                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2538059                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5497                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3593513250                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.150305                       # CPI: cycles per instruction
+system.cpu.ipc                               0.317430                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211480                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6384                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0                    74792     40.94%     40.94% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6380                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211465                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74787     40.94%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1901      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105866     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182690                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73425     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105856     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182675                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73420     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1901      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73425     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148882                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1833909486500     97.33%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                80399500      0.00%     97.33% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               673524500      0.04%     97.37% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             49559388000      2.63%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1884222798500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981723                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73420     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148872                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1833844528000     97.33%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                80077500      0.00%     97.33% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               673181000      0.04%     97.37% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             49609971000      2.63%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1884207757500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981721                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693565                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814943                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel                1910
-system.cpu.kern.mode_good::user                  1740
-system.cpu.kern.mode_good::idle                   170
-system.cpu.kern.mode_switch::kernel              5873                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel     0.325217                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081107                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393449                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        36228247000      1.92%      1.92% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4082723500      0.22%      2.14% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1843911818000     97.86%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.kern.ipl_used::31                 0.693584                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814956                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -382,200 +540,75 @@ system.cpu.kern.syscall::132                        4      1.23%     98.77% # nu
 system.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304079                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304079                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69348.639186                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69348.639186                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.106925                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.106925                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       187390                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187390                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8092223358                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8092223358                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       116689                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116689                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6591190642                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6591190642                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383746                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383746                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116689                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116689                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      2551058                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2551058                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65542.886814                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65542.886814                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.655311                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.655311                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      2262409                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2262409                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18918888736                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  18918888736                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113149                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.113149                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst       288649                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288649                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15310420764                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15310420764                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113149                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113149                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288649                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288649                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333330000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333330000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           21                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12646.882353                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12646.882353                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15971.411765                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15971.411765                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       214997                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       214997                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809524                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst           17                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           17                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       271514                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       271514                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1887556500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887556500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       837448                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       837448                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       837448                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       837448                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      2855137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2855137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66638.489591                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66638.489591                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54032.958681                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54032.958681                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      2449799                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2449799                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27011112094                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27011112094                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.141968                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.141968                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       405338                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        405338                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21901611406                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21901611406                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.141968                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.141968                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       405338                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       405338                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      2855137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2855137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66638.489591                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66638.489591                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54032.958681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54032.958681                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits::cpu.inst      2449799                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2449799                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27011112094                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27011112094                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.141968                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.141968                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       405338                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       405338                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21901611406                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21901611406                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.141968                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141968                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       405338                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405338                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3220886500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3220886500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1457                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5165                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2777                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55533                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             7.369819                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        30249758                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 54473.589189                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10850.670788                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.831201                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165568                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996769                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           339425                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           404587                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         30249758                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        65324.259976                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2981733                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5872511750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        76620                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76620                       # number of writebacks
-system.cpu.numCycles                        174555159                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                      5529                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.quiesceCycles                   3593892488                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.tickCycles                        83883988                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         236368668                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2920246                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3660834                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6581080                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2696865499                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2193891072                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2193491412                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       237000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus        13952                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               125453578                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93445952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142932828                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      236378780                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        2558221                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2558187                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       837448                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       345631                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304081                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           17                       # Transaction distribution
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.data_through_bus                 2705924                       # Total data (bytes)
+system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175516     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6804      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
+system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rti                     5126      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
+system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
+system.cpu.kern.callpal::total                 192403                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5869                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2100                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1905                      
+system.cpu.kern.mode_good::user                  1735                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.324587                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle       0.080952                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392622                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        36214076000      1.92%      1.92% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4058025000      0.22%      2.14% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1843935646500     97.86%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.tickCycles                        85802593                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        91013233                       # Total number of cycles that the object has spent stopped
+system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
+system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
+system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
+system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
+system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
+system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
+system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
+system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
+system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
+system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
+system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
+system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
+system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
+system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
+system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
+system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
+system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
+system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
+system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
+system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
+system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
+system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
+system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
+system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
+system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
+system.iobus.throughput                       1436106                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51171                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51171                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5094                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
@@ -592,12 +625,31 @@ system.iobus.pkt_count_system.bridge.master::total        33098
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  116548                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20376                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        44316                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              2705924                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2705924                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy              4705000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
@@ -612,476 +664,425 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           380176812                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380105365                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23479000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            43191500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43180001                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.throughput                       1436095                       # Throughput (bytes/s)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44316                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2705924                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51171                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51171                       # Transaction distribution
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 301458.532177                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 301458.532177                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 249403.998099                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 249403.998099                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency::tsunami.ide  12526204929                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12526204929                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10363234929                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10363234929                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs    12.981557                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.blocked::no_mshrs                28683                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs        372350                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::tsunami.ide 300715.142289                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 300715.142289                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248660.810354                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 248660.810354                       # average overall mshr miss latency
-system.iocache.demand_miss_latency::tsunami.ide  12547339312                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12547339312                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10375372312                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10375372312                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::tsunami.ide 300715.142289                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 300715.142289                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248660.810354                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 248660.810354                       # average overall mshr miss latency
-system.iocache.overall_miss_latency::tsunami.ide  12547339312                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12547339312                       # number of overall miss cycles
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10375372312                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10375372312                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.tags.occ_blocks::tsunami.ide     1.296002                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.081000                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.081000                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.tagsinuse                1.296002                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1728023406000                       # Cycle when the warmup percentage was hit.
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.membus.data_through_bus               36171420                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       887021                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       920153                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1044833                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy            29924500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1588463750                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               21000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3825251579                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376658500                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.snoop_data_through_bus            35520                       # Total snoop data (bytes)
-system.membus.throughput                     19215838                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44316                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30817984                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30862300                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36171420                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq              295752                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295735                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9619                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9619                       # Transaction distribution
-system.membus.trans_dist::Writeback            118132                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              154                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             154                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158104                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158104                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           17                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      3337930.50                       # Average gap between requests
-system.physmem.avgMemAccLat                  35387.14                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       16637.14                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          15.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.16                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.01                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        25.04                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          558643                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             558643                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             13753305                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1407663                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15160967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4012500                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            13753305                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1407663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19173467                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4012500                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4012500                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples        65544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      551.049921                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     339.619427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     417.892498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14350     21.89%     21.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10693     16.31%     38.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5022      7.66%     45.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3000      4.58%     50.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2439      3.72%     54.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2123      3.24%     57.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1392      2.12%     59.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1695      2.59%     62.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        24830     37.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65544                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                 28559488                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  28566656                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7558528                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                7560448                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst      1052608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1052608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst          25914304                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28566656                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      7560448                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7560448                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     1774858406250                       # Time in different power states
-system.physmem.memoryStateTime::REF       62918180000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       46441683750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            152                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             404911                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                446354                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118132                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118132                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      88.38                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0               28089                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28214                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28576                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28273                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27773                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27528                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27276                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26988                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27824                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27526                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28068                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27422                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27509                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28403                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28310                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28463                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7815                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7669                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8056                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7732                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7316                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6956                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6791                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6409                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7232                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6875                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7393                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6865                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7044                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8010                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7992                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7947                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          6969                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        64.029703                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       16.504435                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2530.006276                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           6966     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6969                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    402867                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      3807                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1230                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1958                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      4351                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      3967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4001                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      2558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      2209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1643                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1639                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     1928                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     1884                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                     2114                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                     1233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      977                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      904                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      446354                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  446354                       # Read request sizes (log2)
-system.physmem.readReqs                        446354                       # Number of read requests accepted
-system.physmem.readRowHitRate                   90.24                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     402699                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                   2231210000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1884215033500                       # Total gap between requests
-system.physmem.totMemAccLat               15791226000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     7424188500                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          6969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.946764                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.727841                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        3.644099                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               5693     81.69%     81.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 31      0.44%     82.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                825     11.84%     93.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 64      0.92%     94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 11      0.16%     95.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 13      0.19%     95.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 18      0.26%     95.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 88      1.26%     96.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 18      0.26%     97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 42      0.60%     97.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 18      0.26%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                 17      0.24%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                 12      0.17%     98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                 10      0.14%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  5      0.07%     98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                 20      0.29%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                 11      0.16%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  4      0.06%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  5      0.07%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  3      0.04%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  1      0.01%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  1      0.01%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  4      0.06%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  6      0.09%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42                  2      0.03%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  5      0.07%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  3      0.04%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::45                  2      0.03%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.01%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  5      0.07%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48                  2      0.03%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49                  5      0.07%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  3      0.04%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::51                  1      0.01%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  3      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.01%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56                  5      0.07%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::57                  7      0.10%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::58                  3      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6969                       # Writes before turning the bus around for reads
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4777                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      875                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      972                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     1055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     2061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1878                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
-system.physmem.writeBursts                     118132                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118132                       # Write request sizes (log2)
-system.physmem.writeReqs                       118132                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  81.35                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     96101                       # Number of row buffer hits during writes
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.cpu.icache.tags.replacements           1458006                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.628197                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18953120                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1458517                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.994789                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       31559763000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.628197                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995368                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995368                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          386                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          21870509                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21870509                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18953123                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18953123                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18953123                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18953123                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18953123                       # number of overall hits
+system.cpu.icache.overall_hits::total        18953123                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1458693                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1458693                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1458693                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1458693                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1458693                       # number of overall misses
+system.cpu.icache.overall_misses::total       1458693                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20024605540                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20024605540                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20024605540                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20024605540                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20024605540                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20024605540                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20411816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20411816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20411816                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20411816                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20411816                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20411816                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071463                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071463                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.071463                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13727.772424                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13727.772424                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1458693                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1458693                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1458693                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1458693                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1458693                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1458693                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17099831460                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17099831460                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17099831460                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17099831460                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17099831460                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17099831460                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071463                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.071463                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071463                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.071463                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               125457945                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2557417                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2557383                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9619                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9619                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       838210                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       345773                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304222                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917325                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3663192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6580517                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93352448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143032604                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      236385052                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         236375068                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        13888                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2697678498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       234000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2191733540                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2194708666                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           339421                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65326.541432                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2981708                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           404583                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.369830                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5872511750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.831429                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.165375                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996804                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1468                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         30250697                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        30250697                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      2261599                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2261599                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       838210                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       838210                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.inst            4                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       187541                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187541                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      2449140                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2449140                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      2449140                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2449140                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       288654                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288654                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.inst           18                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       116680                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116680                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       405334                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        405334                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       405334                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       405334                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  18918477985                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  18918477985                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       214497                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       214497                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   8091487855                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8091487855                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  27009965840                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27009965840                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  27009965840                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27009965840                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      2550253                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2550253                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       838210                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       838210                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.inst           22                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           22                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       304221                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304221                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      2854474                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2854474                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2854474                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2854474                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113186                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.113186                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.818182                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818182                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.383537                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383537                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142000                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.142000                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142000                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.142000                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11916.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11916.500000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69347.684736                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69347.684736                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66636.319282                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66636.319282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66636.319282                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66636.319282                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        76620                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76620                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       288654                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288654                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst           18                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       116680                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116680                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       405334                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       405334                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       405334                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       405334                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  15309737015                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15309737015                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst       281515                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       281515                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6590751145                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6590751145                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  21900488160                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21900488160                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  21900488160                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21900488160                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1333191500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333191500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   1887604500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1887604500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3220796000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3220796000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113186                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.113186                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.818182                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.383537                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383537                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142000                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.142000                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142000                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.142000                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53038.367786                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53038.367786                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15639.722222                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15639.722222                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56485.697163                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56485.697163                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54030.720739                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54030.720739                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54030.720739                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54030.720739                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           1395313                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.982337                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13766743                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395825                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.862800                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          86814250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.982337                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999966                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999966                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63632966                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63632966                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst      7808132                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7808132                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      5576867                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576867                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       182710                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182710                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       198999                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       198999                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      13384999                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13384999                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     13384999                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13384999                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1201593                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201593                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       573675                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       573675                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        17309                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17309                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1775268                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1775268                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1775268                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1775268                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  31027712510                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31027712510                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20753893806                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20753893806                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    231648000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    231648000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  51781606316                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51781606316                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  51781606316                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51781606316                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst      9009725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9009725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      6150542                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6150542                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       200019                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200019                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       198999                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       198999                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     15160267                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15160267                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     15160267                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15160267                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.133366                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133366                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.093272                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093272                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.086537                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086537                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.117100                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117100                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.117100                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117100                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25822.148190                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25822.148190                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36177.092964                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36177.092964                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.095499                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.095499                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29168.331945                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29168.331945                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29168.331945                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29168.331945                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       838210                       # number of writebacks
+system.cpu.dcache.writebacks::total            838210                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       127240                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127240                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       269470                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       269470                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       396710                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       396710                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       396710                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       396710                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1074353                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074353                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       304205                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304205                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        17306                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17306                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1378558                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378558                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1378558                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378558                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  26912219745                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26912219745                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10275413589                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10275413589                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    196866500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196866500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  37187633334                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37187633334                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  37187633334                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37187633334                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   1423283000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423283000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   2003033000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2003033000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst   3426316000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3426316000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.119244                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119244                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.049460                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049460                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.086522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.090932                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090932                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.090932                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090932                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index e0d04ae07d479356cc8f2a89013a21d21e7eaafa..d5447172fb18653cefe1a43881376fe896c4b497 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1146785401000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                  81646                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 463904                       # Number of bytes of host memory used
-host_op_rate                                   105090                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   758.04                       # Real time elapsed on the host
-host_tick_rate                             1512825196                       # Simulator tick rate (ticks/s)
+sim_seconds                                  1.146775                       # Number of seconds simulated
+sim_ticks                                1146774863500                       # Number of ticks simulated
+final_tick                               1146774863500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    61891142                       # Number of instructions simulated
-sim_ops                                      79662361                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.146785                       # Number of seconds simulated
-sim_ticks                                1146785401000                       # Number of ticks simulated
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+host_inst_rate                                  52366                       # Simulator instruction rate (inst/s)
+host_op_rate                                    67406                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              970268509                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 448492                       # Number of bytes of host memory used
+host_seconds                                  1181.92                       # Real time elapsed on the host
+sim_insts                                    61892059                       # Number of instructions simulated
+sim_ops                                      79667620                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         2560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7022076                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3606712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             60963700                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       763904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       275840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1039744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4294592                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.inst         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.inst       3010344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7321936                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           40                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            109794                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6457684                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           67103                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.inst             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.inst           752586                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               823939                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43889738                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker          2232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           112                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst             6123326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           502                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             3145092                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53161001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         666132                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         240535                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             906668                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3744930                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.inst              14824                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.inst            2625052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6384807                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3744930                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43889738                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          112                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst            6138150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          502                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            5770144                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               59545808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6457684                       # Number of read requests accepted
+system.physmem.writeReqs                       823939                       # Number of write requests accepted
+system.physmem.readBursts                     6457684                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     823939                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                413268352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     23424                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7334336                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  60963700                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7321936                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      366                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709320                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          12375                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              403317                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              403674                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              403089                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              403454                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              406236                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              403730                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              403529                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              403381                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              403672                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              404158                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             403104                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             402562                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             403651                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             403575                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             403252                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             402934                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7008                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7418                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6865                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7615                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7300                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7325                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7167                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7323                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7753                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6901                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6492                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7387                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7157                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7029                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6775                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1146771945000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
+system.physmem.readPktSize::3                 6291456                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166119                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  67103                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    558746                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    398674                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    399850                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    441647                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    404684                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    430598                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1121698                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   1089151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   1417401                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     50859                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    42455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    39349                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    37752                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     8359                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     8007                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     7903                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      180                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6613                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6670                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       461513                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      911.356100                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     779.117173                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     292.189115                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24977      5.41%      5.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        21582      4.68%     10.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5972      1.29%     11.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2646      0.57%     11.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2555      0.55%     12.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1574      0.34%     12.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4102      0.89%     13.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          979      0.21%     13.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       397126     86.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         461513                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       968.839160                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    26148.924018                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          6658     99.89%     99.89% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.194149                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.165520                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.984786                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2686     40.30%     40.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 20      0.30%     40.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3941     59.13%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 15      0.23%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   165007028750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              286081741250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  32286590000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25553.49                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  44303.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         360.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           6.40                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.16                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        6.38                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         4.16                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.54                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6015984                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94420                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  82.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                       157488.51                       # Average gap between requests
+system.physmem.pageHitRate                      92.98                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     908124290750                       # Time in different power states
+system.physmem.memoryStateTime::REF       38293320000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      200357121750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.realview.nvmem.bytes_read::cpu0.inst          256                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          448                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          256                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            4                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst            7                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst          223                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          391                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              614                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst          223                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          391                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          614                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst          223                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          391                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             614                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     61651742                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7506663                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7506663                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767825                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767825                       # Transaction distribution
+system.membus.trans_dist::Writeback             67103                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33483                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17276                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           12375                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137796                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137454                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382664                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11280                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          874                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1976707                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4371551                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12582912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     12582912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               16954463                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        22560                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1748                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17953988                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     20369020                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     50331648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            70700668                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               70700668                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1725618000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy               16500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy            10203000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer5.occupancy              700000                       # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer6.occupancy          8808401000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         4909176600                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        15579623500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.l2c.tags.replacements                    73595                       # number of replacements
+system.l2c.tags.tagsinuse                53913.869309                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2430089                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   138750                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    17.514155                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   38825.506974                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    30.840279                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001297                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     8944.299229                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.867460                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     6105.354070                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.592430                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000471                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.136479                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000120                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.093160                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.822660                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65141                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2303                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8599                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54129                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000214                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.993973                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 23296068                       # Number of tag accesses
+system.l2c.tags.data_accesses                23296068                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        29004                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6772                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             959141                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        26476                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5085                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             968677                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1995155                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          576981                       # number of Writeback hits
+system.l2c.Writeback_hits::total               576981                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.inst             913                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.inst             959                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1872                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.inst           209                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.inst           100                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               309                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.inst            58748                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.inst            50778                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109526                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         29004                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6772                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             1017889                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         26476                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5085                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             1019455                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2104681                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        29004                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6772                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            1017889                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        26476                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5085                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            1019455                       # number of overall hits
+system.l2c.overall_hits::total                2104681                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           40                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            16374                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker            9                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             9914                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                26339                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.inst          4863                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.inst          4102                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8965                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.inst          683                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.inst          310                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             993                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.inst          92483                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.inst          47388                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139871                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           40                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst            108857                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker            9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             57302                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                166210                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           40                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst           108857                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker            9                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            57302                       # number of overall misses
+system.l2c.overall_misses::total               166210                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      3039250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst   1157856000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       661250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    747415749                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1909121749                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.inst      8211643                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.inst     13589417                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     21801060                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.inst       673971                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.inst      2091409                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2765380                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.inst   6321431326                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.inst   3362017496                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9683448822                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      3039250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   7479287326                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       661250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   4109433245                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     11592570571                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      3039250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   7479287326                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       661250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   4109433245                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11592570571                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        29044                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         6774                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         975515                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        26485                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         5085                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         978591                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2021494                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       576981                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           576981                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.inst         5776                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.inst         5061                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           10837                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.inst          892                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.inst          410                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1302                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.inst       151231                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.inst        98166                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249397                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        29044                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6774                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         1126746                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        26485                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5085                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         1076757                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2270891                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        29044                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6774                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        1126746                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        26485                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5085                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        1076757                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2270891                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.016785                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010131                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.013029                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.841932                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.810512                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.827258                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.765695                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.756098                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.762673                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.inst     0.611535                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.inst     0.482733                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.560837                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.096612                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.053217                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.073192                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001377                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000295                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.096612                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000340                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.053217                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.073192                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70713.081715                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75389.928283                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72482.696723                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1688.596134                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  3312.875914                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2431.796988                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst   986.780381                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  6746.480645                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2784.874119                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68352.360174                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70946.600321                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 69231.283268                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 69746.528915                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75981.250000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 68707.454054                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 73472.222222                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 71715.354525                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 69746.528915                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks::writebacks               67103                       # number of writebacks
+system.l2c.writebacks::total                    67103                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst            49                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst            19                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                68                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst             49                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             19                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 68                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst            49                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst            19                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                68                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           40                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        16325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            9                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         9895                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           26271                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.inst         4863                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.inst         4102                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8965                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          683                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst          310                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          993                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.inst        92483                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.inst        47388                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139871                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           40                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst       108808                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst        57283                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           166142                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           40                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst       108808                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker            9                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst        57283                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          166142                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    950227250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    622555749                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1576006999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     48716838                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     41086590                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     89803428                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6847181                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst      3100809                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      9947990                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   5160123162                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   2766953994                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7927077156                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   6110350412                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   3389509743                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9503084155                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2549250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   6110350412                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       549750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   3389509743                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9503084155                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156402291235                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst  10978060744                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167380351979                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   1364398990                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst  15414990793                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16779389783                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157766690225                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst  26393051537                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184159741762                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016735                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010111                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.012996                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.841932                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.810512                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.827258                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.765695                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.756098                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.762673                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.611535                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.482733                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.560837                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.073162                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001377                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000295                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.096568                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000340                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053200                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.073162                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58206.875957                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62916.194947                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 59990.369571                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10017.856878                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10016.233545                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.114110                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10025.155198                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.609677                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10018.116818                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55795.369549                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58389.338947                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56674.200914                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57198.566016                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.700237                       # BTB Hit Percentage
-system.cpu0.branchPred.BTBHits                3353058                       # Number of BTB hits
-system.cpu0.branchPred.BTBLookups             4676495                       # Number of BTB lookups
-system.cpu0.branchPred.RASInCorrect             70484                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.condIncorrect           650965                       # Number of conditional branches incorrect
-system.cpu0.branchPred.condPredicted          5175442                       # Number of conditional branches predicted
-system.cpu0.branchPred.lookups                6862341                       # Number of BP lookups
-system.cpu0.branchPred.usedRAS                 848882                       # Number of times the RAS was used to get a target.
-system.cpu0.committedInsts                   29915640                       # Number of instructions committed
-system.cpu0.committedOps                     39339363                       # Number of ops (including micro ops) committed
-system.cpu0.cpi                             14.502071                       # CPI: cycles per instruction
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       161256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       161256                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10306.777196                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10306.777196                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst  8288.517611                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8288.517611                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       152661                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       152661                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst     88586750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     88586750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.053300                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053300                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         8595                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8595                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           21                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total           21                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     71065750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71065750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.053170                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.053170                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         8574                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8574                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.inst      6911519                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6911519                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14955.771110                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14955.771110                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12252.616817                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12252.616817                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::cpu0.inst      6653819                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6653819                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   3854102215                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3854102215                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.037286                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037286                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::cpu0.inst       257700                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       257700                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        51318                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        51318                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   2528719564                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2528719564                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.029861                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029861                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       206382                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       206382                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170751064250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170751064250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       161153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       161153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst  6297.509524                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6297.509524                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst  4297.199471                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4297.199471                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       153593                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       153593                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst     47609172                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     47609172                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.046912                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046912                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.inst         7560                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7560                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst     32486828                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32486828                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.046912                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.046912                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst         7560                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7560                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::cpu0.inst      5819437                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5819437                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49213.556324                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 49213.556324                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42966.373247                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42966.373247                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::cpu0.inst      5512001                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5512001                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  15130018902                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  15130018902                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.052829                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.052829                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst       307436                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       307436                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       139625                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       139625                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   7210230061                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7210230061                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.028836                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028836                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       167811                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       167811                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   1513184500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1513184500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses::cpu0.inst     12730956                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12730956                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33592.128474                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33592.128474                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26026.541451                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.541451                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::cpu0.inst     12165820                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12165820                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency::cpu0.inst  18984121117                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  18984121117                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.044391                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044391                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::cpu0.inst       565136                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        565136                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits::cpu0.inst       190943                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       190943                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9738949625                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   9738949625                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.029392                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029392                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses::cpu0.inst       374193                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       374193                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses::cpu0.inst     12730956                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12730956                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33592.128474                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33592.128474                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26026.541451                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26026.541451                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::cpu0.inst     12165820                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12165820                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency::cpu0.inst  18984121117                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  18984121117                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.044391                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.044391                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::cpu0.inst       565136                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       565136                       # number of overall misses
-system.cpu0.dcache.overall_mshr_hits::cpu0.inst       190943                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       190943                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9738949625                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   9738949625                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.029392                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029392                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses::cpu0.inst       374193                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       374193                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172264248750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172264248750                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          364                       # Occupied blocks per task id
-system.cpu0.dcache.tags.avg_refs            37.525252                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.data_accesses        52581616                       # Number of data accesses
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst   495.504489                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.967782                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.967782                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.replacements           332602                       # number of replacements
-system.cpu0.dcache.tags.sampled_refs           332966                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.tag_accesses         52581616                       # Number of tag accesses
-system.cpu0.dcache.tags.tagsinuse          495.504489                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12494633                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        236260250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks::writebacks       306168                       # number of writebacks
-system.cpu0.dcache.writebacks::total           306168                       # number of writebacks
-system.cpu0.discardedOps                      1920081                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.dtb.accesses                     14321266                       # DTB accesses
-system.cpu0.dtb.align_faults                     1416                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.flush_entries                    1942                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.hits                         14297430                       # DTB hits
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.misses                          23836                       # DTB misses
-system.cpu0.dtb.perms_faults                      284                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.prefetch_faults                   167                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.read_accesses                 8272964                       # DTB read accesses
-system.cpu0.dtb.read_hits                     8250552                       # DTB read hits
-system.cpu0.dtb.read_misses                     22412                       # DTB read misses
-system.cpu0.dtb.write_accesses                6048302                       # DTB write accesses
-system.cpu0.dtb.write_hits                    6046878                       # DTB write hits
-system.cpu0.dtb.write_misses                     1424                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     12525310                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     12525310                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13777.726344                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13777.726344                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11772.390367                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.390367                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_hits::cpu0.inst     11740482                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       11740482                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10813145411                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  10813145411                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.062659                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.062659                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::cpu0.inst       784828                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       784828                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9239301587                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9239301587                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.062659                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.062659                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       784828                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       784828                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    171826250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    171826250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses::cpu0.inst     12525310                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     12525310                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13777.726344                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13777.726344                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11772.390367                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.390367                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits::cpu0.inst     11740482                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        11740482                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency::cpu0.inst  10813145411                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  10813145411                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.062659                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.062659                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses::cpu0.inst       784828                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        784828                       # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9239301587                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9239301587                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.062659                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.062659                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       784828                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       784828                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses::cpu0.inst     12525310                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     12525310                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13777.726344                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13777.726344                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11772.390367                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.390367                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::cpu0.inst     11740482                       # number of overall hits
-system.cpu0.icache.overall_hits::total       11740482                       # number of overall hits
-system.cpu0.icache.overall_miss_latency::cpu0.inst  10813145411                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  10813145411                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.062659                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.062659                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses::cpu0.inst       784828                       # number of overall misses
-system.cpu0.icache.overall_misses::total       784828                       # number of overall misses
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9239301587                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9239301587                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.062659                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.062659                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       784828                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       784828                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    171826250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    171826250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu0.icache.tags.avg_refs            14.959363                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.data_accesses        13310138                       # Number of data accesses
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.783510                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997624                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997624                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.replacements           784313                       # number of replacements
-system.cpu0.icache.tags.sampled_refs           784825                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.tag_accesses         13310138                       # Number of tag accesses
-system.cpu0.icache.tags.tagsinuse          510.783510                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           11740482                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10281183000                       # Cycle when the warmup percentage was hit.
-system.cpu0.idleCycles                       80090425                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.ipc                              0.068956                       # IPC: instructions per cycle
-system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.itb.accesses                     12532416                       # DTB accesses
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.flush_entries                    1298                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.hits                         12527520                       # DTB hits
-system.cpu0.itb.inst_accesses                12532416                       # ITB inst accesses
-system.cpu0.itb.inst_hits                    12527520                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4896                       # ITB inst misses
-system.cpu0.itb.misses                           4896                       # DTB misses
-system.cpu0.itb.perms_faults                     2037                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   50383                       # number of quiesce instructions executed
-system.cpu0.numCycles                       433838745                       # number of cpu cycles simulated
-system.cpu0.numFetchSuspends                    39517                       # Number of times Execute suspended instruction fetching
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.quiesceCycles                  1859796920                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.tickCycles                      353748320                       # Number of cycles that the CPU actually ticked
-system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            75.016066                       # BTB Hit Percentage
-system.cpu1.branchPred.BTBHits                3095670                       # Number of BTB hits
-system.cpu1.branchPred.BTBLookups             4126676                       # Number of BTB lookups
-system.cpu1.branchPred.RASInCorrect             63011                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.condIncorrect           435091                       # Number of conditional branches incorrect
-system.cpu1.branchPred.condPredicted          4929472                       # Number of conditional branches predicted
-system.cpu1.branchPred.lookups                6347852                       # Number of BP lookups
-system.cpu1.branchPred.usedRAS                 662563                       # Number of times the RAS was used to get a target.
-system.cpu1.committedInsts                   31975502                       # Number of instructions committed
-system.cpu1.committedOps                     40322998                       # Number of ops (including micro ops) committed
-system.cpu1.cpi                              4.679096                       # CPI: cycles per instruction
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        89293                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        89293                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst  8380.702313                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8380.702313                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst  6356.969903                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6356.969903                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        78530                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        78530                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     90201499                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     90201499                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.120536                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120536                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst        10763                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        10763                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           31                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total           31                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     68223001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68223001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.120189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst        10732                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        10732                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst      7361037                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7361037                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14987.876806                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14987.876806                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11879.325450                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11879.325450                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::cpu1.inst      7117762                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        7117762                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   3646175730                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3646175730                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.033049                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.033049                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::cpu1.inst       243275                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       243275                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        37480                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        37480                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2444705781                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2444705781                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.027957                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.027957                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       205795                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       205795                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst  11991518750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  11991518750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        89217                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89217                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst  5027.484214                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5027.484214                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst  3027.420473                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3027.420473                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        79145                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79145                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst     50636821                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     50636821                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.112893                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.112893                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        10072                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10072                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst     30492179                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30492179                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.112893                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.112893                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        10072                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10072                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::cpu1.inst      4649691                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4649691                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38966.175425                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 38966.175425                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.531262                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.531262                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::cpu1.inst      4425658                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4425658                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   8729709179                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   8729709179                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.048182                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.048182                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst       224033                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       224033                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        98146                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        98146                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   4132055880                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4132055880                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027074                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027074                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst       125887                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       125887                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst  24672578609                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  24672578609                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses::cpu1.inst     12010728                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12010728                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26483.357676                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26483.357676                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19828.515449                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19828.515449                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::cpu1.inst     11543420                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11543420                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency::cpu1.inst  12375884909                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  12375884909                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.038908                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.038908                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::cpu1.inst       467308                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        467308                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits::cpu1.inst       135626                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       135626                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   6576761661                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   6576761661                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.027615                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027615                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst       331682                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       331682                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses::cpu1.inst     12010728                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12010728                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26483.357676                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26483.357676                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19828.515449                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19828.515449                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::cpu1.inst     11543420                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11543420                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency::cpu1.inst  12375884909                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  12375884909                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.038908                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.038908                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::cpu1.inst       467308                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       467308                       # number of overall misses
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst       135626                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       135626                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   6576761661                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6576761661                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.027615                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.027615                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses::cpu1.inst       331682                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       331682                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst  36664097359                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total  36664097359                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu1.dcache.tags.avg_refs            38.928946                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.data_accesses        49080911                       # Number of data accesses
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst   448.678844                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.876326                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.876326                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.replacements           300905                       # number of replacements
-system.cpu1.dcache.tags.sampled_refs           301417                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.tag_accesses         49080911                       # Number of tag accesses
-system.cpu1.dcache.tags.tagsinuse          448.678844                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           11733846                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      76695286250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks::writebacks       270884                       # number of writebacks
-system.cpu1.dcache.writebacks::total           270884                       # number of writebacks
-system.cpu1.discardedOps                      1803588                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.dtb.accesses                     13158810                       # DTB accesses
-system.cpu1.dtb.align_faults                     2430                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.hits                         13135953                       # DTB hits
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.misses                          22857                       # DTB misses
-system.cpu1.dtb.perms_faults                      233                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.prefetch_faults                   234                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.read_accesses                 7605254                       # DTB read accesses
-system.cpu1.dtb.read_hits                     7584952                       # DTB read hits
-system.cpu1.dtb.read_misses                     20302                       # DTB read misses
-system.cpu1.dtb.write_accesses                5553556                       # DTB write accesses
-system.cpu1.dtb.write_hits                    5551001                       # DTB write hits
-system.cpu1.dtb.write_misses                     2555                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     11366597                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     11366597                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.195767                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.195767                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.787952                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11384.787952                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_hits::cpu1.inst     10566141                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       10566141                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10715861175                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  10715861175                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.070422                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.070422                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::cpu1.inst       800456                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       800456                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9113021825                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   9113021825                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.070422                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.070422                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       800456                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       800456                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5643750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5643750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses::cpu1.inst     11366597                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     11366597                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.195767                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13387.195767                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.787952                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11384.787952                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits::cpu1.inst     10566141                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        10566141                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency::cpu1.inst  10715861175                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  10715861175                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.070422                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.070422                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses::cpu1.inst       800456                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        800456                       # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9113021825                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   9113021825                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.070422                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.070422                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       800456                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       800456                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses::cpu1.inst     11366597                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     11366597                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.195767                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13387.195767                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.787952                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11384.787952                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::cpu1.inst     10566141                       # number of overall hits
-system.cpu1.icache.overall_hits::total       10566141                       # number of overall hits
-system.cpu1.icache.overall_miss_latency::cpu1.inst  10715861175                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  10715861175                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.070422                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.070422                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses::cpu1.inst       800456                       # number of overall misses
-system.cpu1.icache.overall_misses::total       800456                       # number of overall misses
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9113021825                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   9113021825                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.070422                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.070422                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       800456                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       800456                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5643750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      5643750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu1.icache.tags.avg_refs            13.200169                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.data_accesses        12167052                       # Number of data accesses
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.617049                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938705                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.938705                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.replacements           799943                       # number of replacements
-system.cpu1.icache.tags.sampled_refs           800455                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.tag_accesses         12167052                       # Number of tag accesses
-system.cpu1.icache.tags.tagsinuse          480.617049                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           10566141                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      82057257250                       # Cycle when the warmup percentage was hit.
-system.cpu1.idleCycles                       29483115                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.ipc                              0.213717                       # IPC: instructions per cycle
-system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.itb.accesses                     11372965                       # DTB accesses
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.flush_entries                    1189                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.hits                         11368674                       # DTB hits
-system.cpu1.itb.inst_accesses                11372965                       # ITB inst accesses
-system.cpu1.itb.inst_hits                    11368674                       # ITB inst hits
-system.cpu1.itb.inst_misses                      4291                       # ITB inst misses
-system.cpu1.itb.misses                           4291                       # DTB misses
-system.cpu1.itb.perms_faults                     1912                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   40529                       # number of quiesce instructions executed
-system.cpu1.numCycles                       149616439                       # number of cpu cycles simulated
-system.cpu1.numFetchSuspends                    40001                       # Number of times Execute suspended instruction fetching
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.quiesceCycles                  2144894120                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.tickCycles                      120133324                       # Number of cycles that the CPU actually ticked
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.iobus.data_through_bus                52721660                       # Total data (bytes)
+system.toL2Bus.throughput                   164548117                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            3298522                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3298521                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767825                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767825                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           576981                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           32938                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          50523                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260723                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260723                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1574360                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3288712                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        16464                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        66826                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1600801                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2571055                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        13478                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        62668                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               9194364                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     50355392                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     43867388                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        27096                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       116176                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     51198592                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     38125568                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        20340                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       105940                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          183816492                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             183816492                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4883152                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5169541990                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.5                       # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy        3546630183                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        2800512724                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy           9693493                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy          37783748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy        3604679924                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy        1938501968                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer8.occupancy           8396493                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer9.occupancy          36187242                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
+system.iobus.throughput                      45973854                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7474822                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7474822                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                7966                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               7966                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30566                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8050                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
@@ -784,10 +782,52 @@ system.iobus.pkt_count_system.bridge.master::total      2382664
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12582912                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12582912                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                14965576                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16100                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          273                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390012                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     50331648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total             52721660                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                52721660                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21429000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy              4031000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy               372000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy               299000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
+system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
@@ -808,8 +848,6 @@ system.iobus.reqLayer18.occupancy                8000                       # La
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
@@ -820,809 +858,771 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6291456000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               372000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               299000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374698000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         15868889251                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         15850285500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
-system.iobus.throughput                      45973431                       # Throughput (bytes/s)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16100                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1464                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          273                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390012                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             52721660                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq              7474822                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7474822                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7966                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7966                       # Transaction distribution
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722546651251                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 722546651251                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.cpu0.branchPred.lookups                6861856                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          5181081                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           652173                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4714052                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3350352                       # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct            71.071596                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 844036                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             70439                       # Number of incorrect RAS predictions.
+system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
+system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu0.dtb.read_hits                     8249046                       # DTB read hits
+system.cpu0.dtb.read_misses                     22426                       # DTB read misses
+system.cpu0.dtb.write_hits                    6048331                       # DTB write hits
+system.cpu0.dtb.write_misses                     1452                       # DTB write misses
+system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    1952                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1134                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   199                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.dtb.perms_faults                      288                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 8271472                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6049783                       # DTB write accesses
+system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu0.dtb.hits                         14297377                       # DTB hits
+system.cpu0.dtb.misses                          23878                       # DTB misses
+system.cpu0.dtb.accesses                     14321255                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
+system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.inst_hits                    12515958                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4886                       # ITB inst misses
+system.cpu0.itb.read_hits                           0                       # DTB read hits
+system.cpu0.itb.read_misses                         0                       # DTB read misses
+system.cpu0.itb.write_hits                          0                       # DTB write hits
+system.cpu0.itb.write_misses                        0                       # DTB write misses
+system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    1295                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu0.itb.perms_faults                     2118                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.read_accesses                       0                       # DTB read accesses
+system.cpu0.itb.write_accesses                      0                       # DTB write accesses
+system.cpu0.itb.inst_accesses                12520844                       # ITB inst accesses
+system.cpu0.itb.hits                         12515958                       # DTB hits
+system.cpu0.itb.misses                           4886                       # DTB misses
+system.cpu0.itb.accesses                     12520844                       # DTB accesses
+system.cpu0.numCycles                       433909161                       # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu0.committedInsts                   29915294                       # Number of instructions committed
+system.cpu0.committedOps                     39343022                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      1900672                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                    39481                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  1859706962                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                             14.504593                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.068944                       # IPC: instructions per cycle
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                   50347                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      353761855                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       80147306                       # Total number of cycles that the object has spent stopped
+system.cpu0.icache.tags.replacements           784713                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.784867                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           11728456                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           785225                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            14.936427                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10280766000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.784867                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997627                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997627                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         13298912                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        13298912                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     11728456                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       11728456                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     11728456                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        11728456                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     11728456                       # number of overall hits
+system.cpu0.icache.overall_hits::total       11728456                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       785228                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       785228                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       785228                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        785228                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       785228                       # number of overall misses
+system.cpu0.icache.overall_misses::total       785228                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10819127683                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10819127683                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10819127683                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10819127683                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10819127683                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10819127683                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     12513684                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     12513684                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     12513684                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     12513684                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     12513684                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     12513684                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.062750                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.062750                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.062750                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.062750                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.062750                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.062750                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13778.326401                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13778.326401                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       785228                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       785228                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       785228                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       785228                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       785228                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       785228                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9244507317                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9244507317                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9244507317                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9244507317                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9244507317                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9244507317                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    171313500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    171313500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    171313500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.062750                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.062750                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.062750                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.062750                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu0.dcache.tags.replacements           332522                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          495.116335                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12493941                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           332889                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.531853                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        236260250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst   495.116335                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst     0.967024                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.967024                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          367                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          367                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.716797                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         52581205                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        52581205                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.inst      6652234                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6652234                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.inst      5513247                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5513247                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst       152467                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       152467                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.inst       153686                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       153686                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.inst     12165481                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12165481                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.inst     12165481                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12165481                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.inst       257861                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       257861                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.inst       307489                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       307489                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst         8753                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         8753                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.inst         7461                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7461                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.inst       565350                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        565350                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.inst       565350                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       565350                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst   3878128215                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3878128215                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst  15135680350                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  15135680350                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst     89040000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     89040000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst     47241681                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     47241681                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.inst  19013808565                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  19013808565                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.inst  19013808565                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  19013808565                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.inst      6910095                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6910095                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.inst      5820736                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5820736                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst       161220                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       161220                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst       161147                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       161147                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.inst     12730831                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12730831                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.inst     12730831                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12730831                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst     0.037317                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.037317                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst     0.052826                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.052826                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst     0.054292                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054292                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst     0.046299                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046299                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.inst     0.044408                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.044408                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.inst     0.044408                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044408                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15039.607444                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15039.607444                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49223.485556                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 49223.485556                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10172.512282                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10172.512282                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst  6331.816244                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6331.816244                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33631.924587                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33631.924587                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33631.924587                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks       307804                       # number of writebacks
+system.cpu0.dcache.writebacks::total           307804                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst        51446                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        51446                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst       139700                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       139700                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst           20                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total           20                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.inst       191146                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       191146                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.inst       191146                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       191146                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst       206415                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       206415                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst       167789                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       167789                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst         8733                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8733                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst         7461                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7461                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.inst       374204                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       374204                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.inst       374204                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       374204                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst   2545797312                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2545797312                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst   7212492893                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7212492893                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst     71207000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71207000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst     32318319                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32318319                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst   9758290205                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9758290205                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst   9758290205                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9758290205                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170750199252                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170750199252                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst   1513150500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1513150500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172263349752                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172263349752                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst     0.029872                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029872                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst     0.028826                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028826                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst     0.054168                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.054168                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst     0.046299                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.046299                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029394                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst     0.029394                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029394                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.392980                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12333.392980                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 42985.493048                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42985.493048                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst  8153.784496                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8153.784496                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst  4331.633695                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4331.633695                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups                6346953                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          4931527                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           433505                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             4095605                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3083437                       # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct            75.286484                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 663921                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             63861                       # Number of incorrect RAS predictions.
+system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
+system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
+system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
+system.cpu1.dtb.read_hits                     7581512                       # DTB read hits
+system.cpu1.dtb.read_misses                     20239                       # DTB read misses
+system.cpu1.dtb.write_hits                    5551171                       # DTB write hits
+system.cpu1.dtb.write_misses                     2521                       # DTB write misses
+system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     2404                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   233                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.dtb.perms_faults                      237                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7601751                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5553692                       # DTB write accesses
+system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
+system.cpu1.dtb.hits                         13132683                       # DTB hits
+system.cpu1.dtb.misses                          22760                       # DTB misses
+system.cpu1.dtb.accesses                     13155443                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
+system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.inst_hits                    11349850                       # ITB inst hits
+system.cpu1.itb.inst_misses                      4207                       # ITB inst misses
+system.cpu1.itb.read_hits                           0                       # DTB read hits
+system.cpu1.itb.read_misses                         0                       # DTB read misses
+system.cpu1.itb.write_hits                          0                       # DTB write hits
+system.cpu1.itb.write_misses                        0                       # DTB write misses
+system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    1191                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
+system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
+system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
+system.cpu1.itb.perms_faults                     2046                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.read_accesses                       0                       # DTB read accesses
+system.cpu1.itb.write_accesses                      0                       # DTB write accesses
+system.cpu1.itb.inst_accesses                11354057                       # ITB inst accesses
+system.cpu1.itb.hits                         11349850                       # DTB hits
+system.cpu1.itb.misses                           4207                       # DTB misses
+system.cpu1.itb.accesses                     11354057                       # DTB accesses
+system.cpu1.numCycles                       149527233                       # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+system.cpu1.committedInsts                   31976765                       # Number of instructions committed
+system.cpu1.committedOps                     40324598                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1783017                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                    39969                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  2144960974                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              4.676121                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.213852                       # IPC: instructions per cycle
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                   40497                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      120083069                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       29444164                       # Total number of cycles that the object has spent stopped
+system.cpu1.icache.tags.replacements           800234                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          480.617194                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           10546899                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           800746                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            13.171341                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      82063984250                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.617194                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938705                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.938705                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         12148392                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        12148392                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     10546899                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       10546899                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     10546899                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        10546899                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     10546899                       # number of overall hits
+system.cpu1.icache.overall_hits::total       10546899                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       800747                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       800747                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       800747                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        800747                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       800747                       # number of overall misses
+system.cpu1.icache.overall_misses::total       800747                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10721128674                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  10721128674                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  10721128674                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  10721128674                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  10721128674                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  10721128674                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     11347646                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     11347646                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     11347646                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     11347646                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     11347646                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     11347646                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.070565                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.070565                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.070565                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.070565                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.070565                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.070565                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13388.908949                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13388.908949                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       800747                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       800747                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       800747                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       800747                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       800747                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       800747                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   9117705326                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   9117705326                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   9117705326                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   9117705326                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   9117705326                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   9117705326                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5654750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5654750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      5654750                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.070565                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.070565                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.070565                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.070565                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11386.499514                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11386.499514                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11386.499514                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dcache.tags.replacements           301108                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          446.775625                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11731236                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           301620                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.894092                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      76702840250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst   446.775625                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst     0.872609                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.872609                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         49070289                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        49070289                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst      7114972                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        7114972                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst      4425981                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4425981                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst        78462                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        78462                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst        79072                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        79072                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst     11540953                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11540953                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst     11540953                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11540953                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst       243175                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       243175                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst       224036                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       224036                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst        10782                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        10782                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst        10124                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10124                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst       467211                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        467211                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst       467211                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       467211                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst   3616409978                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3616409978                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst   8727689439                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   8727689439                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst     90341500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     90341500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst     50520310                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     50520310                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst  12344099417                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  12344099417                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst  12344099417                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  12344099417                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst      7358147                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7358147                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst      4650017                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4650017                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst        89244                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        89244                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst        89196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        89196                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst     12008164                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12008164                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst     12008164                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12008164                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst     0.033048                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.033048                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst     0.048180                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.048180                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst     0.120815                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120815                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst     0.113503                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113503                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst     0.038908                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.038908                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst     0.038908                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.038908                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.635563                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.635563                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38956.638393                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 38956.638393                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst  8378.918568                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8378.918568                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst  4990.153102                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  4990.153102                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26420.823604                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26420.823604                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26420.823604                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
+system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks       269177                       # number of writebacks
+system.cpu1.dcache.writebacks::total           269177                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst        37509                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        37509                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst        98167                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        98167                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst           30                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total           30                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst       135676                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       135676                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst       135676                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       135676                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst       205666                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       205666                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst       125869                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       125869                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst        10752                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        10752                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst        10124                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10124                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst       331535                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       331535                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst       331535                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       331535                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst   2422782037                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2422782037                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst   4131508096                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4131508096                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst     68345000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68345000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst     30271690                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30271690                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst   6554290133                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   6554290133                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst   6554290133                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   6554290133                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst  11992419500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  11992419500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst  24672512707                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  24672512707                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst  36664932207                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total  36664932207                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst     0.027951                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.027951                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst     0.027069                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027069                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst     0.120479                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120479                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst     0.113503                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113503                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027609                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst     0.027609                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.027609                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst  6356.491815                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6356.491815                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst  2990.091861                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  2990.091861                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.iocache.tags.replacements                    0                       # number of replacements
+system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 721880739500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722546651251                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 722546651251                       # number of overall MSHR uncacheable cycles
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.l2c.ReadExReq_accesses::cpu0.inst       151088                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.inst        98363                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249451                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68340.802831                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70836.135654                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 69186.818320                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55784.041664                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58278.521386                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56629.767918                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::cpu0.inst            58609                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.inst            50926                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109535                       # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency::cpu0.inst   6320089105                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.inst   3360253767                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9680342872                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::cpu0.inst     0.612087                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.inst     0.482265                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.560896                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::cpu0.inst          92479                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.inst          47437                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139916                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst   5158852389                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst   2764558219                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7923410608                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst     0.612087                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst     0.482265                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.560896                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses::cpu0.inst        92479                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.inst        47437                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139916                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        28623                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6686                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         972984                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        26977                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         5385                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         980230                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2020885                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75197.368421                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70701.604050                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        88575                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75547.349058                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 72536.539775                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58187.997185                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76175                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63048.000202                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60029.934536                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::cpu0.dtb.walker        28604                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6684                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             956588                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        26967                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5385                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             970309                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1994537                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1428750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst   1159223500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       885750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    749505250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1911192750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000664                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.016851                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000371                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010121                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.013038                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::cpu0.dtb.walker           19                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst            16396                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             9921                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                26348                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits::cpu0.inst            54                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            20                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                74                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1193250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    950908250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       761750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    624238250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1577226500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000664                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.016796                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000371                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010101                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.013001                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           19                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst        16342                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         9901                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           26274                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156403460492                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst  10977229000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167380689492                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::cpu0.inst          889                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.inst          428                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1317                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst   821.973412                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst  6364.211838                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2604.597194                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10035.706056                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.557632                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.044088                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_hits::cpu0.inst           212                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.inst           107                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               319                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_miss_latency::cpu0.inst       556476                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.inst      2042912                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      2599388                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::cpu0.inst     0.761530                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.inst     0.750000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.757783                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::cpu0.inst          677                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.inst          321                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             998                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst      6794173                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst      3210821                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     10004994                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst     0.761530                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst     0.750000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.757783                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst          677                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst          321                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          998                       # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::cpu0.inst         5825                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.inst         5183                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           11008                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst  1631.426752                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst  3342.816847                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2419.591886                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10026.163345                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10005.691697                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.735314                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::cpu0.inst             958                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.inst            1028                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1986                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency::cpu0.inst      7940154                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.inst     13889404                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     21829558                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::cpu0.inst     0.835536                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.inst     0.801659                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.819586                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::cpu0.inst          4867                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.inst          4155                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9022                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst     48797337                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst     41573649                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     90370986                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst     0.835536                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst     0.801659                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.819586                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses::cpu0.inst         4867                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.inst         4155                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         9022                       # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst   1364457493                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst  15414956890                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16779414383                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::writebacks       577052                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           577052                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::writebacks          577052                       # number of Writeback hits
-system.l2c.Writeback_hits::total               577052                       # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses::cpu0.dtb.walker        28623                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6686                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         1124072                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        26977                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5385                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         1078593                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2270336                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75197.368421                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 68696.327026                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        88575                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 71651.016720                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 69717.651578                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56145.051406                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76175                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59102.104521                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57167.321187                       # average overall mshr miss latency
-system.l2c.demand_hits::cpu0.dtb.walker         28604                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6684                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             1015197                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         26967                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5385                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1021235                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2104072                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency::cpu0.dtb.walker      1428750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   7479312605                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       885750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4109759017                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     11591535622                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000664                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.096858                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000371                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.053179                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.073233                       # miss rate for demand accesses
-system.l2c.demand_misses::cpu0.dtb.walker           19                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst            108875                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             57358                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                166264                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits::cpu0.inst             54                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             20                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 74                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1193250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   6109760639                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       761750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3388796469                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9500637108                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000664                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.096810                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000371                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.053160                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.073201                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           19                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst       108821                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        57338                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           166190                       # number of demand (read+write) MSHR misses
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses::cpu0.dtb.walker        28623                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6686                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        1124072                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        26977                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5385                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1078593                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2270336                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75197.368421                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 68696.327026                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        88575                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 71651.016720                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 69717.651578                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56145.051406                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76175                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59102.104521                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57167.321187                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits::cpu0.dtb.walker        28604                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6684                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            1015197                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        26967                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5385                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1021235                       # number of overall hits
-system.l2c.overall_hits::total                2104072                       # number of overall hits
-system.l2c.overall_miss_latency::cpu0.dtb.walker      1428750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   7479312605                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       885750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4109759017                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    11591535622                       # number of overall miss cycles
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000664                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.096858                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000371                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.053179                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.073233                       # miss rate for overall accesses
-system.l2c.overall_misses::cpu0.dtb.walker           19                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst           108875                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            57358                       # number of overall misses
-system.l2c.overall_misses::total               166264                       # number of overall misses
-system.l2c.overall_mshr_hits::cpu0.inst            54                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            20                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                74                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1193250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   6109760639                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       761750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3388796469                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9500637108                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000664                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.096810                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000371                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.053160                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.073201                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           19                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst       108821                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        57338                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          166190                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157767917985                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst  26392185890                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184160103875                       # number of overall MSHR uncacheable cycles
-system.l2c.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2318                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8665                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54076                       # Occupied blocks per task id
-system.l2c.tags.avg_refs                    17.496486                       # Average number of references to valid blocks.
-system.l2c.tags.data_accesses                23293968                       # Number of data accesses
-system.l2c.tags.occ_blocks::writebacks   38836.595678                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    12.172943                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001299                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     8927.165185                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.671671                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     6116.054658                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.592599                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000186                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.136218                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000132                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.093324                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.822459                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000122                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.l2c.tags.replacements                    73691                       # number of replacements
-system.l2c.tags.sampled_refs                   138862                       # Sample count of references to valid blocks.
-system.l2c.tags.tag_accesses                 23293968                       # Number of tag accesses
-system.l2c.tags.tagsinuse                53900.661434                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2429597                       # Total number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks::writebacks               67203                       # number of writebacks
-system.l2c.writebacks::total                    67203                       # number of writebacks
-system.membus.data_through_bus               70713692                       # Total data (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        11296                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          874                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1977013                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4371873                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12582912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     12582912                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               16954785                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1725804499                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               16500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            10159500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy              707500                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy          8809576499                       # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4910157489                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        15563933749                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     61662532                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        22592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1748                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17966980                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     20382044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total     50331648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            70713692                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq             7506677                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7506677                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767829                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767829                       # Transaction distribution
-system.membus.trans_dist::Writeback             67203                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33449                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          17313                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12389                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137872                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137547                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       157485.55                       # Average gap between requests
-system.physmem.avgMemAccLat                  44404.73                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       25654.73                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         360.38                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         4.16                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           6.40                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.39                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        23.53                       # Average write queue length when enqueuing
-system.physmem.busUtil                           2.87                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.82                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu0.inst         666071                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         241370                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             907441                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.clcd        43889334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker          1060                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           112                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst             6125781                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           558                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             3149416                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53166261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3750477                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43889334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst            6140605                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          558                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            5774444                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59556590                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3750477                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.inst              14824                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.inst            2625028                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6390329                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples       461405                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      911.601183                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     779.379075                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     292.108282                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24920      5.40%      5.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        21689      4.70%     10.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5921      1.28%     11.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2595      0.56%     11.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2392      0.52%     12.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1620      0.35%     12.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3961      0.86%     13.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          945      0.20%     13.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       397362     86.12%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         461405                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                413277056                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  60970292                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     21312                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7340288                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                7328336                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu0.inst       763840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       276800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1040640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         1216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7024956                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3611704                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60970292                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      4300992                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.inst         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.inst       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7328336                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     907580229250                       # Time in different power states
-system.physmem.memoryStateTime::REF       38293580000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      200908709500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                  709322                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          12389                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           19                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            109839                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56461                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6457787                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           67203                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.inst             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.inst           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               824039                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      92.98                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0              403322                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              403674                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              403179                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              403456                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              406212                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              403697                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              403585                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              403309                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              403688                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              404195                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             403096                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             402549                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             403605                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             403586                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             403320                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             402981                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7004                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7414                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6962                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7076                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7614                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7289                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7332                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7122                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7331                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7785                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6895                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6483                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7357                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7159                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7082                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6787                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          6667                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       968.567572                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    25247.895153                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-65535          6659     99.88%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-262143            4      0.06%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::589824-655359            1      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-851967            2      0.03%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6667                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    559033                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    398819                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    399992                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    446086                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    404802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                    432883                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1116979                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   1080646                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   1404200                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     57088                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    46892                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    43646                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    42022                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     8400                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     7955                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     7847                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                     6457787                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
-system.physmem.readPktSize::3                 6291456                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166222                       # Read request sizes (log2)
-system.physmem.readReqs                       6457787                       # Number of read requests accepted
-system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
-system.physmem.readRowHits                    6016258                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      333                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                  32287270000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1146782404500                       # Total gap between requests
-system.physmem.totMemAccLat              286741508250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                   165664245750                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          6667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.202940                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.174263                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.985830                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2664     39.96%     39.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 13      0.19%     40.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3969     59.53%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 17      0.25%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  3      0.04%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6667                       # Writes before turning the bus around for reads
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4002                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6598                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                     824039                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  67203                       # Write request sizes (log2)
-system.physmem.writeReqs                       824039                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  82.36                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     94483                       # Number of row buffer hits during writes
-system.realview.nvmem.bw_inst_read::cpu0.inst          223                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          391                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          614                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.inst          223                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          391                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              614                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst          223                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          391                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             614                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu0.inst          256                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          704                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.inst          256                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            4                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst            7                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             11                       # Number of read requests responded to by this memory
-system.toL2Bus.data_through_bus             183769016                       # Total data (bytes)
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1573579                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3284792                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        16388                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        66250                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1600218                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2575101                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        13938                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        63483                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               9193749                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.reqLayer0.occupancy         5169689504                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.5                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3544874662                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2799461047                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           9704495                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          37627749                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        3603369425                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        1938898298                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           8556493                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          36509744                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_data_through_bus         4881844                       # Total snoop data (bytes)
-system.toL2Bus.throughput                   164504065                       # Throughput (bytes/s)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     50330560                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     43616868                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26744                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       114492                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     51179904                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     38371000                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        21540                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       107908                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          183769016                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.trans_dist::ReadReq            3298101                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3298100                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767829                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767829                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           577052                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           33066                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         17632                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          50698                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           260633                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          260633                       # Transaction distribution
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index cd537ca0cfbcf06f1db2109790a3b85b93c9e14a..4491c3f1309a4b65794c263a73f8062724fd4fdf 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               2567690995500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                  83247                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 453632                       # Number of bytes of host memory used
-host_op_rate                                   107007                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   727.87                       # Real time elapsed on the host
-host_tick_rate                             3527658330                       # Simulator tick rate (ticks/s)
+sim_seconds                                  2.567677                       # Number of seconds simulated
+sim_ticks                                2567677478000                       # Number of ticks simulated
+final_tick                               2567677478000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    60593069                       # Number of instructions simulated
-sim_ops                                      77887632                       # Number of ops (including micro ops) simulated
-sim_seconds                                  2.567691                       # Number of seconds simulated
-sim_ticks                                2567690995500                       # Number of ticks simulated
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
+host_inst_rate                                  53140                       # Simulator instruction rate (inst/s)
+host_op_rate                                    68307                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2251849348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 443244                       # Number of bytes of host memory used
+host_seconds                                  1140.25                       # Real time elapsed on the host
+sim_insts                                    60592948                       # Number of instructions simulated
+sim_ops                                      77887482                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10106264                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131218072                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1017856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1017856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3829760                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.inst        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6845832                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             157946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15296782                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59840                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.inst            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813858                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47167344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            449                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3935955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51103798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          396411                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             396411                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1491527                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.inst             1174630                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2666157                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1491527                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47167344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5110586                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53769956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15296782                       # Number of read requests accepted
+system.physmem.writeReqs                       813858                       # Number of write requests accepted
+system.physmem.readBursts                    15296782                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813858                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                978883904                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    110144                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6853696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131218072                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6845832                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1721                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706743                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4671                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955926                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              955615                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              955732                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              955955                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              957630                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              955653                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              955569                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              955430                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956341                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              955977                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             955547                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             955151                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956306                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             956026                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             956165                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             956038                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6624                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6445                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6544                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6594                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6491                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6747                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6783                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6690                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7075                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6811                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6482                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6150                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7106                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6684                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7011                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6852                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2567675574500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
+system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157928                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  59840                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1112326                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    958648                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    963944                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1085542                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    974308                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1043218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2679684                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2578598                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3358182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                    142716                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                   121801                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                   111705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                   108393                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19289                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    18414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    18153                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      135                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1015088                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      971.085857                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     904.509360                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     205.145024                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22501      2.22%      2.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22772      2.24%      4.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8563      0.84%      5.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2455      0.24%      5.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2778      0.27%      5.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1897      0.19%      6.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8457      0.83%      6.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          971      0.10%      6.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       944694     93.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1015088                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6216                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2460.593951                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    115853.550339                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         6211     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6216                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6216                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.227960                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.199911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.974162                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2395     38.53%     38.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.26%     38.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               3798     61.10%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  7      0.11%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6216                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   396370290250                       # Total ticks spent queuing
+system.physmem.totMemAccLat              683152684000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76475305000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25914.92                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  44664.92                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         381.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.67                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.10                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         6.49                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        27.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14297424                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89638                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  83.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159377.63                       # Average gap between requests
+system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     2210132306750                       # Time in different power states
+system.physmem.memoryStateTime::REF       85740200000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      271799415750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.realview.nvmem.bytes_read::cpu.inst          256                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           256                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          256                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          256                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            4                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              4                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst           100                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              100                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst          100                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          100                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst          100                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             100                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     54704015                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16349240                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16349240                       # Transaction distribution
+system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
+system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
+system.membus.trans_dist::Writeback             59840                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4671                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131634                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131634                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383068                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            8                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3800                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893150                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280028                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34557660                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390502                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16953376                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19351738                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           140462266                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140462266                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1731218500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.reqLayer1.occupancy                6000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer2.occupancy             3525000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.reqLayer6.occupancy         17560732500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         4805026968                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37408380500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.037327                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 6285951                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups              8848800                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect             141766                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           1083327                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted           9899581                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                12901223                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 1514142                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    60593069                       # Number of instructions committed
-system.cpu.committedOps                      77887632                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               9.521608                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       247603                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247603                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13892.781561                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13892.781561                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11890.018527                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.018527                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       236735                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236735                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    150986750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    150986750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.043893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst        10868                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        10868                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst           73                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           73                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    128352750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    128352750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.043598                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.043598                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        10795                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        10795                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::cpu.inst     13864450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13864450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15150.498583                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15150.498583                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12786.142134                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12786.142134                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     13401466                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13401466                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   7014438436                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7014438436                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.033394                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.033394                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst       462984                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        462984                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        82872                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        82872                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   4860166059                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4860166059                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.027416                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027416                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       380112                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       380112                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182581857500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182581857500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       247602                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247602                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       247602                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247602                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst     10222557                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222557                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46293.122518                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46293.122518                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.604187                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.604187                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::cpu.inst      9749254                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9749254                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21910673767                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21910673767                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.046300                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046300                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       473303                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       473303                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       222786                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       222786                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10668668321                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10668668321                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.024506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024506                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       250517                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250517                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst  26058222680                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26058222680                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     24087007                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24087007                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30893.424989                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30893.424989                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24624.358188                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24624.358188                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      23150720                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23150720                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  28925112203                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28925112203                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.038871                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.038871                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst       936287                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         936287                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       305658                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       305658                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  15528834380                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15528834380                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.026181                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026181                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       630629                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       630629                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     24087007                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24087007                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30893.424989                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30893.424989                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24624.358188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24624.358188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::cpu.inst     23150720                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23150720                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  28925112203                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28925112203                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.038871                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038871                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst       936287                       # number of overall misses
-system.cpu.dcache.overall_misses::total        936287                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       305658                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       305658                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  15528834380                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15528834380                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.026181                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026181                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       630629                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       630629                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640080180                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640080180                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          341                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             37.024295                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         98967296                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959208                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999920                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999920                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements            637936                       # number of replacements
-system.cpu.dcache.tags.sampled_refs            638448                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          98967296                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse           511.959208                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23638087                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         227414250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       603000                       # number of writebacks
-system.cpu.dcache.writebacks::total            603000                       # number of writebacks
-system.cpu.discardedOps                       3607979                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                      26805017                       # DTB accesses
-system.cpu.dtb.align_faults                      1584                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                     3457                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                          26758984                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.inst_hits                            0                       # ITB inst hits
-system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                           46033                       # DTB misses
-system.cpu.dtb.perms_faults                       524                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                    266                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                 15458164                       # DTB read accesses
-system.cpu.dtb.read_hits                     15416095                       # DTB read hits
-system.cpu.dtb.read_misses                      42069                       # DTB read misses
-system.cpu.dtb.write_accesses                11346853                       # DTB write accesses
-system.cpu.dtb.write_hits                    11342889                       # DTB write hits
-system.cpu.dtb.write_misses                      3964                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     23332180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23332180                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.944355                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13520.944355                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11517.182541                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11517.182541                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_hits::cpu.inst     21786211                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        21786211                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20902960824                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20902960824                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.066259                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.066259                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst      1545969                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1545969                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17805207176                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  17805207176                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.066259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.066259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1545969                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1545969                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    172412750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    172412750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     23332180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23332180                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.944355                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13520.944355                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11517.182541                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11517.182541                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      21786211                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         21786211                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst  20902960824                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20902960824                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.066259                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.066259                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst      1545969                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1545969                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17805207176                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  17805207176                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.066259                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.066259                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1545969                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1545969                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     23332180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23332180                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.944355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13520.944355                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11517.182541                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11517.182541                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::cpu.inst     21786211                       # number of overall hits
-system.cpu.icache.overall_hits::total        21786211                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst  20902960824                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20902960824                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.066259                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.066259                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst      1545969                       # number of overall misses
-system.cpu.icache.overall_misses::total       1545969                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17805207176                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  17805207176                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.066259                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.066259                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1545969                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1545969                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    172412750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    172412750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          181                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs             14.092278                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         24878148                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.467492                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998960                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998960                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements           1545456                       # number of replacements
-system.cpu.icache.tags.sampled_refs           1545968                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          24878148                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           511.467492                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            21786211                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       10068892000                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                       106196788                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.105024                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                      23345804                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                     2396                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                          23336489                       # DTB hits
-system.cpu.itb.inst_accesses                 23345804                       # ITB inst accesses
-system.cpu.itb.inst_hits                     23336489                       # ITB inst hits
-system.cpu.itb.inst_misses                       9315                       # ITB inst misses
-system.cpu.itb.misses                            9315                       # DTB misses
-system.cpu.itb.perms_faults                      4052                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82977                       # number of quiesce instructions executed
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       247542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69059.848663                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69059.848663                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56515.321009                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56515.321009                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       114197                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       114197                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9208785520                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9208785520                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.538676                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.538676                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       133345                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133345                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7536035480                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7536035480                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.538676                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.538676                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       133345                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133345                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52818                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11330                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1934916                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1999064                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85107.142857                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71955.193483                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71966.894361                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59447.036018                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59458.945900                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52797                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11328                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1910857                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1974982                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1787250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1731170000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1733106750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000398                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000177                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012434                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.012047                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        24059                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        24082                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1528250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1426015500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1427668750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000398                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000177                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012397                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012011                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        23988                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        24011                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167311975000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167311975000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2976                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2976                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   126.265763                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   126.265763                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10004.558983                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10004.558983                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       372484                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       372484                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.991263                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991263                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2950                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2950                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     29513449                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29513449                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.991263                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991263                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2950                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2950                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst  16707831820                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16707831820                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       603000                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       603000                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       603000                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       603000                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52818                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        11330                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      2182458                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2246606                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85107.142857                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69502.398414                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69504.546679                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.309115                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56964.489629                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        52797                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        11328                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      2025054                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2089179                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1787250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  10939955520                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10941892270                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000398                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000177                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.072122                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.070073                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           21                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       157404                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        157427                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1528250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8962050980                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8963704230                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000398                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000177                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.072090                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.070042                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       157333                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       157356                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52818                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        11330                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      2182458                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2246606                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85107.142857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69502.398414                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69504.546679                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.309115                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56964.489629                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        52797                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        11328                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      2025054                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2089179                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1787250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  10939955520                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10941892270                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000398                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000177                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.072122                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.070073                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           21                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       157404                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       157427                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           71                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1528250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8962050980                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8963704230                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000398                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000177                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.072090                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.070042                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       157333                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       157356                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184019806820                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184019806820                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2431                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6707                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56131                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs            18.629243                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        23223720                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 36351.350875                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    12.813342                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000576                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 15263.969553                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.554678                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000196                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.232910                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.787783                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           13                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65377                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000198                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997574                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements            65515                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           130905                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         23223720                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        51628.134347                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2438661                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2525287108000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        59837                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59837                       # number of writebacks
-system.cpu.numCycles                        576943440                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                     77491                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.quiesceCycles                   4560354752                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.tickCycles                       470746652                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         184089158                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3094634                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5780828                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29817                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       125263                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9030542                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3400418424                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2325892574                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2551470440                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      18491990                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      72446749                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus       232512                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                71784989                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     98965568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84866998                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        45320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       211272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      184089158                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        3214260                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3214259                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq        763365                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp       763365                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       603000                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2976                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2976                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247542                       # Transaction distribution
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.iobus.data_through_bus               123501026                       # Total data (bytes)
+system.iobus.throughput                      48098342                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322172                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322172                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8178                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8178                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7942                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7944                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          524                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1032                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -649,14 +352,56 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383066                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383068                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32660698                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32660700                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1048                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2064                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390502                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            123501030                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123501030                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3976000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3977000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy               524000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer3.occupancy               522000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
@@ -677,8 +422,6 @@ system.iobus.reqLayer18.occupancy                8000                       # La
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               524000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
@@ -689,386 +432,641 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               522000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374888000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374890000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         38216821000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         38224979500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
-system.iobus.throughput                      48098087                       # Throughput (bytes/s)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15884                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1048                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2064                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390498                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123501026                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.trans_dist::ReadReq             16322171                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322171                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8178                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8178                       # Transaction distribution
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738144017000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1738144017000                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                12907759                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9898849                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1085572                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8888360                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6291175                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             70.779930                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1515479                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             141893                       # Number of incorrect RAS predictions.
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.read_hits                     15416418                       # DTB read hits
+system.cpu.dtb.read_misses                      42733                       # DTB read misses
+system.cpu.dtb.write_hits                    11344011                       # DTB write hits
+system.cpu.dtb.write_misses                      3796                       # DTB write misses
+system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                     3452                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1264                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    262                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                       531                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 15459151                       # DTB read accesses
+system.cpu.dtb.write_accesses                11347807                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                          26760429                       # DTB hits
+system.cpu.dtb.misses                           46529                       # DTB misses
+system.cpu.dtb.accesses                      26806958                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                     23352687                       # ITB inst hits
+system.cpu.itb.inst_misses                       9286                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                     2392                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                      4189                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                 23361973                       # ITB inst accesses
+system.cpu.itb.hits                          23352687                       # DTB hits
+system.cpu.itb.misses                            9286                       # DTB misses
+system.cpu.itb.accesses                      23361973                       # DTB accesses
+system.cpu.numCycles                        576983411                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    60592948                       # Number of instructions committed
+system.cpu.committedOps                      77887482                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       3584241                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                     77491                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   4560301069                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               9.522287                       # CPI: cycles per instruction
+system.cpu.ipc                               0.105017                       # IPC: instructions per cycle
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                    82977                       # number of quiesce instructions executed
+system.cpu.tickCycles                       470832364                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       106151047                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements           1545254                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.467506                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            21802506                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1545766                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             14.104661                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       10068892000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.467506                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998960                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998960                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          24894039                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         24894039                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     21802506                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        21802506                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      21802506                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         21802506                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     21802506                       # number of overall hits
+system.cpu.icache.overall_hits::total        21802506                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1545767                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1545767                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1545767                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1545767                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1545767                       # number of overall misses
+system.cpu.icache.overall_misses::total       1545767                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  20898816329                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  20898816329                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  20898816329                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  20898816329                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  20898816329                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  20898816329                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     23348273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     23348273                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     23348273                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     23348273                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     23348273                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     23348273                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.066205                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.066205                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.066205                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.066205                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.066205                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.066205                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13520.030075                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13520.030075                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1545767                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1545767                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1545767                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1545767                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1545767                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1545767                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  17801487671                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  17801487671                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  17801487671                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  17801487671                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  17801487671                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  17801487671                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    172412750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    172412750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    172412750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    172412750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.066205                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.066205                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.066205                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.066205                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                71776562                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        3214470                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3214469                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq        763365                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp       763365                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       602969                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247546                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3094256                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5780457                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        29847                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       126652                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9031212                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     98954304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     84855034                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        45620                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214364                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      184069322                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         184069322                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       229740                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3400466435                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2325579079                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2551211790                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy      18447489                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy      73062749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements            65493                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51631.050557                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2439202                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           130882                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            18.636650                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2525290748000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.573566                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000576                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.554876                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000207                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.232744                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.787827                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65379                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2430                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6701                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56138                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000153                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997604                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         23227461                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        23227461                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53573                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11403                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1910560                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1975536                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       602969                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       602969                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.inst           25                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           25                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       114177                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       114177                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53573                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        11403                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      2024737                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2089713                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53573                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        11403                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      2024737                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2089713                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           18                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        24020                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        24040                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2936                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2936                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       133369                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133369                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           18                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst       157389                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        157409                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           18                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst       157389                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       157409                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1388250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1729894000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1731431750                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       394983                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       394983                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9208617265                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9208617265                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1388250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  10938511265                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10940049015                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1388250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  10938511265                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10940049015                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53591                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11405                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1934580                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1999576                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       602969                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       602969                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2961                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2961                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       247546                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247546                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53591                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        11405                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      2182126                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2247122                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53591                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        11405                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2182126                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2247122                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000336                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000175                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012416                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.012023                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.991557                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991557                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.538765                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.538765                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000336                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000175                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.072126                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.070049                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000336                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000175                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.072126                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.070049                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        77125                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72018.900916                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72022.951331                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   134.530995                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   134.530995                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69046.159640                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69046.159640                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        77125                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69499.846018                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69500.784676                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        77125                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69499.846018                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69500.784676                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        59840                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59840                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           70                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           70                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           18                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        23950                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        23970                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2936                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2936                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       133369                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133369                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           18                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       157319                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       157339                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           18                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       157319                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       157339                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1165250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1425512750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426803000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     29363936                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29363936                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7535729235                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7535729235                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1165250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8961241985                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8962532235                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1165250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8961241985                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8962532235                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167312402000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167312402000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst  16707876361                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16707876361                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184020278361                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184020278361                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000336                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000175                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012380                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.011988                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.991557                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991557                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.538765                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.538765                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000336                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000175                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.072094                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.070018                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000336                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000175                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.072094                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.070018                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59520.365344                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59524.530663                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.340599                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.340599                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56502.854749                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56502.854749                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements            637780                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.959208                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            23638258                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            638292                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.033612                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         227414250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   511.959208                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999920                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999920                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          98967232                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         98967232                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     13401610                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13401610                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      9749262                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9749262                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst       236772                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236772                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst       247602                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247602                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      23150872                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23150872                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     23150872                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23150872                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst       462868                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        462868                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       473290                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       473290                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.inst        10831                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        10831                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.inst       936158                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         936158                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       936158                       # number of overall misses
+system.cpu.dcache.overall_misses::total        936158                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   7014286436                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7014286436                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21912161323                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21912161323                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    150765000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    150765000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  28926447759                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  28926447759                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  28926447759                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  28926447759                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     13864478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13864478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     10222552                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222552                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       247603                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247603                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst       247602                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247602                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     24087030                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24087030                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     24087030                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24087030                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.033385                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033385                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.046299                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046299                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.043743                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.043743                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.038866                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.038866                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.038866                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.038866                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30899.108654                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30899.108654                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       602969                       # number of writebacks
+system.cpu.dcache.writebacks::total            602969                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        82884                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        82884                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       222784                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       222784                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst           68                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           68                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       305668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       305668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       305668                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       305668                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       379984                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       379984                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       250506                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250506                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst        10763                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        10763                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       630490                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       630490                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       630490                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       630490                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   4859150309                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4859150309                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  10668108512                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10668108512                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst    128265000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    128265000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  15527258821                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15527258821                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  15527258821                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15527258821                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst  26058245639                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26058245639                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.027407                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027407                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.024505                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024505                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.043469                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.043469                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.026175                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026175                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.026175                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026175                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.iocache.tags.replacements                    0                       # number of replacements
+system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1738541884500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738144017000                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1738144017000                       # number of overall MSHR uncacheable cycles
-system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
-system.iocache.tags.data_accesses                   0                       # Number of data accesses
-system.iocache.tags.replacements                    0                       # number of replacements
-system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
-system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
-system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
-system.membus.data_through_bus              140463478                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            8                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893209                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280085                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34557717                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1731044000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                6000                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3530500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17560934000                       # Layer occupancy (ticks)
-system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4805612001                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        37417137000                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     54704199                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390498                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7600                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16954592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19352950                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           140463478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq            16349280                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16349280                       # Transaction distribution
-system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
-system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
-system.membus.trans_dist::Writeback             59837                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4680                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4680                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131615                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131615                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       159378.28                       # Average gap between requests
-system.physmem.avgMemAccLat                  44638.69                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       25888.69                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         381.23                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.10                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         6.57                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           2.67                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        25.93                       # Average write queue length when enqueuing
-system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          396534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             396534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.clcd        47167096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              3936408                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51104078                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1491444                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47167096                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5111032                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53770146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1491444                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst             1174624                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2666068                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples      1015061                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      971.117866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     904.579267                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     205.091565                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22463      2.21%      2.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22781      2.24%      4.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8586      0.85%      5.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2483      0.24%      5.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2672      0.26%      5.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1833      0.18%      5.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8618      0.85%      6.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          926      0.09%      6.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151       944699     93.07%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1015061                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                978888704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                 131219480                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                    106752                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6855168                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                6845640                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst      1018176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1018176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10107480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131219480                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      3829568                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.inst        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6845640                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     2210491886500                       # Time in different power states
-system.physmem.memoryStateTime::REF       85740720000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      271454888500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                  706728                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4680                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             157965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15296804                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59837                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.inst            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813855                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      93.41                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0              955934                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              955610                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              955719                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              955960                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              957705                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              955718                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              955569                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              955478                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956345                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              955973                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             955562                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             955146                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956303                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             956034                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             956157                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             955923                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6634                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6445                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6533                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6602                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6504                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6748                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6784                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6699                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7075                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6807                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6488                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6148                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7101                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6684                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7006                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6854                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          6216                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      2460.607465                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    89585.482628                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-262143         6210     99.90%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::786432-1.04858e+06            2      0.03%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6216                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                   1112302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    958564                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    963836                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1083179                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    974176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1042396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2682768                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                   2583039                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                   3365419                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                    138919                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                   118710                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                   109585                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                   106194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    19284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    18426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    18172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                    15296804                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
-system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157950                       # Read request sizes (log2)
-system.physmem.readReqs                      15296804                       # Number of read requests accepted
-system.physmem.readRowHitRate                   93.48                       # Row buffer hit rate for reads
-system.physmem.readRowHits                   14297551                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                     1668                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                  76475680000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    2567689117500                       # Total gap between requests
-system.physmem.totMemAccLat              682754832250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                   395971032250                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          6216                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.231660                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.203648                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.973536                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2382     38.32%     38.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 22      0.35%     38.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               3802     61.16%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 10      0.16%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6216                       # Writes before turning the bus around for reads
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     6220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     6225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                     813855                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59837                       # Write request sizes (log2)
-system.physmem.writeReqs                       813855                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  83.67                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     89636                       # Number of row buffer hits during writes
-system.realview.nvmem.bw_inst_read::cpu.inst          100                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          100                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu.inst           100                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              100                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst          100                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             100                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_inst_read::cpu.inst          256                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          256                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_read::cpu.inst          256                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           256                       # Number of bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            4                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              4                       # Number of read requests responded to by this memory
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3677da8b63ec77da466802318196b1bed0180504..d97d6a9aa061dd0bfb109a451d1a2d1d077d607f 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               409828126500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 259766                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 250424                       # Number of bytes of host memory used
-host_op_rate                                   259766                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  2355.59                       # Real time elapsed on the host
-host_tick_rate                              173981398                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.409306                       # Number of seconds simulated
+sim_ticks                                409306011500                       # Number of ticks simulated
+final_tick                               409306011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 215743                       # Simulator instruction rate (inst/s)
+host_op_rate                                   215743                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              144312578                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243356                       # Number of bytes of host memory used
+host_seconds                                  2836.25                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.409828                       # Number of seconds simulated
-sim_ticks                                409828126500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.066276                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                67266528                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             71509717                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect            1120898                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           6389580                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          87724444                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               123843348                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                14941692                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                   611901617                       # Number of instructions committed
-system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.339523                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst    148791104                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148791104                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19067.269367                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19067.269367                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17118.543589                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17118.543589                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    146883081                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146883081                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36380788500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36380788500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.012824                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012824                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      1908023                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908023                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143343                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143343                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30208751500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30208751500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.011860                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011860                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764680                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764680                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29178.748051                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29178.748051                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27324.419197                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27324.419197                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     55666185                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666185                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45047581000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  45047581000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026986                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026986                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst      1543849                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543849                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769059                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769059                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21170686750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  21170686750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.013543                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774790                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       774790                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    206001138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206001138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23589.626006                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23589.626006                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20232.347005                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20232.347005                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     202549266                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202549266                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  81428369500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  81428369500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.016757                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016757                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      3451872                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3451872                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       912402                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       912402                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51379438250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  51379438250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.012327                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012327                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      2539470                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539470                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    206001138                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206001138                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23589.626006                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23589.626006                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20232.347005                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20232.347005                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    202549266                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202549266                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  81428369500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  81428369500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.016757                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.016757                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      3451872                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3451872                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       912402                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       912402                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51379438250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  51379438250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.012327                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012327                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      2539470                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539470                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             79.760448                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses        414541746                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.758169                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.997988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997988                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           2535374                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           2539470                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses         414541746                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4087.758169                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202549266                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1608263250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks      2340003                       # number of writebacks
-system.cpu.dcache.writebacks::total           2340003                       # number of writebacks
-system.cpu.discardedOps                      13239611                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                207242011                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    206630168                       # DTB hits
-system.cpu.dtb.data_misses                     611843                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                149856039                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    149313819                       # DTB read hits
-system.cpu.dtb.read_misses                     542220                       # DTB read misses
-system.cpu.dtb.write_accesses                57385972                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                    57316349                       # DTB write hits
-system.cpu.dtb.write_misses                     69623                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    226025524                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    226025524                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45550.859313                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 45550.859313                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43330.035971                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43330.035971                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    226020520                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       226020520                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    227936500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    227936500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst         5004                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5004                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216823500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    216823500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5004                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5004                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    226025524                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    226025524                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 45550.859313                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 45550.859313                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43330.035971                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 43330.035971                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     226020520                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        226020520                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    227936500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    227936500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst         5004                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5004                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216823500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    216823500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    226025524                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    226025524                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 45550.859313                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 45550.859313                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43330.035971                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 43330.035971                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    226020520                       # number of overall hits
-system.cpu.icache.overall_hits::total       226020520                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    227936500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    227936500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst         5004                       # number of overall misses
-system.cpu.icache.overall_misses::total          5004                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216823500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    216823500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5004                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5004                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          45167.969624                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        452056052                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1117.136811                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545477                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545477                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements              3175                       # number of replacements
-system.cpu.icache.tags.sampled_refs              5004                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         452056052                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1117.136811                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226020520                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        81747250                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.746534                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               226025572                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   226025524                       # ITB hits
-system.cpu.itb.fetch_misses                        48                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       778160                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       778160                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71244.326459                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71244.326459                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58557.851000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58557.851000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       571543                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571543                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14720289000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14720289000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265520                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265520                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       206617                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206617                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12099047500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12099047500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265520                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265520                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206617                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206617                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766314                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1766314                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73023.954626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73023.954626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60269.606712                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60269.606712                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1592955                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1592955                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12659359750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  12659359750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098147                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.098147                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst       173359                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       173359                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  10448278750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10448278750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098147                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098147                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       173359                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       173359                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks      2340003                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2340003                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks      2340003                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2340003                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      2544474                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544474                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72056.258158                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72056.258158                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59338.816794                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59338.816794                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      2164498                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164498                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  27379648750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  27379648750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149334                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149334                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       379976                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        379976                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  22547326250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22547326250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149334                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149334                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       379976                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       379976                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      2544474                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544474                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72056.258158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72056.258158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59338.816794                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59338.816794                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      2164498                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164498                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  27379648750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  27379648750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149334                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149334                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       379976                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       379976                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  22547326250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22547326250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149334                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149334                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       379976                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       379976                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          224                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13172                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18830                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             9.773812                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        40233665                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 21416.051201                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8077.270621                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.653566                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246499                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.900065                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32424                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989502                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           347265                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           379689                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         40233665                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        29493.321822                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3711009                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     188556996000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks       292560                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292560                       # number of writebacks
-system.cpu.numCycles                        819656253                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       737909003                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         312606528                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10008                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7418943                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7428951                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4782241500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8058500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3891611750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               762774704                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       320256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312286272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      312606528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        1766314                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1766314                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2340003                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       778160                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       778160                       # Transaction distribution
-system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               43042304                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052512                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1052512                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          3207663500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3609435250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    105025256                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43042304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43042304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq              173359                       # Transaction distribution
-system.membus.trans_dist::ReadResp             173359                       # Transaction distribution
-system.membus.trans_dist::Writeback            292560                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206617                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206617                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       609377.11                       # Average gap between requests
-system.physmem.avgMemAccLat                  29335.98                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       10585.98                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          59.28                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       59.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                          45.68                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.69                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        21.08                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          416487                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             416487                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             59338202                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                59338202                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45687055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            59338202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              105025256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45687055                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45687055                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples       141722                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      303.513414                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.917362                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     325.228374                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50747     35.81%     35.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38472     27.15%     62.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        12956      9.14%     72.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8075      5.70%     77.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5903      4.17%     81.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3858      2.72%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2996      2.11%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2531      1.79%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16184     11.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         141722                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                 24294464                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  24318464                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     24000                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18722176                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys               18723840                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       170688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          170688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst          24318464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24318464                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks     18723840                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18723840                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     275306446750                       # Time in different power states
-system.physmem.memoryStateTime::REF       13684840000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      120830469500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytes_read::cpu.inst          24320640                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24320640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       170752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          170752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18724096                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18724096                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             380010                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380010                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292564                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292564                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             59419210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                59419210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          417174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             417174                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45745959                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45745959                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45745959                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            59419210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              105165169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        380010                       # Number of read requests accepted
+system.physmem.writeReqs                       292564                       # Number of write requests accepted
+system.physmem.readBursts                      380010                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292564                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24298688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18722368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24320640                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18724096                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      343                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             379976                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                379976                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292560                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292560                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      78.91                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0               23726                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23205                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23510                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24533                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25455                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23583                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23677                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23976                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23173                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23944                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24673                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22745                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23724                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24416                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22797                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22464                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               17752                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               17432                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17901                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18769                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               19443                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18535                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18682                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23736                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23211                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23514                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24536                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25475                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23585                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23685                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23974                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23182                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23951                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24679                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22748                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23716                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24414                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22802                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22459                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               17754                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               17435                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17902                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18771                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               19442                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18539                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18677                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               18571                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18355                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18354                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18833                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19130                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19131                       # Per bank write bursts
 system.physmem.perBankWrBursts::11              17964                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18225                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18694                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18221                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18695                       # Per bank write bursts
 system.physmem.perBankWrBursts::14              17147                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              17101                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples         17247                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.008465                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      228.376560                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17237     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            7      0.04%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17247                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    378215                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1371                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    409305930000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  380010                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                 292564                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    378272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1380                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -554,42 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      379976                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  379976                       # Read request sizes (log2)
-system.physmem.readReqs                        379976                       # Number of read requests accepted
-system.physmem.readRowHitRate                   82.98                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     314993                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      375                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                   1898005000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    409828045500                       # Total gap between requests
-system.physmem.totMemAccLat               11135967500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     4018448750                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples         17247                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.961443                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.889231                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.813189                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17030     98.74%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             169      0.98%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              25      0.14%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               7      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::236-239             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17247                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -605,42 +140,42 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7536                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7537                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16938                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17305                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                    17384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17398                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17404                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17292                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       13                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
@@ -654,17 +189,482 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                     292560                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292560                       # Write request sizes (log2)
-system.physmem.writeReqs                       292560                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  73.63                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                    215411                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples       141944                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.070281                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.645979                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     325.191162                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50836     35.81%     35.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38595     27.19%     63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13069      9.21%     72.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8075      5.69%     77.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5863      4.13%     82.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3755      2.65%     84.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3005      2.12%     86.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2490      1.75%     88.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16256     11.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         141944                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17252                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.005912                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      228.974837                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17241     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            7      0.04%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           17252                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17252                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.956701                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.885973                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.749936                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17057     98.87%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             150      0.87%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              24      0.14%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               7      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17252                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4021715750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11140472000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1898335000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10592.75                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  29342.75                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          59.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.74                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       59.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.75                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.32                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314877                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215374                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.94                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                       608566.39                       # Average gap between requests
+system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     274823723500                       # Time in different power states
+system.physmem.memoryStateTime::REF       13667420000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      120808954500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    105165169                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              173388                       # Transaction distribution
+system.membus.trans_dist::ReadResp             173388                       # Transaction distribution
+system.membus.trans_dist::Writeback            292564                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206622                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206622                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1052584                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1052584                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43044736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43044736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43044736                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          3204326000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3607344750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               123709142                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87625206                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6390886                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71443290                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67227338                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             94.098883                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                14930671                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1120494                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    149298589                       # DTB read hits
+system.cpu.dtb.read_misses                     537604                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                149836193                       # DTB read accesses
+system.cpu.dtb.write_hits                    57313863                       # DTB write hits
+system.cpu.dtb.write_misses                     67044                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                57380907                       # DTB write accesses
+system.cpu.dtb.data_hits                    206612452                       # DTB hits
+system.cpu.dtb.data_misses                     604648                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                207217100                       # DTB accesses
+system.cpu.itb.fetch_hits                   225745608                       # ITB hits
+system.cpu.itb.fetch_misses                        48                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               225745656                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  485                       # Number of system calls
+system.cpu.numCycles                        818612023                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   611901617                       # Number of instructions committed
+system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      13147093                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.337816                       # CPI: cycles per instruction
+system.cpu.ipc                               0.747487                       # IPC: instructions per cycle
+system.cpu.tickCycles                       736852058                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        81759965                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements              3162                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1116.165991                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           225740617                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4991                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45229.536566                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1116.165991                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545003                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545003                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1589                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         451496207                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        451496207                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    225740617                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       225740617                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     225740617                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        225740617                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    225740617                       # number of overall hits
+system.cpu.icache.overall_hits::total       225740617                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4991                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4991                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4991                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4991                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4991                       # number of overall misses
+system.cpu.icache.overall_misses::total          4991                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    227498000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    227498000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    227498000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    227498000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    227498000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    227498000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    225745608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    225745608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    225745608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    225745608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    225745608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    225745608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45581.646965                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 45581.646965                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 45581.646965                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 45581.646965                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 45581.646965                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 45581.646965                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4991                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4991                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4991                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4991                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4991                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4991                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216413000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    216413000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216413000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    216413000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216413000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    216413000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43360.649169                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43360.649169                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43360.649169                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43360.649169                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               763750366                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1766329                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766329                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2340010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       778155                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       778155                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9982                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7418996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7428978                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       319424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312288192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      312607616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         312607616                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4782257000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       8038000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    3891565250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           347300                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29490.485605                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3710989                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           379724                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.772859                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     188606170000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21413.748537                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8076.737069                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.653496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.246482                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.899978                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32424                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13172                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18828                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989502                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         40233831                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40233831                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1592941                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1592941                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2340010                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2340010                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst       571533                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571533                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      2164474                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164474                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      2164474                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164474                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       173388                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       173388                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       206622                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206622                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       380010                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        380010                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       380010                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       380010                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  12655083750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  12655083750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  14728692500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14728692500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  27383776250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27383776250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  27383776250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27383776250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1766329                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1766329                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2340010                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2340010                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       778155                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       778155                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      2544484                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544484                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      2544484                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544484                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.098163                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.098163                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.265528                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265528                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149347                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.149347                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149347                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.149347                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72987.079556                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72987.079556                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71283.273320                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71283.273320                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72060.672745                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72060.672745                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72060.672745                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72060.672745                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks       292564                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292564                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       173388                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       173388                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       206622                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206622                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       380010                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       380010                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       380010                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       380010                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  10443247750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10443247750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  12110276500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12110276500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  22553524250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22553524250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  22553524250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22553524250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.098163                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.098163                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.265528                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265528                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.149347                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149347                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.149347                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149347                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60230.510474                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60230.510474                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58610.779588                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58610.779588                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59349.817768                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59349.817768                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59349.817768                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59349.817768                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           2535397                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.756934                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202541489                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539493                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.756664                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1608245250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4087.756934                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.997988                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997988                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         414526387                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414526387                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    146875295                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146875295                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     55666194                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666194                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     202541489                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202541489                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    202541489                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202541489                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1908118                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908118                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      1543840                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543840                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      3451958                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3451958                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      3451958                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3451958                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  36372214750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36372214750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  45066771500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  45066771500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  81438986250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  81438986250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  81438986250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81438986250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    148783413                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148783413                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     57210034                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    205993447                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    205993447                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    205993447                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    205993447                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.012825                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026985                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.016758                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016758                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.016758                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016758                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19061.826758                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19061.826758                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29191.348521                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29191.348521                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23592.113881                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23592.113881                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23592.113881                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23592.113881                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      2340010                       # number of writebacks
+system.cpu.dcache.writebacks::total           2340010                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst       143436                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143436                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       769029                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769029                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       912465                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       912465                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       912465                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       912465                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1764682                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764682                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       774811                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       774811                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      2539493                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539493                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      2539493                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539493                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  30204720750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30204720750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  21179013000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  21179013000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  51383733750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  51383733750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  51383733750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  51383733750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.011861                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011861                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.013543                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.012328                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012328                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.012328                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012328                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17116.240065                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17116.240065                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27334.424782                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27334.424782                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20233.855242                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20233.855242                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20233.855242                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20233.855242                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 12f448f86f5f9c17bb1e55e5b9324bceb4d07410..0b41505d83473f08a6ac364ce1398068321ff5f3 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               220685053500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 266134                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 254064                       # Number of bytes of host memory used
-host_op_rate                                   266134                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  1497.99                       # Real time elapsed on the host
-host_tick_rate                              147321061                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.219644                       # Number of seconds simulated
+sim_ticks                                219644167500                       # Number of ticks simulated
+final_tick                               219644167500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 184210                       # Simulator instruction rate (inst/s)
+host_op_rate                                   184210                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              101490439                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247040                       # Number of bytes of host memory used
+host_seconds                                  2164.19                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.220685                       # Number of seconds simulated
-sim_ticks                                220685053500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.751650                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                21330181                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             25468371                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect           1012944                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          26708480                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                46221019                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 8327448                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                   398664665                       # Number of instructions committed
-system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.107121                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst     94494338                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94494338                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68449.404762                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68449.404762                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66089.617769                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66089.617769                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     94493162                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94493162                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     80496500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     80496500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst         1176                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1176                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     63974750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     63974750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66549.865343                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66549.865343                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67934.000626                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67934.000626                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     73514789                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514789                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    395372750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    395372750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000081                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000081                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst         5941                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5941                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2744                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2744                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    217185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    217185000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3197                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3197                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    168015068                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168015068                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66863.741745                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66863.741745                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67505.342137                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67505.342137                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     168007951                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168007951                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst    475869250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    475869250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst         7117                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7117                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst         2952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2952                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    281159750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    281159750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         4165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    168015068                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168015068                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66863.741745                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66863.741745                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67505.342137                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67505.342137                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    168007951                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168007951                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst    475869250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    475869250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst         7117                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7117                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst         2952                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2952                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    281159750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    281159750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         4165                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs          40338.043457                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses        336034301                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.724304                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.803644                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803644                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses         336034301                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          3291.724304                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168007951                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
-system.cpu.dcache.writebacks::total               654                       # number of writebacks
-system.cpu.discardedOps                       4407642                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                169201829                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    169200862                       # DTB hits
-system.cpu.dtb.data_misses                        967                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 95596602                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                     95596493                       # DTB read hits
-system.cpu.dtb.read_misses                        109                       # DTB read misses
-system.cpu.dtb.write_accesses                73605227                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                    73604369                       # DTB write hits
-system.cpu.dtb.write_misses                       858                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     98039875                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98039875                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56706.988208                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56706.988208                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54392.373864                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54392.373864                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     98034702                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98034702                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    293345250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    293345250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst         5173                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5173                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281371750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281371750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5173                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5173                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     98039875                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98039875                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56706.988208                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56706.988208                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54392.373864                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54392.373864                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      98034702                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98034702                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    293345250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    293345250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst         5173                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5173                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281371750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281371750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5173                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     98039875                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98039875                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56706.988208                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56706.988208                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54392.373864                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54392.373864                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     98034702                       # number of overall hits
-system.cpu.icache.overall_hits::total        98034702                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    293345250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    293345250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst         5173                       # number of overall misses
-system.cpu.icache.overall_misses::total          5173                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281371750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281371750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5173                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          200                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          398                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          18951.227914                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses        196084923                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.700868                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937354                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937354                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements              3195                       # number of replacements
-system.cpu.icache.tags.sampled_refs              5173                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses         196084923                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1919.700868                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98034702                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                         3993538                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.903243                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                98041099                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    98039875                       # ITB hits
-system.cpu.itb.fetch_misses                      1224                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         3199                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3199                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68031.548757                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68031.548757                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55379.700446                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55379.700446                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    213483000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    213483000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.980932                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.980932                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         3138                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3138                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    173781500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    173781500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980932                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980932                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         3138                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3138                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6139                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         6139                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68618.957146                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68618.957146                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56083.175005                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56083.175005                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst         1402                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           1402                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    325048000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    325048000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.771624                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.771624                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4737                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4737                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    265666000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    265666000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771624                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771624                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4737                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4737                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst         9338                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9338                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68384.888889                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68384.888889                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55802.857143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55802.857143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst         1463                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst    538531000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    538531000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843328                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.843328                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst         7875                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7875                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    439447500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    439447500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843328                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7875                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7875                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst         9338                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9338                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68384.888889                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68384.888889                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55802.857143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55802.857143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst         1463                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst    538531000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    538531000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843328                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843328                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst         7875                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7875                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    439447500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    439447500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7875                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7875                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4444                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             0.282708                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses           88409                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks   373.078063                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4054.561025                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011385                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123735                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.135121                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160950                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs             5274                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses            88409                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse         4427.639089                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               1491                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                        441370107                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       437376569                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus            639488                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10346                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19330                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        5650000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8573250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6973250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                 2897740                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         639488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq           6139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          6139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3199                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3199                       # Transaction distribution
-system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                 504000                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15750                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy             9402000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           73919000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                      2283798                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       504000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              504000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                4737                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3138                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3138                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                     28023488.51                       # Average gap between requests
-system.physmem.avgMemAccLat                  25444.19                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        6694.19                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                           2.28                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst         1130154                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1130154                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              2283798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2283798                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2283798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2283798                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples         1519                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      329.859118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     197.497740                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.655221                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            518     34.10%     34.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          348     22.91%     57.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          182     11.98%     68.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           96      6.32%     75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      4.15%     79.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           48      3.16%     82.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           42      2.76%     85.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           38      2.50%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     12.11%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1519                       # Bytes accessed per row activation
+system.physmem.bytes_read::cpu.inst            504000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               504000                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       249408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          249408                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               7875                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7875                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2294620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2294620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1135509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1135509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2294620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2294620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7875                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                        7875                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                   504000                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                    504000                       # Total read bytes from the system interface side
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                    504000                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       249408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          249408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst            504000                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               504000                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE     211586881750                       # Time in different power states
-system.physmem.memoryStateTime::REF        7368920000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1722369500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst               7875                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7875                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      80.58                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.perBankRdBursts::0                 551                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 675                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
@@ -503,9 +69,26 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                      6827                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        81                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    219644086000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7875                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                      6822                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       970                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -534,23 +117,7 @@ system.physmem.rdQLenPdf::27                        0                       # Wh
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                        7875                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7875                       # Read request sizes (log2)
-system.physmem.readReqs                          7875                       # Number of read requests accepted
-system.physmem.readRowHitRate                   80.58                       # Row buffer hit rate for reads
-system.physmem.readRowHits                       6346                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                     39375000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    220684972000                       # Total gap between requests
-system.physmem.totMemAccLat                 200373000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                       52716750                       # Total ticks spent queuing
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -615,17 +182,450 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples         1515                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      331.828383                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     199.155331                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.926802                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            511     33.73%     33.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          341     22.51%     56.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          189     12.48%     68.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          107      7.06%     75.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           50      3.30%     79.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           60      3.96%     83.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      2.38%     85.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           30      1.98%     87.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          191     12.61%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1515                       # Bytes accessed per row activation
+system.physmem.totQLat                       51832750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 199489000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     39375000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6581.94                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  25331.94                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                       6354                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   80.69                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                     27891312.51                       # Average gap between requests
+system.physmem.pageHitRate                      80.69                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     210595847500                       # Time in different power states
+system.physmem.memoryStateTime::REF        7334340000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1712418250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      2294620                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4737                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4737                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3138                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3138                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15750                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15750                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       504000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              504000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 504000                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             9401500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           73916250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                46223200                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26710359                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1014875                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25598344                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21333887                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             83.340887                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8326899                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     95595217                       # DTB read hits
+system.cpu.dtb.read_misses                        114                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 95595331                       # DTB read accesses
+system.cpu.dtb.write_hits                    73605959                       # DTB write hits
+system.cpu.dtb.write_misses                       858                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                73606817                       # DTB write accesses
+system.cpu.dtb.data_hits                    169201176                       # DTB hits
+system.cpu.dtb.data_misses                        972                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                169202148                       # DTB accesses
+system.cpu.itb.fetch_hits                    98054052                       # ITB hits
+system.cpu.itb.fetch_misses                      1240                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                98055292                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  215                       # Number of system calls
+system.cpu.numCycles                        439288335                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                   398664665                       # Number of instructions committed
+system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       4458110                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.101899                       # CPI: cycles per instruction
+system.cpu.ipc                               0.907524                       # IPC: instructions per cycle
+system.cpu.tickCycles                       435056382                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         4231953                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements              3195                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1919.689869                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            98048879                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5173                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18953.968490                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.689869                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937349                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937349                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          200                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          398                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         196113277                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        196113277                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     98048879                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        98048879                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      98048879                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         98048879                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     98048879                       # number of overall hits
+system.cpu.icache.overall_hits::total        98048879                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5173                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5173                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5173                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5173                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5173                       # number of overall misses
+system.cpu.icache.overall_misses::total          5173                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    293884750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    293884750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    293884750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    293884750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    293884750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    293884750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     98054052                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     98054052                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     98054052                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     98054052                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     98054052                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     98054052                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56811.279722                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56811.279722                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5173                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5173                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5173                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5173                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281914250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281914250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281914250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281914250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281914250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281914250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                 2911473                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           6139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          6139                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3199                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3199                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10346                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         8984                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19330                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       331072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         639488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            639488                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        5650000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       8571750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       6975500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         4427.544414                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               1491                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5274                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.282708                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks   373.069820                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4054.474595                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011385                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123733                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.135118                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5274                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4444                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160950                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            88409                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           88409                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1402                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1402                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           61                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1463                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1463                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4737                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4737                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         3138                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3138                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7875                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7875                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7875                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7875                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    325631750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    325631750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    212036500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    212036500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    537668250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    537668250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    537668250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    537668250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6139                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         6139                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         3199                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3199                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         9338                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9338                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         9338                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9338                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.771624                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.771624                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.980932                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.980932                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843328                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.843328                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843328                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.843328                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4737                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4737                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         3138                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3138                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7875                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7875                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7875                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7875                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    266250750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    266250750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    172336000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    172336000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    438586750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    438586750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    438586750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    438586750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771624                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771624                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980932                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980932                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843328                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843328                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843328                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements               771                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3291.682067                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168006905                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40337.792317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.682067                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.803633                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803633                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336032209                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336032209                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     94492115                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94492115                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     73514790                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514790                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     168006905                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168006905                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    168006905                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168006905                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst         1177                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1177                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         5940                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5940                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         7117                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7117                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         7117                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7117                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     80734750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     80734750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    392862000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    392862000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    473596750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    473596750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    473596750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    473596750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     94493292                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94493292                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    168014022                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168014022                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    168014022                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168014022                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000081                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000081                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66544.435858                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66544.435858                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
+system.cpu.dcache.writebacks::total               654                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          208                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2744                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2744                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst         2952                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2952                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst         2952                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2952                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          969                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         3196                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3196                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst         4165                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         4165                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64078250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     64078250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    215682250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    215682250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    279760500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    279760500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    279760500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    279760500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 9659640f2db860a95869ef22626912438ac075e7..ef1860117ace6bc963e14a29b2dd96f2c4b1f745 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1191522940000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 293885                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 258084                       # Number of bytes of host memory used
-host_op_rate                                   293885                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  6837.45                       # Real time elapsed on the host
-host_tick_rate                              174264280                       # Simulator tick rate (ticks/s)
+sim_seconds                                  1.190861                       # Number of seconds simulated
+sim_ticks                                1190860634000                       # Number of ticks simulated
+final_tick                               1190860634000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 304682                       # Simulator instruction rate (inst/s)
+host_op_rate                                   304682                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              180566626                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250024                       # Number of bytes of host memory used
+host_seconds                                  6595.13                       # Real time elapsed on the host
 sim_insts                                  2009421070                       # Number of instructions simulated
 sim_ops                                    2009421070                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.191523                       # Number of seconds simulated
-sim_ticks                                1191522940000                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.283547                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits               179637334                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups            223753609                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect              24504                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect          26222048                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted         174812836                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               271009171                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                40320873                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                  2009421070                       # Number of instructions committed
-system.cpu.committedOps                    2009421070                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.185937                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst    484973463                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    484973463                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 29869.727061                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 29869.727061                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 27793.909016                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27793.909016                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    483514457                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       483514457                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  43580111000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  43580111000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.003008                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003008                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      1459006                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1459006                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          621                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          621                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  40534220000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  40534220000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003007                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1458385                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1458385                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64653.542435                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64653.542435                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62992.275671                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62992.275671                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst    210652621                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      210652621                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9198582750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9198582750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000675                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000675                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       142275                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       142275                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        70327                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        70327                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4532168250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4532168250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        71948                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71948                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    695768359                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    695768359                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 32960.294758                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32960.294758                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29448.746286                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29448.746286                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     694167078                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        694167078                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  52778693750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  52778693750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.002301                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002301                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      1601281                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1601281                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst        70948                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        70948                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  45066388250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45066388250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002199                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002199                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      1530333                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1530333                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    695768359                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    695768359                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 32960.294758                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32960.294758                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29448.746286                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29448.746286                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    694167078                       # number of overall hits
-system.cpu.dcache.overall_hits::total       694167078                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  52778693750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  52778693750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.002301                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002301                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      1601281                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1601281                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst        70948                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        70948                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  45066388250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45066388250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002199                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002199                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      1530333                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1530333                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          948                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1258                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1618                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs            453.605247                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses       1393067051                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4094.559536                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999648                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999648                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           1526237                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           1530333                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses        1393067051                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4094.559536                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           694167078                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         828837250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks        95962                       # number of writebacks
-system.cpu.dcache.writebacks::total             95962                       # number of writebacks
-system.cpu.discardedOps                      54230447                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                722376032                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    721933722                       # DTB hits
-system.cpu.dtb.data_misses                     442310                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                511558478                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    511131393                       # DTB read hits
-system.cpu.dtb.read_misses                     427085                       # DTB read misses
-system.cpu.dtb.write_accesses               210817554                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                   210802329                       # DTB write hits
-system.cpu.dtb.write_misses                     15225                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    683609242                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    683609242                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20652.120610                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20652.120610                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18596.962668                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18596.962668                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    683586607                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       683586607                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    467460750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    467460750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst        22635                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         22635                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    420942250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    420942250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        22635                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        22635                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    683609242                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    683609242                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20652.120610                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20652.120610                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18596.962668                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18596.962668                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     683586607                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        683586607                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    467460750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    467460750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        22635                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          22635                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    420942250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    420942250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        22635                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        22635                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    683609242                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    683609242                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20652.120610                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20652.120610                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18596.962668                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18596.962668                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    683586607                       # number of overall hits
-system.cpu.icache.overall_hits::total       683586607                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    467460750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    467460750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        22635                       # number of overall misses
-system.cpu.icache.overall_misses::total         22635                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    420942250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    420942250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst        22635                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        22635                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1573                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          30201.758726                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses       1367241118                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1688.672888                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.824547                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.824547                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1741                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             20893                       # number of replacements
-system.cpu.icache.tags.sampled_refs             22634                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses        1367241118                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1688.672888                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           683586607                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                       103732278                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.843215                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               683609362                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   683609242                       # ITB hits
-system.cpu.itb.fetch_misses                       120                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst        71948                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        71948                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65940.521766                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65940.521766                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53018.517549                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53018.517549                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst         5079                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4409376750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4409376750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.929407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.929407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst        66869                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66869                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3545295250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3545295250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.929407                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929407                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66869                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66869                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1481020                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1481020                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70256.406419                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70256.406419                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57611.646625                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57611.646625                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1071704                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1071704                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  28757071250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  28757071250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.276374                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.276374                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst       409316                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       409316                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  23581368750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  23581368750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.276374                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.276374                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       409316                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       409316                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks        95962                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        95962                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks        95962                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        95962                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      1552968                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1552968                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69650.341779                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69650.341779                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56966.649516                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56966.649516                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      1076783                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1076783                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  33166448000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  33166448000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.306629                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.306629                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       476185                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        476185                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  27126664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  27126664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.306629                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.306629                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       476185                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       476185                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      1552968                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1552968                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69650.341779                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69650.341779                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56966.649516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56966.649516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      1076783                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1076783                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  33166448000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  33166448000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.306629                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.306629                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       476185                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       476185                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  27126664000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  27126664000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.306629                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.306629                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       476185                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       476185                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2674                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29455                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             2.311701                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses        13739527                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks  1349.197229                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.044596                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.041174                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.956178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997352                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           443405                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           476139                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses         13739527                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        32681.241826                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1100691                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
-system.cpu.numCycles                       2383045880                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                      2279313602                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         105531456                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45269                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3156628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3201897                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      920427000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      34576250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2370536750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                88568547                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1448576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104082880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      105531456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        1481020                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1481019                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        95962                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        71948                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        71948                       # Transaction distribution
-system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               34757888                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019276                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1019276                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1283589500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4535569500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                     29170977                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34757888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34757888                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq              409315                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409315                       # Transaction distribution
-system.membus.trans_dist::Writeback             66908                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66869                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66869                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      2193961.36                       # Average gap between requests
-system.physmem.avgMemAccLat                  26986.02                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        8236.02                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                          25.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           3.59                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.59                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        24.44                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst          156519                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156519                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst             25577163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25577163                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3593814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            25577163                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29170977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3593814                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3593814                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples       196329                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      176.935328                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     127.479402                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     206.642311                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          75423     38.42%     38.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        90953     46.33%     84.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        17208      8.76%     93.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          945      0.48%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          960      0.49%     94.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          641      0.33%     94.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1086      0.55%     95.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          966      0.49%     95.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8147      4.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         196329                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                 30457664                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  30475776                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     18112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4280512                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       186496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst          30475776                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30475776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          30476096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30476096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       186816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          186816                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     593665055500                       # Time in different power states
-system.physmem.memoryStateTime::REF       39787540000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      558069752500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             476184                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                476184                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             476189                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                476189                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      63.83                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.bw_read::cpu.inst             25591656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25591656                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          156875                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             156875                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3595813                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3595813                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3595813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            25591656                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29187469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        476189                       # Number of read requests accepted
+system.physmem.writeReqs                        66908                       # Number of write requests accepted
+system.physmem.readBursts                      476189                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 30458432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     17664                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4280448                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  30476096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      276                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               29463                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29813                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29826                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29780                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29692                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29773                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29849                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29830                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29753                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29878                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29844                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29908                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               29817                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29839                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29779                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               29691                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               29776                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               29845                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               29824                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29755                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29877                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              29842                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29915                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              29785                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29573                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29507                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              29577                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29501                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              29627                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
@@ -508,23 +70,31 @@ system.physmem.perBankWrBursts::6                4262                       # Pe
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4222                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          4057                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       115.306631                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.801532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     1128.564145                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           4038     99.53%     99.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-14335            6      0.15%     99.68% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-16383           12      0.30%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4057                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    475416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       459                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1190860558500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  476189                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    475413                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       474                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -555,30 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      476184                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  476184                       # Read request sizes (log2)
-system.physmem.readReqs                        476184                       # Number of read requests accepted
-system.physmem.readRowHitRate                   62.16                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     295815                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                      283                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                   2379505000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1191522864500                       # Total gap between requests
-system.physmem.totMemAccLat               12842674500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     3919530750                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          4057                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.485827                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.464369                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.858223                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3072     75.72%     75.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                984     24.25%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4057                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -594,24 +140,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4057                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4056                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -643,17 +189,471 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
-system.physmem.writeReqs                        66908                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  75.68                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     50635                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples       196024                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      177.216831                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     127.562877                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     207.494740                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          75216     38.37%     38.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        90843     46.34%     84.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        17447      8.90%     93.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          798      0.41%     94.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          682      0.35%     94.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          656      0.33%     94.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1172      0.60%     95.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1008      0.51%     95.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8202      4.18%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         196024                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4056                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       115.321252                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.815163                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1129.679023                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4037     99.53%     99.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            7      0.17%     99.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383            9      0.22%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-18431            2      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4056                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4056                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.489645                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.468091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.860070                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3063     75.52%     75.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                993     24.48%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4056                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4642842500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               13566211250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2379565000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9755.65                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  28505.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.58                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.59                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.59                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.60                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     296141                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50629                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   62.23                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2192721.67                       # Average gap between requests
+system.physmem.pageHitRate                      63.88                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     589509971750                       # Time in different power states
+system.physmem.memoryStateTime::REF       39765440000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      561585082000                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                     29187469                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              409320                       # Transaction distribution
+system.membus.trans_dist::ReadResp             409320                       # Transaction distribution
+system.membus.trans_dist::Writeback             66908                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66869                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66869                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019286                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1019286                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34758208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34758208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34758208                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1283694000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         4536921750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               271010035                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         174815111                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          26224729                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            223743631                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               179636452                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             80.286733                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                40316732                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              27614                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    511123125                       # DTB read hits
+system.cpu.dtb.read_misses                     428196                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                511551321                       # DTB read accesses
+system.cpu.dtb.write_hits                   210802220                       # DTB write hits
+system.cpu.dtb.write_misses                     15121                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               210817341                       # DTB write accesses
+system.cpu.dtb.data_hits                    721925345                       # DTB hits
+system.cpu.dtb.data_misses                     443317                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                722368662                       # DTB accesses
+system.cpu.itb.fetch_hits                   682230205                       # ITB hits
+system.cpu.itb.fetch_misses                       120                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               682230325                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   39                       # Number of system calls
+system.cpu.numCycles                       2381721268                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                  2009421070                       # Number of instructions committed
+system.cpu.committedOps                    2009421070                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      51480727                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.185277                       # CPI: cycles per instruction
+system.cpu.ipc                               0.843684                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2275163827                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       106557441                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             20821                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1689.662119                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           682207641                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             22563                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          30235.679697                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1689.662119                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.825030                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.825030                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1574                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1364482973                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1364482973                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    682207641                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       682207641                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     682207641                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        682207641                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    682207641                       # number of overall hits
+system.cpu.icache.overall_hits::total       682207641                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        22564                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         22564                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        22564                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          22564                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        22564                       # number of overall misses
+system.cpu.icache.overall_misses::total         22564                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    467220750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    467220750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    467220750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    467220750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    467220750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    467220750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    682230205                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    682230205                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    682230205                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    682230205                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    682230205                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    682230205                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20706.468268                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20706.468268                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        22564                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        22564                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        22564                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        22564                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        22564                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        22564                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    420842250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    420842250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    420842250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    420842250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    420842250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    420842250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                88620923                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1481078                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1481077                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        95962                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        71948                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        71948                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45127                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3156886                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3202013                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1444032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104091136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      105535168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         105535168                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      920456000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      34470750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2371437000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           443410                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32681.250734                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1100744                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           476144                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.311788                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  1349.100172                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.150562                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.041171                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.956181                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997353                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2678                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29451                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13739996                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13739996                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      1071757                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1071757                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        95962                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        95962                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst         5079                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1076836                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1076836                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1076836                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1076836                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst       409321                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       409321                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst        66869                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66869                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       476190                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        476190                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       476190                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       476190                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  29485195750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  29485195750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4407101000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4407101000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  33892296750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  33892296750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  33892296750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  33892296750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1481078                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1481078                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        95962                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        95962                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst        71948                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71948                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1553026                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1553026                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1553026                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1553026                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.276367                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.276367                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.929407                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.929407                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.306621                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.306621                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.306621                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.306621                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72034.407592                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72034.407592                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65906.488806                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65906.488806                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71173.894349                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71173.894349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71173.894349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst       409321                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       409321                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst        66869                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66869                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       476190                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       476190                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       476190                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       476190                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  24307408750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24307408750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3543029000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3543029000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  27850437750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  27850437750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  27850437750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  27850437750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.276367                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.276367                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.929407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.929407                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.306621                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.306621                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.306621                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.306621                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59384.709678                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59384.709678                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52984.626658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52984.626658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58485.977761                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58485.977761                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58485.977761                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58485.977761                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           1526366                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.558807                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           694159033                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1530462                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            453.561757                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         828677250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4094.558807                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.999648                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999648                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          948                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1262                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1615                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1393051346                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1393051346                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    483506411                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       483506411                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    210652622                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      210652622                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     694159033                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        694159033                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    694159033                       # number of overall hits
+system.cpu.dcache.overall_hits::total       694159033                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      1459135                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1459135                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       142274                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       142274                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      1601409                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1601409                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      1601409                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1601409                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  44310462500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  44310462500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9194463750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9194463750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  53504926250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  53504926250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  53504926250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  53504926250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    484965546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    484965546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    695760442                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    695760442                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    695760442                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    695760442                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.003009                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003009                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000675                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000675                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.002302                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002302                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.002302                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002302                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30367.623626                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30367.623626                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64625.045686                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64625.045686                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33411.156207                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33411.156207                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33411.156207                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33411.156207                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        95962                       # number of writebacks
+system.cpu.dcache.writebacks::total             95962                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          621                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          621                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst        70326                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        70326                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst        70947                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        70947                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst        70947                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        70947                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      1458514                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1458514                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst        71948                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71948                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      1530462                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1530462                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      1530462                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1530462                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  41263033500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  41263033500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4529893000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4529893000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  45792926500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45792926500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  45792926500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45792926500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003007                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003007                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002200                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002200                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002200                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002200                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8796e7316462c7dfc25ac02384dd3db294572770..5d39af8d64a9bdb839acfb863cac8de33390beb6 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                                58437370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 298644                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 257212                       # Number of bytes of host memory used
-host_op_rate                                   298644                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   296.13                       # Real time elapsed on the host
-host_tick_rate                              197335322                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.058331                       # Number of seconds simulated
+sim_ticks                                 58330740000                       # Number of ticks simulated
+final_tick                                58330740000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 186275                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186275                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              122860334                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249156                       # Number of bytes of host memory used
+host_seconds                                   474.77                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.058437                       # Number of seconds simulated
-sim_ticks                                 58437370000                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             63.309910                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 6368851                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             10059801                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect              72966                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect            375118                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted           9451361                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                14600308                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 1701571                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    88438073                       # Number of instructions committed
-system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.321543                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20357517                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20357517                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49316.405682                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49316.405682                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39545.722557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39545.722557                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     20268112                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20268112                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4409133250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4409133250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004392                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004392                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst        89405                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89405                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28095                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28095                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2424548250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2424548250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003012                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003012                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61310                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61310                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70753.026587                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70753.026587                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69179.575454                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69179.575454                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     14333276                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333276                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  19817993500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  19817993500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019167                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019167                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       280101                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280101                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136536                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136536                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9931765750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9931765750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143565                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143565                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     34970894                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34970894                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 65566.260764                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65566.260764                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60311.477730                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60311.477730                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      34601388                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34601388                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  24227126750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24227126750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.010566                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010566                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst       369506                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369506                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       164631                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164631                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12356314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12356314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005858                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005858                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       204875                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204875                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     34970894                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34970894                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 65566.260764                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65566.260764                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60311.477730                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60311.477730                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst     34601388                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34601388                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  24227126750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24227126750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.010566                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010566                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst       369506                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369506                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       164631                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164631                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12356314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12356314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005858                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005858                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       204875                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204875                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          730                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3314                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs            168.890240                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         70146663                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.465989                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.994010                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994010                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements            200779                       # number of replacements
-system.cpu.dcache.tags.sampled_refs            204875                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          70146663                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4071.465989                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34601388                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         644810250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       168548                       # number of writebacks
-system.cpu.dcache.writebacks::total            168548                       # number of writebacks
-system.cpu.discardedOps                       1195680                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                 35330623                       # DTB accesses
-system.cpu.dtb.data_acv                             9                       # DTB access violations
-system.cpu.dtb.data_hits                     35224185                       # DTB hits
-system.cpu.dtb.data_misses                     106438                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 20656247                       # DTB read accesses
-system.cpu.dtb.read_acv                             9                       # DTB read access violations
-system.cpu.dtb.read_hits                     20558934                       # DTB read hits
-system.cpu.dtb.read_misses                      97313                       # DTB read misses
-system.cpu.dtb.write_accesses                14674376                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                    14665251                       # DTB write hits
-system.cpu.dtb.write_misses                      9125                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     25515682                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25515682                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16238.011767                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16238.011767                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14217.821664                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14217.821664                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     25361176                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25361176                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2508870246                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2508870246                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006055                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006055                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst       154506                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        154506                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2196738754                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2196738754                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006055                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154506                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       154506                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     25515682                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25515682                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16238.011767                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16238.011767                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14217.821664                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14217.821664                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      25361176                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25361176                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst   2508870246                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2508870246                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006055                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006055                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst       154506                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         154506                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2196738754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2196738754                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006055                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst       154506                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       154506                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     25515682                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25515682                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16238.011767                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16238.011767                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14217.821664                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14217.821664                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     25361176                       # number of overall hits
-system.cpu.icache.overall_hits::total        25361176                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst   2508870246                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2508870246                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006055                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006055                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst       154506                       # number of overall misses
-system.cpu.icache.overall_misses::total        154506                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2196738754                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2196738754                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006055                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst       154506                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       154506                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1044                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          797                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs            164.144694                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         51185869                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1934.490309                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.944575                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.944575                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements            152457                       # number of replacements
-system.cpu.icache.tags.sampled_refs            154505                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          51185869                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1934.490309                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25361176                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       41486335250                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        25710116                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.756691                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                25520848                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    25515682                       # ITB hits
-system.cpu.itb.fetch_misses                      5166                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143566                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143566                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73817.546091                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73817.546091                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60944.031219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60944.031219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst        12685                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12685                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9661314250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9661314250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911643                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911643                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       130881                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130881                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7976415750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7976415750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911643                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911643                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130881                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       215815                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       215815                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72877.172362                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72877.172362                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60213.094339                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60213.094339                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst       180082                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         180082                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2604120000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2604120000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.165572                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.165572                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        35733                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35733                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2151594500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2151594500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.165572                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165572                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35733                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35733                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks       168548                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168548                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       168548                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168548                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst       359381                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       359381                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73615.868114                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73615.868114                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.270277                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60787.270277                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst       192767                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          192767                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst  12265434250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12265434250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463614                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.463614                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       166614                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166614                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10128010250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10128010250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463614                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.463614                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       166614                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166614                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst       359381                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       359381                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73615.868114                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73615.868114                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.270277                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60787.270277                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst       192767                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         192767                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst  12265434250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12265434250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463614                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.463614                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       166614                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166614                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10128010250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10128010250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463614                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.463614                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       166614                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166614                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          993                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12007                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18840                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             1.331233                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses         4531761                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 26227.699402                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4243.729621                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.800406                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.129508                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.929914                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32076                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements           132687                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           164763                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses          4531761                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        30471.429023                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             219338                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks       114047                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114047                       # number of writebacks
-system.cpu.numCycles                        116874740                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                        91164624                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus          33787392                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       309011                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578298                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            887309                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      432512500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     233318246                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     343226000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               578181256                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9888320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23899072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       33787392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq         215815                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        215814                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168548                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143566                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143566                       # Transaction distribution
-system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               17962240                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447273                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 447273                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy          1301422000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1600112750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    307375914                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17962240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            17962240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq               35732                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35732                       # Transaction distribution
-system.membus.trans_dist::Writeback            114047                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130881                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130881                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       208214.01                       # Average gap between requests
-system.physmem.avgMemAccLat                  30471.23                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       11721.23                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         182.46                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      182.47                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                         124.87                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      124.90                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        24.17                       # Average write queue length when enqueuing
-system.physmem.busUtil                           2.40                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.98                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst         8825038                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8825038                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            182472825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               182472825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         124903089                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           182472825                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              307375914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks         124903089                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              124903089                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples        54430                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      329.948631                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.734417                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.314792                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19369     35.59%     35.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11718     21.53%     57.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5622     10.33%     67.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3646      6.70%     74.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2769      5.09%     79.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2059      3.78%     83.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1651      3.03%     86.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1489      2.74%     88.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6107     11.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54430                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                 10662720                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                  10663232                       # Total read bytes from the system interface side
+system.physmem.bytes_read::cpu.inst          10662976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10662976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       515264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          515264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7299200                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7299200                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             166609                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166609                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114050                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114050                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            182802001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               182802001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8833490                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8833490                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         125134706                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              125134706                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         125134706                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           182802001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              307936707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166609                       # Number of read requests accepted
+system.physmem.writeReqs                       114050                       # Number of write requests accepted
+system.physmem.readBursts                      166609                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114050                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10662464                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       512                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7296960                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                7299008                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       515712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          515712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10663232                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10663232                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      7299008                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7299008                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE      31940805250                       # Time in different power states
-system.physmem.memoryStateTime::REF        1951300000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       24543978500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytesWritten                   7297728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10662976                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7299200                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             166613                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166613                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114047                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114047                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      80.59                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0               10468                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10509                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10471                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10513                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10311                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10091                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10432                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10432                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9848                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10303                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10643                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10591                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10256                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10303                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10430                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10425                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9845                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10301                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10592                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10642                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10594                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10255                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10302                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10654                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10527                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10528                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              10647                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7087                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7261                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7256                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6999                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7177                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7085                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7096                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7089                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7224                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6941                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7095                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6965                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7289                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7282                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          7018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.736820                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      347.923098                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7017     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7018                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    164979                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1599                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        27                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                     58330713500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166609                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                 114050                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    164962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1611                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -550,36 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      166613                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166613                       # Read request sizes (log2)
-system.physmem.readReqs                        166613                       # Number of read requests accepted
-system.physmem.readRowHitRate                   86.96                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     144887                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        8                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                    833025000                       # Total ticks spent in databus transfers
-system.physmem.totGap                     58437343500                       # Total gap between requests
-system.physmem.totMemAccLat                5076659000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     1952815250                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          7018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.246082                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.230651                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.740530                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6255     89.13%     89.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 14      0.20%     89.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                591      8.42%     97.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                122      1.74%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 26      0.37%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  3      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  4      0.06%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7018                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -595,28 +140,28 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7033                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     7035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7040                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7075                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7030                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7036                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7023                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
@@ -644,17 +189,472 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                     114047                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114047                       # Write request sizes (log2)
-system.physmem.writeReqs                       114047                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  71.29                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     81299                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples        54540                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      329.285515                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     195.168705                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.681094                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19405     35.58%     35.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11848     21.72%     57.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5629     10.32%     67.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3624      6.64%     74.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2728      5.00%     79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2044      3.75%     83.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1598      2.93%     85.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1491      2.73%     88.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6173     11.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54540                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7020                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.731339                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      347.912038                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7019     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7020                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7020                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.243162                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.227940                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.737137                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6260     89.17%     89.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.21%     89.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                596      8.49%     97.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                118      1.68%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 21      0.30%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  7      0.10%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7020                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1961331500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5085100250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    833005000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11772.63                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  30522.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         182.79                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         125.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      182.80                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      125.13                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           2.41                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.98                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144790                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81289                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   86.91                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.27                       # Row buffer hit rate for writes
+system.physmem.avgGap                       207834.82                       # Average gap between requests
+system.physmem.pageHitRate                      80.56                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      31870385750                       # Time in different power states
+system.physmem.memoryStateTime::REF        1947660000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       24509026750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    307936707                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               35729                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35729                       # Transaction distribution
+system.membus.trans_dist::Writeback            114050                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130880                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130880                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       447268                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 447268                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17962176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            17962176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               17962176                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy          1302300000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1600619750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                14594378                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9449120                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            378858                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10404778                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6369492                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             61.216991                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1700724                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              73182                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     20554057                       # DTB read hits
+system.cpu.dtb.read_misses                      96859                       # DTB read misses
+system.cpu.dtb.read_acv                             9                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20650916                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665861                       # DTB write hits
+system.cpu.dtb.write_misses                      9387                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                14675248                       # DTB write accesses
+system.cpu.dtb.data_hits                     35219918                       # DTB hits
+system.cpu.dtb.data_misses                     106246                       # DTB misses
+system.cpu.dtb.data_acv                             9                       # DTB access violations
+system.cpu.dtb.data_accesses                 35326164                       # DTB accesses
+system.cpu.itb.fetch_hits                    25539378                       # ITB hits
+system.cpu.itb.fetch_misses                      5182                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                25544560                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.numCycles                        116661480                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    88438073                       # Number of instructions committed
+system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       1184669                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.319132                       # CPI: cycles per instruction
+system.cpu.ipc                               0.758074                       # IPC: instructions per cycle
+system.cpu.tickCycles                        90786920                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        25874560                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements            152636                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1933.709390                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25384693                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154684                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.106779                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       41485931250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1933.709390                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.944194                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.944194                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1042                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          799                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          51233440                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51233440                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25384693                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25384693                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25384693                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25384693                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25384693                       # number of overall hits
+system.cpu.icache.overall_hits::total        25384693                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       154685                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        154685                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       154685                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         154685                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       154685                       # number of overall misses
+system.cpu.icache.overall_misses::total        154685                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2511936746                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2511936746                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2511936746                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2511936746                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2511936746                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2511936746                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25539378                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25539378                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25539378                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25539378                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25539378                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25539378                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006057                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006057                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006057                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006057                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006057                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006057                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16239.045454                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16239.045454                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16239.045454                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16239.045454                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16239.045454                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16239.045454                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154685                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       154685                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       154685                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       154685                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       154685                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       154685                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2199492254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2199492254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2199492254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2199492254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2199492254                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2199492254                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006057                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006057                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006057                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006057                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14219.169629                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14219.169629                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14219.169629                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14219.169629                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               579413736                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         215991                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        215990                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168535                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143563                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143563                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       309369                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       578273                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            887642                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9899776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23897856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       33797632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          33797632                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      432579500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     233564246                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     343185250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements           132686                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30472.865320                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             219503                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164761                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.332251                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 26247.009665                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4225.855654                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.800995                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.128963                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.929958                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32075                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1028                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11972                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18837                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978851                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          4533036                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4533036                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       180261                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         180261                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168535                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168535                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst        12683                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12683                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       192944                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          192944                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       192944                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         192944                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        35730                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        35730                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       130880                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130880                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst       166610                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166610                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       166610                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166610                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2607479500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2607479500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9666800250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9666800250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  12274279750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12274279750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  12274279750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12274279750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       215991                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       215991                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       143563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       359554                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       359554                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       359554                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       359554                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.165424                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.165424                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.911656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463380                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.463380                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463380                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.463380                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72977.315981                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72977.315981                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73860.026360                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73860.026360                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73670.726547                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73670.726547                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73670.726547                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73670.726547                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks       114050                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114050                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        35730                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        35730                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       130880                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130880                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       166610                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166610                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       166610                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166610                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2154391500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2154391500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7982023250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7982023250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10136414750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10136414750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10136414750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10136414750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.165424                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.165424                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.911656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463380                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.463380                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463380                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.463380                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60296.431570                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60296.431570                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60987.341458                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60987.341458                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60839.173819                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60839.173819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60839.173819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60839.173819                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements            200773                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4071.422788                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34597432                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204869                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.875877                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         644670250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4071.422788                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.994000                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.994000                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          752                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3292                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          70138775                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70138775                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20264167                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20264167                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     14333265                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333265                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst      34597432                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34597432                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     34597432                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34597432                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst        89409                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89409                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       280112                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280112                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       369521                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369521                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       369521                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369521                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   4415904250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4415904250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  20008402750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20008402750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  24424307000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24424307000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  24424307000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24424307000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20353576                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20353576                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     34966953                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34966953                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     34966953                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34966953                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.004393                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004393                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.019168                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.010568                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010568                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.010568                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010568                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49389.929985                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49389.929985                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71430.009246                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 71430.009246                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66097.209631                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66097.209631                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66097.209631                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66097.209631                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       168535                       # number of writebacks
+system.cpu.dcache.writebacks::total            168535                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        28102                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28102                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       136550                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136550                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       164652                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164652                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       164652                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164652                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        61307                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61307                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       143562                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143562                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       204869                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204869                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       204869                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204869                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2427134250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2427134250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   9937233500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9937233500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  12364367750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12364367750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  12364367750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12364367750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003012                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003012                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.005859                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005859                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.005859                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005859                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39589.838844                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39589.838844                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69219.107424                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69219.107424                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60352.555780                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60352.555780                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60352.555780                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60352.555780                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index ce74a291830b2996d73774d88a4b368d03544bb2..a19ba8014fed8b1e30e132edcacf5f8f29172593 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.064367                       # Number of seconds simulated
+sim_ticks                                 64366581500                       # Number of ticks simulated
 final_tick                                64366581500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 178791                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 302756                       # Number of bytes of host memory used
-host_op_rate                                   253719                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   396.64                       # Real time elapsed on the host
-host_tick_rate                              162280857                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  99170                       # Simulator instruction rate (inst/s)
+host_op_rate                                   140730                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               90012135                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295432                       # Number of bytes of host memory used
+host_seconds                                   715.09                       # Real time elapsed on the host
 sim_insts                                    70915127                       # Number of instructions simulated
 sim_ops                                     100634375                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.064367                       # Number of seconds simulated
-sim_ticks                                 64366581500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst           8259328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8259328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       325696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          325696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5373248                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5373248                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst             129052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                129052                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           83957                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                83957                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            128317021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               128317021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5060017                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5060017                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          83478847                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               83478847                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          83478847                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           128317021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              211795868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        129052                       # Number of read requests accepted
+system.physmem.writeReqs                        83957                       # Number of write requests accepted
+system.physmem.readBursts                      129052                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83957                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8258880                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5371584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8259328                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5373248                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                8196                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8381                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8249                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8185                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8327                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8459                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8094                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7981                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8076                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7644                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7831                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               7843                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7891                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8027                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5181                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5375                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5284                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5034                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5146                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               5344                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5227                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                     64366550000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  129052                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                  83957                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    128466                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5208                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        38820                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.055332                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     212.918314                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     334.655421                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12445     32.06%     32.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8253     21.26%     53.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4125     10.63%     63.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2767      7.13%     71.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2567      6.61%     77.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1675      4.31%     82.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1312      3.38%     85.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1197      3.08%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4479     11.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38820                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.028123                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      359.400532                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5155                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.280116                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.263015                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.779231                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4514     87.57%     87.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  7      0.14%     87.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                501      9.72%     97.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                114      2.21%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 12      0.23%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  3      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5155                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1458157250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3877751000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    645225000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11299.60                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  30049.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         128.31                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          83.45                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      128.32                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       83.48                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           1.65                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.00                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.65                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.63                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112129                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62016                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   86.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.87                       # Row buffer hit rate for writes
+system.physmem.avgGap                       302177.61                       # Average gap between requests
+system.physmem.pageHitRate                      81.76                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      37447706500                       # Time in different power states
+system.physmem.memoryStateTime::REF        2149160000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT       24764549750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    211795868                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               26785                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26785                       # Transaction distribution
+system.membus.trans_dist::Writeback             83957                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102267                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102267                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342061                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 342061                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13632576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            13632576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               13632576                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           975516500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1243562250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.9                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                16883830                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12871662                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            417499                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11152919                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7446252                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             66.765050                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 7446252                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups             11152919                       # Number of BTB lookups
+system.cpu.branchPred.usedRAS                 1514690                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                511                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect            417499                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted          12871662                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                16883830                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 1514690                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    70915127                       # Number of instructions committed
-system.cpu.committedOps                     100634375                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.815313                       # CPI: cycles per instruction
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses::cpu.inst     27634745                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     27634745                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38199.338598                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38199.338598                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.609683                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.609683                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     27577955                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        27577955                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   2169340439                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2169340439                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002055                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002055                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst        56790                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         56790                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         2862                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2862                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2001786311                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2001786311                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.001951                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001951                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        53928                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        53928                       # number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::cpu.inst        15919                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::cpu.inst     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73771.399808                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73771.399808                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.202050                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.202050                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst     19642294                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642294                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  15315459000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  15315459000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.010459                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010459                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst       207607                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207607                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       100574                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100574                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7591658250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   7591658250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       107033                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107033                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     47484646                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     47484646                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.854128                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66130.854128                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59601.049701                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59601.049701                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      47220249                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         47220249                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst  17484799439                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  17484799439                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.005568                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.005568                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst       264397                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         264397                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       103436                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       103436                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9593444561                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9593444561                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003390                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       160961                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       160961                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     47484646                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     47484646                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.854128                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66130.854128                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59601.049701                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59601.049701                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst     47220249                       # number of overall hits
-system.cpu.dcache.overall_hits::total        47220249                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst  17484799439                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  17484799439                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.005568                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.005568                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst       264397                       # number of overall misses
-system.cpu.dcache.overall_misses::total        264397                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       103436                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       103436                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9593444561                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   9593444561                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003390                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       160961                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160961                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          711                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3335                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs            293.562335                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         95193929                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4070.633737                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.993807                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993807                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements            156865                       # number of replacements
-system.cpu.dcache.tags.sampled_refs            160961                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          95193929                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4070.633737                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            47252087                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         802561250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks       128565                       # number of writebacks
-system.cpu.dcache.writebacks::total            128565                       # number of writebacks
-system.cpu.discardedOps                       2952330                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
 system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
 system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
 system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits                                 0                       # DTB hits
-system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.misses                               0                       # DTB misses
-system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses                        0                       # DTB read accesses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
-system.cpu.dtb.write_accesses                       0                       # DTB write accesses
 system.cpu.dtb.write_hits                           0                       # DTB write hits
 system.cpu.dtb.write_misses                         0                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     27472867                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27472867                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19971.672117                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19971.672117                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17929.897070                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17929.897070                       # average ReadReq mshr miss latency
+system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                        0                       # DTB read accesses
+system.cpu.dtb.write_accesses                       0                       # DTB write accesses
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.hits                                 0                       # DTB hits
+system.cpu.dtb.misses                               0                       # DTB misses
+system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
+system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
+system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
+system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
+system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
+system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
+system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
+system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
+system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
+system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
+system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
+system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
+system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
+system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
+system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.inst_hits                            0                       # ITB inst hits
+system.cpu.itb.inst_misses                          0                       # ITB inst misses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.itb.hits                                 0                       # DTB hits
+system.cpu.itb.misses                               0                       # DTB misses
+system.cpu.itb.accesses                             0                       # DTB accesses
+system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.numCycles                        128733163                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    70915127                       # Number of instructions committed
+system.cpu.committedOps                     100634375                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2952341                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.815313                       # CPI: cycles per instruction
+system.cpu.ipc                               0.550869                       # IPC: instructions per cycle
+system.cpu.tickCycles                       109168240                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        19564923                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             43522                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1864.297124                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27427302                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             45564                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            601.951146                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1864.297124                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          727                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1194                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          54991298                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         54991298                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     27427302                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        27427302                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    910009240                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    910009240                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001659                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001659                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_hits::cpu.inst      27427302                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27427302                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27427302                       # number of overall hits
+system.cpu.icache.overall_hits::total        27427302                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        45565                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         45565                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    816975760                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    816975760                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001659                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45565                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        45565                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_misses::cpu.inst        45565                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          45565                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        45565                       # number of overall misses
+system.cpu.icache.overall_misses::total         45565                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    909865240                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    909865240                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    909865240                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    909865240                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    909865240                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    909865240                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27472867                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27472867                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     27472867                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     27472867                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19971.672117                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19971.672117                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17929.897070                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17929.897070                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      27427302                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27427302                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    910009240                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    910009240                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_accesses::cpu.inst     27472867                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27472867                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001659                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001659                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001659                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.001659                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        45565                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          45565                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    816975760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    816975760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001659                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        45565                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        45565                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     27472867                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27472867                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19971.672117                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19971.672117                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17929.897070                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17929.897070                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     27427302                       # number of overall hits
-system.cpu.icache.overall_hits::total        27427302                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    910009240                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    910009240                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001659                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001659                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        45565                       # number of overall misses
-system.cpu.icache.overall_misses::total         45565                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    816975760                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    816975760                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001659                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19968.511796                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19968.511796                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45565                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        45565                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        45565                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        45565                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        45565                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        45565                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          727                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1194                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs            601.951146                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         54991298                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1864.297147                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             43522                       # number of replacements
-system.cpu.icache.tags.sampled_refs             45564                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          54991298                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1864.297147                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27427302                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                        19565206                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.550869                       # IPC: instructions per cycle
-system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits                                 0                       # DTB hits
-system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.itb.inst_hits                            0                       # ITB inst hits
-system.cpu.itb.inst_misses                          0                       # ITB inst misses
-system.cpu.itb.misses                               0                       # DTB misses
-system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107033                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107033                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.821477                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.821477                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.466837                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.466837                       # average ReadExReq mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    816831760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    816831760                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    816831760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    816831760                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    816831760                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    816831760                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001659                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001659                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001659                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001659                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               333181591                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          99493                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         99492                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       128565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107033                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        91129                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       450487                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            541616                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2916096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18529664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       21445760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          21445760                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      296110500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      69298740                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     269478689                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements            95911                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30027.975303                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             100921                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127032                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.794453                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3288.834967                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.816014                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.100367                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.916381                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31121                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1012                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9483                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19900                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          597                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949738                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2914793                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2914793                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        72636                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          72636                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       128565                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       128565                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.inst         4766                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4766                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7436940250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7436940250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955472                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955472                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_hits::cpu.inst        77402                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           77402                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        77402                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          77402                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        26857                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        26857                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.inst       102267                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       102267                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6118068750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6118068750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.955472                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955472                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       102267                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102267                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_misses::cpu.inst       129124                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        129124                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst       129124                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       129124                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1992283500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1992283500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   7436939000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7436939000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   9429222500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   9429222500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   9429222500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   9429222500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        99493                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        99493                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74187.493019                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74187.493019                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.049578                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61477.049578                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst        72636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          72636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1992453500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1992453500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.269939                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.269939                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        26857                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26857                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1646724250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1646724250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.269225                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.269225                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26786                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26786                       # number of ReadReq MSHR misses
 system.cpu.l2cache.Writeback_accesses::writebacks       128565                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       128565                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks       128565                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128565                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst       107033                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107033                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst       206526                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       206526                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73025.880162                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73025.880162                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60167.473829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60167.473829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst        77402                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           77402                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst   9429393750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   9429393750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.625219                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.625219                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst       129124                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        129124                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7764793000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   7764793000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.624875                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       129053                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       129053                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.l2cache.overall_accesses::cpu.inst       206526                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       206526                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73025.880162                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73025.880162                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60167.473829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60167.473829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst        77402                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          77402                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst   9429393750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   9429393750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.269939                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.269939                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.955472                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955472                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.625219                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.625219                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.625219                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.625219                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst       129124                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       129124                       # number of overall misses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        83957                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83957                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           71                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7764793000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   7764793000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.624875                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        26786                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        26786                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       102267                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102267                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       129053                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       129053                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst       129053                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       129053                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1012                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9483                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19900                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          597                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             0.794453                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses         2914793                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 26739.141291                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3288.835051                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.816014                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.100367                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.916381                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31121                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949738                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements            95911                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs           127032                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses          2914793                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        30027.976342                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             100921                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks        83957                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83957                       # number of writebacks
-system.cpu.numCycles                        128733163                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       109167957                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus          21445760                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        91129                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       450487                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            541616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      296110500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      69298740                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     269478939                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               333181591                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2916096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18529664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       21445760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq          99493                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         99492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       128565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107033                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107033                       # Transaction distribution
-system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus               13632576                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342061                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 342061                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy           975516000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1243562500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.9                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    211795868                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13632576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            13632576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq               26785                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26785                       # Transaction distribution
-system.membus.trans_dist::Writeback             83957                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102267                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102267                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       302177.61                       # Average gap between requests
-system.physmem.avgMemAccLat                  30050.93                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       11300.93                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         128.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      128.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                          83.45                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       83.48                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        23.63                       # Average write queue length when enqueuing
-system.physmem.busUtil                           1.65                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.00                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.65                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst         5060017                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5060017                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            128317021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               128317021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          83478847                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           128317021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              211795868                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks          83478847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               83478847                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples        38820                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      351.055332                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     212.915649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     334.657943                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12445     32.06%     32.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8253     21.26%     53.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4125     10.63%     63.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2766      7.13%     71.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2568      6.62%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1673      4.31%     81.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1314      3.38%     85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1198      3.09%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4478     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38820                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                  8258880                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                   8259328                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371584                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                5373248                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       325696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          325696                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst           8259328                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8259328                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks      5373248                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5373248                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE      37439884750                       # Time in different power states
-system.physmem.memoryStateTime::REF        2149160000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT       24772371500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst             129052                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                129052                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83957                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83957                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      81.76                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                8196                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8381                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8249                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8185                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8327                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8459                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8094                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7981                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8076                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7644                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7831                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               7843                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7891                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7977                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8027                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5181                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5375                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5284                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5050                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5034                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5087                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5146                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5344                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5227                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples          5156                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.028123                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      359.400532                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5153     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5156                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                    128466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       557                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                      129052                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  129052                       # Read request sizes (log2)
-system.physmem.readReqs                        129052                       # Number of read requests accepted
-system.physmem.readRowHitRate                   86.89                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     112129                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                    645225000                       # Total ticks spent in databus transfers
-system.physmem.totGap                     64366550000                       # Total gap between requests
-system.physmem.totMemAccLat                3877921750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                     1458328000                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples          5155                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.280116                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.263015                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.779231                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4514     87.57%     87.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  7      0.14%     87.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                501      9.72%     97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                114      2.21%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 12      0.23%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  3      0.06%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5155                       # Writes before turning the bus around for reads
-system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      633                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                      83957                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83957                       # Write request sizes (log2)
-system.physmem.writeReqs                        83957                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  73.87                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                     62016                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1646558250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1646558250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   6118064000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6118064000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7764622250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7764622250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7764622250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   7764622250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.269225                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.269225                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.955472                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955472                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.624875                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.624875                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.624875                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements            156865                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.633737                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            47252087                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160961                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            293.562335                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         802561250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4070.633737                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.993807                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993807                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          711                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3335                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          95193929                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         95193929                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     27577955                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        27577955                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst     19642294                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642294                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.inst        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.inst        15919                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.inst      47220249                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         47220249                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     47220249                       # number of overall hits
+system.cpu.dcache.overall_hits::total        47220249                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst        56790                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         56790                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst       207607                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207607                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst       264397                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         264397                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst       264397                       # number of overall misses
+system.cpu.dcache.overall_misses::total        264397                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst   2169299439                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2169299439                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst  15315314750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  15315314750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  17484614189                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  17484614189                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  17484614189                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  17484614189                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     27634745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     27634745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.inst        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     47484646                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     47484646                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     47484646                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     47484646                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.002055                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002055                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.010459                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010459                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.005568                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.005568                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.005568                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.005568                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66130.153478                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66130.153478                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       128565                       # number of writebacks
+system.cpu.dcache.writebacks::total            128565                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst         2862                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2862                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       100574                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100574                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       103436                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       103436                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       103436                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       103436                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst        53928                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        53928                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       107033                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107033                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst       160961                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       160961                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst       160961                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160961                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   2001760311                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2001760311                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   7591657000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7591657000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst   9593417311                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9593417311                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst   9593417311                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9593417311                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.001951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001951                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003390                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.003390                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003390                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8b5bdef98c99f83afbf38fc179f694006faf3681..fd5fa200e5e1b068171790a2d263d4da95ba444e 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                               1183291184500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 268503                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 248104                       # Number of bytes of host memory used
-host_op_rate                                   268503                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                  6802.08                       # Real time elapsed on the host
-host_tick_rate                              173960186                       # Simulator tick rate (ticks/s)
+sim_seconds                                  1.181828                       # Number of seconds simulated
+sim_ticks                                1181828044500                       # Number of ticks simulated
+final_tick                               1181828044500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 296156                       # Simulator instruction rate (inst/s)
+host_op_rate                                   296156                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              191639126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241048                       # Number of bytes of host memory used
+host_seconds                                  6166.95                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
-sim_seconds                                  1.183291                       # Number of seconds simulated
-sim_ticks                                1183291184500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.726550                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits               164028132                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups            166143892                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect             101063                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect          15659000                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted         184956948                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups               244507485                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                18318035                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                  1826378509                       # Number of instructions committed
-system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.295779                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst    448787942                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    448787942                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24412.387640                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24412.387640                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22378.762178                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22378.762178                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst    441498317                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       441498317                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177957151250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 177957151250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.016243                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016243                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst      7289625                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289625                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        50799                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50799                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 161995965500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 161995965500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.016130                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016130                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7238826                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238826                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45036.490101                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 45036.490101                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40206.712752                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40206.712752                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst    158490258                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158490258                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100802653750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 100802653750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.013926                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013926                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst      2238244                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2238244                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       350933                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       350933                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  75882571250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  75882571250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.011742                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011742                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1887311                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887311                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst    609516444                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    609516444                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29257.308743                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29257.308743                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26065.632890                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26065.632890                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst     599988575                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        599988575                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst 278759805000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 278759805000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.015632                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.015632                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst      9527869                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9527869                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst       401732                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       401732                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237878536750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 237878536750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014973                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014973                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst      9126137                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126137                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst    609516444                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    609516444                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29257.308743                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29257.308743                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26065.632890                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26065.632890                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst    599988575                       # number of overall hits
-system.cpu.dcache.overall_hits::total       599988575                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst 278759805000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 278759805000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.015632                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.015632                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst      9527869                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9527869                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst       401732                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       401732                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237878536750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 237878536750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014973                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014973                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst      9126137                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126137                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1591                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2338                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             65.743981                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses       1228159025                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.562725                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.996231                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996231                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements           9122041                       # number of replacements
-system.cpu.dcache.tags.sampled_refs           9126137                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses        1228159025                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          4080.562725                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           599988575                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       16716397000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks      3700613                       # number of writebacks
-system.cpu.dcache.writebacks::total           3700613                       # number of writebacks
-system.cpu.discardedOps                      50078248                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                620722700                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                    614030991                       # DTB hits
-system.cpu.dtb.data_misses                    6691709                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                457660877                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                    452677890                       # DTB read hits
-system.cpu.dtb.read_misses                    4982987                       # DTB read misses
-system.cpu.dtb.write_accesses               163061823                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                   161353101                       # DTB write hits
-system.cpu.dtb.write_misses                   1708722                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    592077907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    592077907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74367.693111                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74367.693111                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71956.941545                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71956.941545                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst    592076949                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       592076949                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     71244250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     71244250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     68934750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     68934750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          958                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst    592077907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    592077907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74367.693111                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74367.693111                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71956.941545                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71956.941545                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst     592076949                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        592076949                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     71244250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     71244250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     68934750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     68934750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst    592077907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    592077907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74367.693111                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74367.693111                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71956.941545                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71956.941545                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst    592076949                       # number of overall hits
-system.cpu.icache.overall_hits::total       592076949                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     71244250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     71244250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
-system.cpu.icache.overall_misses::total           958                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     68934750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     68934750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs          618034.393528                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses       1184156772                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   750.687488                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.366547                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.366547                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses        1184156772                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           750.687488                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           592076949                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                       321001841                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.771737                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses               592077926                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                   592077907                       # ITB hits
-system.cpu.itb.fetch_misses                        19                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1887311                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887311                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80641.484731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80641.484731                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68018.096944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68018.096944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst      1107870                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1107870                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  62855279500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  62855279500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.412990                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.412990                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       779441                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       779441                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  53016093500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53016093500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.412990                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412990                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       779441                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       779441                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      7239784                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7239784                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79744.744851                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79744.744851                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67168.011379                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67168.011379                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst      6058181                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6058181                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  94226629750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  94226629750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.163210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst      1181603                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1181603                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  79365923750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  79365923750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1181603                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1181603                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks      3700613                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3700613                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks      3700613                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3700613                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst      9127095                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9127095                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80101.165119                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80101.165119                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67505.888318                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67505.888318                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst      7166051                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7166051                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst 157081909250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 157081909250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.214860                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214860                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst      1961044                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1961044                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132382017250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 132382017250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.214860                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214860                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst      1961044                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961044                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst      9127095                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9127095                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80101.165119                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80101.165119                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67505.888318                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67505.888318                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst      7166051                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7166051                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst 157081909250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 157081909250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.214860                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214860                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst      1961044                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1961044                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132382017250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 132382017250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.214860                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214860                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst      1961044                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961044                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1231                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12870                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15515                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             4.586945                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses       106467088                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks 14930.905733                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 15810.667479                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455655                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.482503                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938158                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29804                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements          1928309                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs          1958113                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses        106467088                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse        30741.573213                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8981756                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      88668325250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks::writebacks      1018252                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1018252                       # number of writebacks
-system.cpu.numCycles                       2366582369                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                      2045580528                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus         820973312                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1916                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952887                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21954803                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10114467000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1633750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14012915250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               693804976                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820912000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      820973312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq        7239784                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7239784                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3700613                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887311                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887311                       # Transaction distribution
-system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus              190674944                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940340                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4940340                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy         11933306500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18491731750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    161139495                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190674944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           190674944                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq             1181603                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1181603                       # Transaction distribution
-system.membus.trans_dist::Writeback           1018252                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            779441                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           779441                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                       397171.37                       # Average gap between requests
-system.physmem.avgMemAccLat                  37373.81                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                       18623.81                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         106.00                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      106.07                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                          55.07                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       55.07                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                        25.40                       # Average write queue length when enqueuing
-system.physmem.busUtil                           1.26                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.43                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst           51815                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              51815                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            106065876                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               106065876                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          55073619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           106065876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              161139495                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_write::writebacks          55073619                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               55073619                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples      1832587                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      104.000528                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.206567                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.424181                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1451916     79.23%     79.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       263842     14.40%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        49021      2.67%     96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20912      1.14%     97.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12920      0.71%     98.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7284      0.40%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5395      0.29%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4101      0.22%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        17196      0.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1832587                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                125427328                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                 125506816                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                     79488                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65166528                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys               65168128                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst         125506816                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125506816                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks     65168128                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65168128                       # Number of bytes written to this memory
-system.physmem.memoryStateTime::IDLE     388135850750                       # Time in different power states
-system.physmem.memoryStateTime::REF       39512460000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      755636161750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.bytes_read::cpu.inst         125507328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125507328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65168512                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65168512                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst            1961052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961052                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1018258                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1018258                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst            106197622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               106197622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           51825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              51825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          55142127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               55142127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          55142127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           106197622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              161339749                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961052                       # Number of read requests accepted
+system.physmem.writeReqs                      1018258                       # Number of write requests accepted
+system.physmem.readBursts                     1961052                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1018258                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125425344                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     81984                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65166912                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125507328                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65168512                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1281                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst            1961044                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961044                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1018252                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1018252                       # Number of write requests responded to by this memory
-system.physmem.pageHitRate                      38.46                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0              118755                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118745                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              114099                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116230                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117769                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117839                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117521                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119889                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124535                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126979                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130093                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128642                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116228                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117773                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117823                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117515                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119886                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124512                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126980                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130096                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128651                       # Per bank write bursts
 system.physmem.perBankRdBursts::11             130358                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126048                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125260                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122592                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123193                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61221                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61486                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60571                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61239                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126070                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125261                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122591                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123183                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61220                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61482                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60570                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61238                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               61663                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63103                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64150                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65615                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65333                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65778                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65294                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65644                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64163                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64209                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64571                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64187                       # Per bank write bursts
-system.physmem.rdPerTurnAround::samples         59249                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.075495                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      165.201868                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          59213     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            8      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59249                       # Reads before turning the bus around for writes
-system.physmem.rdQLenPdf::0                   1833824                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    125960                       # What read queue length does an incoming req see
+system.physmem.perBankWrBursts::5               63102                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64153                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65613                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65334                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65779                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65298                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65646                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64168                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64213                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64569                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64185                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1181827934500                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961052                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                1018258                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1833401                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    126352                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -558,37 +125,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                     1961044                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961044                       # Read request sizes (log2)
-system.physmem.readReqs                       1961044                       # Number of read requests accepted
-system.physmem.readRowHitRate                   37.25                       # Row buffer hit rate for reads
-system.physmem.readRowHits                     729960                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                     1242                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                   9799010000                       # Total ticks spent in databus transfers
-system.physmem.totGap                    1183291074500                       # Total gap between requests
-system.physmem.totMemAccLat               73245258000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                    36498970500                       # Total ticks spent queuing
-system.physmem.wrPerTurnAround::samples         59249                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.185556                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.149947                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.108422                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              25999     43.88%     43.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1383      2.33%     46.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              27359     46.18%     92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4006      6.76%     99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                414      0.70%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 70      0.12%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 15      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59249                       # Writes before turning the bus around for reads
 system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
@@ -604,31 +140,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    31537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    59798                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    59784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    59755                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    31610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    59814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    59766                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    59740                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                    59781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    59768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    59810                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                    59797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    59826                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    60270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    59953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    60664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59252                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    59814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    60213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    59934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    60699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       95                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
@@ -653,17 +189,482 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                    1018252                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1018252                       # Write request sizes (log2)
-system.physmem.writeReqs                      1018252                       # Number of write requests accepted
-system.physmem.writeRowHitRate                  40.80                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                    415473                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.bytesPerActivate::samples      1832736                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.991479                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.204587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.379474                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1452314     79.24%     79.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       263429     14.37%     93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        49355      2.69%     96.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20877      1.14%     97.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12925      0.71%     98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7130      0.39%     98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5386      0.29%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4144      0.23%     99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        17176      0.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1832736                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59244                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.077763                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      162.502392                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          59205     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           59244                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59244                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.187108                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.151334                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.111623                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              26003     43.89%     43.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1351      2.28%     46.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              27334     46.14%     92.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4039      6.82%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                439      0.74%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 54      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 18      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  3      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59244                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36544904000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73290610250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9798855000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18647.54                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  37397.54                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         106.13                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          55.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      106.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       55.14                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           1.26                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.43                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.90                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     730029                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    415229                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.78                       # Row buffer hit rate for writes
+system.physmem.avgGap                       396678.40                       # Average gap between requests
+system.physmem.pageHitRate                      38.46                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE     386610550250                       # Time in different power states
+system.physmem.memoryStateTime::REF       39463580000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT      755746527250                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    161339749                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1181614                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1181614                       # Transaction distribution
+system.membus.trans_dist::Writeback           1018258                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            779438                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           779438                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4940362                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4940362                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190675840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           190675840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              190675840                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy         11933572000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        18494807500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               244429252                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         184894637                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15662499                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            166226175                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               163968290                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             98.641679                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18313425                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              99980                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                    452571491                       # DTB read hits
+system.cpu.dtb.read_misses                    4982965                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                457554456                       # DTB read accesses
+system.cpu.dtb.write_hits                   161354418                       # DTB write hits
+system.cpu.dtb.write_misses                   1708765                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses               163063183                       # DTB write accesses
+system.cpu.dtb.data_hits                    613925909                       # DTB hits
+system.cpu.dtb.data_misses                    6691730                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                620617639                       # DTB accesses
+system.cpu.itb.fetch_hits                   591482700                       # ITB hits
+system.cpu.itb.fetch_misses                        19                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses               591482719                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   29                       # Number of system calls
+system.cpu.numCycles                       2363656089                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                  1826378509                       # Number of instructions committed
+system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      49661954                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.294176                       # CPI: cycles per instruction
+system.cpu.ipc                               0.772692                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2043068356                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       320587733                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                 3                       # number of replacements
+system.cpu.icache.tags.tagsinuse           750.459785                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           591481743                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          618058.247649                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   750.459785                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.366435                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.366435                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          873                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1182966357                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1182966357                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    591481743                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       591481743                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     591481743                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        591481743                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    591481743                       # number of overall hits
+system.cpu.icache.overall_hits::total       591481743                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
+system.cpu.icache.overall_misses::total           957                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     70550250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     70550250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     70550250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     70550250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     70550250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     70550250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    591482700                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    591482700                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    591482700                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    591482700                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    591482700                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    591482700                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73720.219436                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73720.219436                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     68248750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     68248750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     68248750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     68248750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     68248750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     68248750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               694662629                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7239687                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239687                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3700672                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887325                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887325                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1914                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21952782                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21954696                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61248                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820910528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      820971776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         820971776                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy    10114514000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1629250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy   14012964250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements          1928316                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30739.409036                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8981710                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1958121                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.586902                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      88667368250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14930.422883                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 15808.986154                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.455640                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.482452                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.938092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29805                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12869                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15516                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106466918                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106466918                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst      6058073                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6058073                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3700672                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3700672                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst      1107887                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1107887                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      7165960                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7165960                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      7165960                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7165960                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst      1181614                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1181614                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst       779438                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       779438                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst      1961052                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1961052                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst      1961052                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1961052                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  94264990000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94264990000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst  62866370000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  62866370000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 157131360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 157131360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 157131360000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 157131360000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      7239687                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7239687                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3700672                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3700672                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst      1887325                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887325                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      9127012                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127012                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      9127012                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127012                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.163213                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.163213                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.412986                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.412986                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.214862                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214862                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.214862                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214862                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79776.466765                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 79776.466765                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.023956                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.023956                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80126.054791                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80126.054791                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80126.054791                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80126.054791                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks      1018258                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1018258                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst      1181614                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1181614                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       779438                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       779438                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst      1961052                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961052                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst      1961052                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961052                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  79403793000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  79403793000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst  53024408000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  53024408000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132428201000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 132428201000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132428201000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 132428201000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.163213                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163213                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.412986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412986                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.214862                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214862                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.214862                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214862                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67199.434841                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67199.434841                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68029.026042                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68029.026042                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67529.163429                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67529.163429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67529.163429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67529.163429                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements           9121959                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.549274                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           599881153                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126055                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.732801                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       16715078000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4080.549274                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.996228                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996228                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1621                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2308                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           64                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1227943655                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1227943655                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst    441390753                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       441390753                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst    158490400                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158490400                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst     599881153                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        599881153                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst    599881153                       # number of overall hits
+system.cpu.dcache.overall_hits::total       599881153                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst      7289545                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289545                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst      2238102                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2238102                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst      9527647                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9527647                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst      9527647                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9527647                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177999429500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177999429500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100859304250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 100859304250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 278858733750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 278858733750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 278858733750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 278858733750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst    448680298                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    448680298                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst    609408800                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    609408800                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst    609408800                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    609408800                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.016247                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.016247                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.013925                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013925                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.015634                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015634                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.015634                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015634                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24418.455404                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24418.455404                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45064.659363                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 45064.659363                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29268.373792                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29268.373792                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29268.373792                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29268.373792                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      3700672                       # number of writebacks
+system.cpu.dcache.writebacks::total           3700672                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        50815                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50815                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       350777                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       350777                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst       401592                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       401592                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst       401592                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       401592                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst      1887325                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887325                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst      9126055                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126055                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst      9126055                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126055                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  75893768500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  75893768500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 237927598250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 237927598250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.016133                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016133                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.011742                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011742                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.014975                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014975                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.014975                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014975                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 98d3f10249aa0e0678011783ece396851112c6c1..2c6817645a5c00708969071431c08eccdfdee12c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-final_tick                                51810521500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                 191326                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 251752                       # Number of bytes of host memory used
-host_op_rate                                   191326                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                   480.35                       # Real time elapsed on the host
-host_tick_rate                              107860315                       # Simulator tick rate (ticks/s)
+sim_seconds                                  0.051523                       # Number of seconds simulated
+sim_ticks                                 51522973500                       # Number of ticks simulated
+final_tick                                51522973500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                 192794                       # Simulator instruction rate (inst/s)
+host_op_rate                                   192794                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              108084557                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244692                       # Number of bytes of host memory used
+host_seconds                                   476.69                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.051811                       # Number of seconds simulated
-sim_ticks                                 51810521500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             79.960972                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                 5346983                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups              6686991                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect            788623                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted           8172556                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                11403069                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                 1173096                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                    91903089                       # Number of instructions committed
-system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.cpi                               1.127503                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst     20044127                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20044127                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 69928.365385                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69928.365385                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 68014.432990                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68014.432990                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst     20043607                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20043607                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     36362750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     36362750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000026                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst          520                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           520                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           35                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           35                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     32987000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     32987000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          485                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67476.975945                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 67476.975945                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68165.329513                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68165.329513                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst      6498193                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6498193                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    196358000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    196358000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000448                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000448                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst         2910                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2910                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    118948500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    118948500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000268                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000268                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         1745                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1745                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst     26545230                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26545230                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67848.615160                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67848.615160                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68132.511211                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68132.511211                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst      26541800                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26541800                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst    232720750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    232720750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.000129                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst         3430                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst         1200                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1200                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    151935500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    151935500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst         2230                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst     26545230                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26545230                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67848.615160                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67848.615160                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68132.511211                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68132.511211                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst     26541800                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26541800                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst    232720750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    232720750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst         3430                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst         1200                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1200                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    151935500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    151935500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst         2230                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs          11902.152466                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses         53092690                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.584633                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.353658                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353658                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses          53092690                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse          1448.584633                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26541800                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
-system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.discardedOps                       2238069                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                 27017530                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                     26970236                       # DTB hits
-system.cpu.dtb.data_misses                      47294                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                 20437728                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                     20390711                       # DTB read hits
-system.cpu.dtb.read_misses                      47017                       # DTB read misses
-system.cpu.dtb.write_accesses                 6579802                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                     6579525                       # DTB write hits
-system.cpu.dtb.write_misses                       277                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     22978908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22978908                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24673.484027                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24673.484027                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22586.223937                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22586.223937                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::cpu.inst     22963225                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22963225                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    386954250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    386954250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000682                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000682                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst        15683                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15683                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    354219750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    354219750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000682                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15683                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15683                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst     22978908                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22978908                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24673.484027                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24673.484027                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22586.223937                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22586.223937                       # average overall mshr miss latency
-system.cpu.icache.demand_hits::cpu.inst      22963225                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22963225                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst    386954250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    386954250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000682                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000682                       # miss rate for demand accesses
-system.cpu.icache.demand_misses::cpu.inst        15683                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15683                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    354219750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    354219750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000682                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15683                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15683                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses::cpu.inst     22978908                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22978908                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24673.484027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24673.484027                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22586.223937                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22586.223937                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst     22963225                       # number of overall hits
-system.cpu.icache.overall_hits::total        22963225                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst    386954250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    386954250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000682                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000682                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst        15683                       # number of overall misses
-system.cpu.icache.overall_misses::total         15683                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    354219750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    354219750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000682                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15683                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15683                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          668                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          948                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs           1464.211248                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses         45973499                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.514711                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801521                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801521                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements             13718                       # number of replacements
-system.cpu.icache.tags.sampled_refs             15683                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses          45973499                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse          1641.514711                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22963225                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                         2226173                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.886915                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                22978996                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                    22978908                       # ITB hits
-system.cpu.itb.fetch_misses                        88                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68029.959279                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68029.959279                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55498.836533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55498.836533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits::cpu.inst           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    116943500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    116943500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst         1719                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     95402500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95402500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        16168                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        16168                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68200.931332                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68200.931332                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55638.518210                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55638.518210                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12571                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          12571                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    245318750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    245318750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.222476                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.222476                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3597                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3597                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    200131750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    200131750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.222476                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.222476                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3597                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst        17913                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        17913                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68145.645222                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68145.645222                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55593.350263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55593.350263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst        12597                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           12597                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst    362262250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    362262250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.296768                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.296768                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst         5316                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5316                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    295534250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    295534250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.296768                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.296768                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         5316                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5316                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst        17913                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        17913                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68145.645222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68145.645222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55593.350263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55593.350263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst        12597                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          12597                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst    362262250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    362262250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.296768                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.296768                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst         5316                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5316                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    295534250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    295534250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.296768                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.296768                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         5316                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5316                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          767                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          181                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2506                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             3.435708                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses          149568                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.784221                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2462.008081                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075135                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.075677                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3663                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111786                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs             3663                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses           149568                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse         2479.792302                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              12585                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                        103621043                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                       101394870                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus           1153280                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31366                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4567                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             35933                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        9117000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24208750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3732500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput                22259571                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1003712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total        1153280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq          16168                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         16168                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                 340224                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10632                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy             6066000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           49708250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                      6566697                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              340224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                3597                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3597                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                      9746132.43                       # Average gap between requests
-system.physmem.avgMemAccLat                  25349.60                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        6599.60                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                           6.57                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.57                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst         3909631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3909631                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              6566697                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6566697                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             6566697                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6566697                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples          980                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      346.710204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     212.810529                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.902824                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            318     32.45%     32.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          196     20.00%     52.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          101     10.31%     62.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           95      9.69%     72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           76      7.76%     80.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           37      3.78%     83.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           22      2.24%     86.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           21      2.14%     88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          114     11.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            980                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                   340224                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                    340224                       # Total read bytes from the system interface side
+system.physmem.bytes_read::cpu.inst            340096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               340096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202432                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               5314                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5314                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              6600861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6600861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3928966                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3928966                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             6600861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6600861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5314                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                        5314                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                   340096                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                    340096                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst       202560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst            340224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340224                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE      48729835000                       # Time in different power states
-system.physmem.memoryStateTime::REF        1730040000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1350106250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst               5316                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5316                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      81.55                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 468                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 295                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 307                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
@@ -485,7 +49,7 @@ system.physmem.perBankRdBursts::8                 251                       # Pe
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                255                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                260                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                409                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                408                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                344                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                500                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                448                       # Per bank write bursts
@@ -505,9 +69,26 @@ system.physmem.perBankWrBursts::12                  0                       # Pe
 system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                      4911                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                     51522892000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5314                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                      4908                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -537,22 +118,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                        5316                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5316                       # Read request sizes (log2)
-system.physmem.readReqs                          5316                       # Number of read requests accepted
-system.physmem.readRowHitRate                   81.55                       # Row buffer hit rate for reads
-system.physmem.readRowHits                       4335                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                     26580000                       # Total ticks spent in databus transfers
-system.physmem.totGap                     51810440000                       # Total gap between requests
-system.physmem.totMemAccLat                 134758500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                       35083500                       # Total ticks spent queuing
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -617,17 +182,452 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.bytesPerActivate::samples          970                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      349.690722                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     213.310004                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     331.842695                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            314     32.37%     32.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          200     20.62%     52.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           99     10.21%     63.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           77      7.94%     71.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           82      8.45%     79.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           28      2.89%     82.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           30      3.09%     85.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           24      2.47%     88.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          116     11.96%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            970                       # Bytes accessed per row activation
+system.physmem.totQLat                       35128750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 134766250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26570000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6610.60                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  25360.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.60                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                       4339                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.physmem.readRowHitRate                   81.65                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9695689.12                       # Average gap between requests
+system.physmem.pageHitRate                      81.65                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE      48460398500                       # Time in different power states
+system.physmem.memoryStateTime::REF        1720420000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT        1341071500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                      6600861                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3595                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3595                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10628                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              340096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 340096                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy             6106000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           49717250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                11407310                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8177170                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            788660                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6672659                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5348436                       # Number of BTB hits
+system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct             80.154493                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1172954                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                     20390002                       # DTB read hits
+system.cpu.dtb.read_misses                      46972                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20436974                       # DTB read accesses
+system.cpu.dtb.write_hits                     6579989                       # DTB write hits
+system.cpu.dtb.write_misses                       273                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                 6580262                       # DTB write accesses
+system.cpu.dtb.data_hits                     26969991                       # DTB hits
+system.cpu.dtb.data_misses                      47245                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                 27017236                       # DTB accesses
+system.cpu.itb.fetch_hits                    22956123                       # ITB hits
+system.cpu.itb.fetch_misses                        88                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                22956211                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                  389                       # Number of system calls
+system.cpu.numCycles                        103045947                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                    91903089                       # Number of instructions committed
+system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2250201                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                               1.121246                       # CPI: cycles per instruction
+system.cpu.ipc                               0.891865                       # IPC: instructions per cycle
+system.cpu.tickCycles                       100852498                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         2193449                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements             13697                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1640.300459                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22940462                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15661                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1464.814635                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.300459                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.800928                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.800928                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          670                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          947                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          45927907                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45927907                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22940462                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22940462                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22940462                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22940462                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22940462                       # number of overall hits
+system.cpu.icache.overall_hits::total        22940462                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15661                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15661                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15661                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15661                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15661                       # number of overall misses
+system.cpu.icache.overall_misses::total         15661                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    385817000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    385817000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    385817000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    385817000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    385817000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    385817000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22956123                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22956123                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22956123                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22956123                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22956123                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22956123                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000682                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000682                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000682                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000682                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000682                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000682                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24635.527744                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24635.527744                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15661                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15661                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15661                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15661                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15661                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15661                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353131000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    353131000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353131000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    353131000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353131000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    353131000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000682                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000682                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000682                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000682                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput                22356474                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          16146                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16146                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31322                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4567                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             35889                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1002304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        1151872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus           1151872                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        9106000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      24173500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       3734250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse         2477.580709                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              12565                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3661                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             3.432122                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.790278                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2459.790431                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075067                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.075610                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3661                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          768                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2504                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111725                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           149390                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          149390                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12551                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          12551                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.inst           26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        12577                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           12577                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12577                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          12577                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3595                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3595                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.inst         1719                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         5314                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5314                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         5314                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5314                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    245039250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    245039250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    117228000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    117228000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    362267250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    362267250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    362267250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    362267250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        16146                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        16146                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst         1745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        17891                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        17891                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        17891                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        17891                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.222656                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.222656                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.985100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.297021                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.297021                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.297021                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.297021                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3595                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3595                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         1719                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5314                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5314                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5314                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5314                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    199861250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    199861250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     95675500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95675500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    295536750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    295536750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    295536750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    295536750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.222656                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.222656                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.297021                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.297021                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.297021                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.297021                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements               157                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1448.553123                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26545427                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11903.778924                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.553123                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.353651                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353651                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          53099944                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53099944                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst     20047235                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20047235                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst      6498192                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6498192                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst      26545427                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26545427                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst     26545427                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26545427                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          519                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           519                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst         2911                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2911                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst         3430                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst         3430                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     36876750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     36876750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    198662500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    198662500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    235539250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235539250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    235539250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235539250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst     20047754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20047754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst     26548857                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26548857                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst     26548857                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26548857                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000026                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000448                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000448                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.000129                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.000129                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68670.335277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68670.335277                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
+system.cpu.dcache.writebacks::total               107                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           34                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           34                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         1166                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         1166                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst         1200                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1200                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst         1200                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1200                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          485                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         1745                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1745                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst         2230                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst         2230                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     33572250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     33572250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    119233500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    119233500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    152805750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    152805750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    152805750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    152805750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000268                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000268                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 39aafd883af158ec70e3c60e83c453a86e622bcf..b10a33b7292d1aa57226002fad5e75c06fb7d491 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000035                       # Number of seconds simulated
+sim_ticks                                    35015500                       # Number of ticks simulated
 final_tick                                   35015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                  59280                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 248380                       # Number of bytes of host memory used
-host_op_rate                                    59280                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                              324332505                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  57020                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57008                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              311836228                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240292                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.000035                       # Number of seconds simulated
-sim_ticks                                    35015500                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst             34112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34112                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            974197141                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               974197141                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       665305365                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          665305365                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           974197141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              974197141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           533                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                    34112                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                     34112                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                  73                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                  36                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  54                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  45                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                  21                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                   5                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 22                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 29                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 19                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                127                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 47                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                 14                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                        34917000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     533                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                       439                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        89                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           90                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      365.511111                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     232.220198                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.209697                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             22     24.44%     24.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           24     26.67%     51.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           10     11.11%     62.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8      8.89%     71.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      4.44%     75.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            7      7.78%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.11%     84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      4.44%     88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     11.11%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             90                       # Bytes accessed per row activation
+system.physmem.totQLat                        3823500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13817250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7173.55                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  25923.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         974.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      974.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           7.61                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.61                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                        435                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                        65510.32                       # Average gap between requests
+system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
+system.physmem.memoryStateTime::REF           1040000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          30385500                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                    974197141                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
+system.membus.trans_dist::ReadResp                460                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               34112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  34112                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy              618000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4976250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                    1959                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1201                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 1551                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     381                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             24.564797                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                     381                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups                 1551                       # Number of BTB lookups
-system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted              1201                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                    1959                       # Number of BP lookups
 system.cpu.branchPred.usedRAS                     224                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 14                       # Number of incorrect RAS predictions.
+system.cpu.dtb.fetch_hits                           0                       # ITB hits
+system.cpu.dtb.fetch_misses                         0                       # ITB misses
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
+system.cpu.dtb.read_hits                         1368                       # DTB read hits
+system.cpu.dtb.read_misses                         11                       # DTB read misses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_accesses                     1379                       # DTB read accesses
+system.cpu.dtb.write_hits                         884                       # DTB write hits
+system.cpu.dtb.write_misses                         3                       # DTB write misses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     887                       # DTB write accesses
+system.cpu.dtb.data_hits                         2252                       # DTB hits
+system.cpu.dtb.data_misses                         14                       # DTB misses
+system.cpu.dtb.data_acv                             0                       # DTB access violations
+system.cpu.dtb.data_accesses                     2266                       # DTB accesses
+system.cpu.itb.fetch_hits                        2630                       # ITB hits
+system.cpu.itb.fetch_misses                        17                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                    2647                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                   17                       # Number of system calls
+system.cpu.numCycles                            70031                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                          1118                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                              10.942344                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1330                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 78029.411765                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78029.411765                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 76945.312500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76945.312500                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst         1228                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1228                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7959000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7959000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076692                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7386750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7386750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.072180                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69500                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        69500                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70147.260274                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70147.260274                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8687500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8687500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5120750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5120750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2195                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73332.599119                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73332.599119                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 74008.875740                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74008.875740                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst          1968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst     16646500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16646500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.103417                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12507500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12507500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076993                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2195                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73332.599119                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73332.599119                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 74008.875740                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74008.875740                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst         1968                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1968                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst     16646500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16646500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.103417                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
-system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12507500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12507500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076993                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs             11.644970                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses             4559                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst   103.870916                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.025359                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025359                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses              4559                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse           103.870916                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1968                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.discardedOps                          1111                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                     2266                       # DTB accesses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_hits                         2252                       # DTB hits
-system.cpu.dtb.data_misses                         14                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
-system.cpu.dtb.fetch_hits                           0                       # ITB hits
-system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                     1379                       # DTB read accesses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_hits                         1368                       # DTB read hits
-system.cpu.dtb.read_misses                         11                       # DTB read misses
-system.cpu.dtb.write_accesses                     887                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_hits                         884                       # DTB write hits
-system.cpu.dtb.write_misses                         3                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2630                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70238.356164                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70238.356164                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67805.479452                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67805.479452                       # average ReadReq mshr miss latency
+system.cpu.ipc                               0.091388                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12510                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           57521                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           176.143820                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                2265                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.205479                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   176.143820                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.086008                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.086008                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              5625                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5625                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         2265                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2265                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25637000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25637000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.138783                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24749000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24749000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138783                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          365                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          365                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst         2630                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2630                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70238.356164                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70238.356164                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67805.479452                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67805.479452                       # average overall mshr miss latency
 system.cpu.icache.demand_hits::cpu.inst          2265                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total             2265                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     25637000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25637000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.138783                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.138783                       # miss rate for demand accesses
+system.cpu.icache.overall_hits::cpu.inst         2265                       # number of overall hits
+system.cpu.icache.overall_hits::total            2265                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          365                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           365                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          365                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24749000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.138783                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
+system.cpu.icache.overall_misses::total           365                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25932750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25932750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25932750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25932750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25932750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25932750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2630                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2630                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2630                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2630                       # number of demand (read+write) accesses
 system.cpu.icache.overall_accesses::cpu.inst         2630                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         2630                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70238.356164                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70238.356164                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67805.479452                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67805.479452                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst         2265                       # number of overall hits
-system.cpu.icache.overall_hits::total            2265                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     25637000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25637000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.138783                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.138783                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.138783                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.138783                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.138783                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.138783                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
-system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24749000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24749000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.138783                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71048.630137                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71048.630137                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          365                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          365                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          365                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs              6.205479                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses             5625                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   175.902434                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085890                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085890                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses              5625                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           175.902434                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                2265                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                           57521                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.091388                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                    2647                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                        2630                       # ITB hits
-system.cpu.itb.fetch_misses                        17                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69126.712329                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69126.712329                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56544.520548                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56544.520548                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5046250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5046250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25045250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25045250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25045250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25045250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25045250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25045250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138783                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.138783                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138783                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.138783                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               976024903                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          34176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             34176                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        626250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          233.878182                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.878182                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          460                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          460                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.inst           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4127750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4127750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_misses::cpu.inst          533                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31726750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     31726750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     36782750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36782750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     36782750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36782750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          461                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68832.065217                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68832.065217                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.891304                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56304.891304                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31662750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31662750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          534                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          534                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          534                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          534                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.997831                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.997831                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25900250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25900250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst          534                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          534                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68872.420263                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68872.420263                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56337.711069                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56337.711069                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36709000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     36709000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst          533                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30028000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30028000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          460                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          460                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          533                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst          534                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          534                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68872.420263                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68872.420263                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56337.711069                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56337.711069                       # average overall mshr miss latency
-system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36709000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     36709000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30028000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30028000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          533                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.550813                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007127                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007127                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse          233.550813                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                            70031                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                           12510                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus             34176                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          730                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          338                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1068                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        626500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput               976024903                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          34176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           73                       # Transaction distribution
-system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                  34112                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1066                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1066                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy              617000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4977500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                    974197141                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               34112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                 460                       # Transaction distribution
-system.membus.trans_dist::ReadResp                460                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               73                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                        65510.32                       # Average gap between requests
-system.physmem.avgMemAccLat                  25799.25                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        7049.25                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                         974.20                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      974.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           7.61                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.61                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst       665305365                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          665305365                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst            974197141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               974197141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           974197141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              974197141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples           89                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      369.617978                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     234.259007                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.584548                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             22     24.72%     24.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255           23     25.84%     50.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           10     11.24%     61.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            8      8.99%     70.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            4      4.49%     75.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            6      6.74%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            2      2.25%     84.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            4      4.49%     88.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           10     11.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             89                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                    34112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                     34112                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        23296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst             34112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34112                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
-system.physmem.memoryStateTime::REF           1040000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          30385500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      81.80                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                  73                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                  36                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  54                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  45                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                  21                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                   5                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 22                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 29                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 19                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                127                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 47                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                 14                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                       440                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        88                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     533                       # Read request sizes (log2)
-system.physmem.readReqs                           533                       # Number of read requests accepted
-system.physmem.readRowHitRate                   81.80                       # Row buffer hit rate for reads
-system.physmem.readRowHits                        436                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.totGap                        34917000                       # Total gap between requests
-system.physmem.totMemAccLat                  13751000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                        3757250                       # Total ticks spent queuing
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25965250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25965250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4138000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4138000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30103250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30103250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30103250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30103250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           104.053835                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1968                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.644970                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst   104.053835                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.025404                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025404                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4559                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4559                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst         1228                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1228                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst          1968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst         1968                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
+system.cpu.dcache.overall_misses::total           227                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7727250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7727250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8696750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8696750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst     16424000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16424000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst     16424000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16424000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst         1330                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1330                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst         2195                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2195                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst         2195                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2195                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076692                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.076692                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.103417                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.103417                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.103417                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.103417                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69574                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        69574                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72352.422907                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72352.422907                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7154500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7154500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5130500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5130500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12285000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12285000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.072180                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.072180                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076993                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076993                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076993                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index e8ab0ad04cdb28b8c48b3caee722221f2334d466..7e0b73788c0d58ec08d7773f3102153621a3137c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000019                       # Number of seconds simulated
+sim_ticks                                    18662000                       # Number of ticks simulated
 final_tick                                   18662000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-host_inst_rate                                  42585                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 247072                       # Number of bytes of host memory used
-host_op_rate                                    42585                       # Simulator op (including micro ops) rate (op/s)
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              307435077                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_inst_rate                                  32674                       # Simulator instruction rate (inst/s)
+host_op_rate                                    32664                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              235769003                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238980                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
-sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    18662000                       # Number of ticks simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst             19712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                19712                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        14272                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           14272                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                308                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1056264066                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1056264066                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       764762619                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          764762619                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1056264066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1056264066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           308                       # Number of read requests accepted
+system.physmem.writeReqs                            0                       # Number of write requests accepted
+system.physmem.readBursts                         308                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                    19712                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                     19712                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                   0                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                   3                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  24                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                  21                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                  27                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                  47                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                  68                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                 15                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                 14                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                 18                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                 52                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                 15                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                  1                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
+system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                        18580000                       # Total gap between requests
+system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     308                       # Read request sizes (log2)
+system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
+system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           44                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      411.636364                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     270.438338                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.932860                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             11     25.00%     25.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            7     15.91%     40.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            4      9.09%     50.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      6.82%     56.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6     13.64%     70.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            5     11.36%     81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      6.82%     88.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      2.27%     90.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            4      9.09%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             44                       # Bytes accessed per row activation
+system.physmem.totQLat                        1654250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7429250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        5370.94                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  24120.94                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1056.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1056.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil                           8.25                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       8.25                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
+system.physmem.readRowHits                        256                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
+system.physmem.avgGap                        60324.68                       # Average gap between requests
+system.physmem.pageHitRate                      83.12                       # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
+system.physmem.memoryStateTime::REF            520000                       # Time in different power states
+system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
+system.physmem.memoryStateTime::ACT          15310750                       # Time in different power states
+system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
+system.membus.throughput                   1056264066                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
+system.membus.trans_dist::ReadResp                281                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          616                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    616                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               19712                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  19712                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy              362000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2870500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             15.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups                     786                       # Number of BP lookups
+system.cpu.branchPred.condPredicted               393                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                  558                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                      58                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             10.394265                       # BTB Hit Percentage
-system.cpu.branchPred.BTBHits                      58                       # Number of BTB hits
-system.cpu.branchPred.BTBLookups                  558                       # Number of BTB lookups
+system.cpu.branchPred.usedRAS                     139                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  2                       # Number of incorrect RAS predictions.
-system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
-system.cpu.branchPred.condPredicted               393                       # Number of conditional branches predicted
-system.cpu.branchPred.lookups                     785                       # Number of BP lookups
-system.cpu.branchPred.usedRAS                     138                       # Number of times the RAS was used to get a target.
-system.cpu.committedInsts                        2585                       # Number of instructions committed
-system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
-system.cpu.cpi                              14.438685                       # CPI: cycles per instruction
-system.cpu.dcache.ReadReq_accesses::cpu.inst          497                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          497                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75877.049180                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75877.049180                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74034.482759                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74034.482759                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits::cpu.inst          436                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             436                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4628500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4628500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.122736                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.122736                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::cpu.inst           61                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4294000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4294000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.116700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116700                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           58                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69872.093023                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69872.093023                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67768.518519                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67768.518519                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits::cpu.inst          251                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3004500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3004500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::cpu.inst           43                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      1829750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1829750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           27                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses::cpu.inst          791                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          791                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73394.230769                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73394.230769                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72044.117647                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.117647                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits::cpu.inst           687                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              687                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::cpu.inst      7633000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7633000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.131479                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.131479                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses::cpu.inst          104                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6123750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6123750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.107459                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::cpu.inst           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses::cpu.inst          791                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          791                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73394.230769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73394.230769                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72044.117647                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.117647                       # average overall mshr miss latency
-system.cpu.dcache.overall_hits::cpu.inst          687                       # number of overall hits
-system.cpu.dcache.overall_hits::total             687                       # number of overall hits
-system.cpu.dcache.overall_miss_latency::cpu.inst      7633000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7633000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.131479                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.131479                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
-system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6123750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6123750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.107459                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.avg_refs              8.082353                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.data_accesses             1667                       # Number of data accesses
-system.cpu.dcache.tags.occ_blocks::cpu.inst    48.695278                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.011888                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011888                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.tag_accesses              1667                       # Number of tag accesses
-system.cpu.dcache.tags.tagsinuse            48.695278                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 687                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.discardedOps                           631                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.dtb.data_accesses                      828                       # DTB accesses
-system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_hits                          815                       # DTB hits
-system.cpu.dtb.data_misses                         13                       # DTB misses
-system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
-system.cpu.dtb.read_accesses                      515                       # DTB read accesses
-system.cpu.dtb.read_acv                             1                       # DTB read access violations
+system.cpu.dtb.fetch_acv                            0                       # ITB acv
+system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
 system.cpu.dtb.read_hits                          508                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
-system.cpu.dtb.write_accesses                     313                       # DTB write accesses
-system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.read_acv                             1                       # DTB read access violations
+system.cpu.dtb.read_accesses                      515                       # DTB read accesses
 system.cpu.dtb.write_hits                         307                       # DTB write hits
 system.cpu.dtb.write_misses                         6                       # DTB write misses
-system.cpu.icache.ReadReq_accesses::cpu.inst          962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          962                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69306.053812                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69306.053812                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66882.286996                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66882.286996                       # average ReadReq mshr miss latency
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_accesses                     313                       # DTB write accesses
+system.cpu.dtb.data_hits                          815                       # DTB hits
+system.cpu.dtb.data_misses                         13                       # DTB misses
+system.cpu.dtb.data_acv                             1                       # DTB access violations
+system.cpu.dtb.data_accesses                      828                       # DTB accesses
+system.cpu.itb.fetch_hits                         962                       # ITB hits
+system.cpu.itb.fetch_misses                        13                       # ITB misses
+system.cpu.itb.fetch_acv                            0                       # ITB acv
+system.cpu.itb.fetch_accesses                     975                       # ITB accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.read_acv                             0                       # DTB read access violations
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.itb.write_acv                            0                       # DTB write access violations
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.data_hits                            0                       # DTB hits
+system.cpu.itb.data_misses                          0                       # DTB misses
+system.cpu.itb.data_acv                             0                       # DTB access violations
+system.cpu.itb.data_accesses                        0                       # DTB accesses
+system.cpu.workload.num_syscalls                    4                       # Number of system calls
+system.cpu.numCycles                            37324                       # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.committedInsts                        2585                       # Number of instructions committed
+system.cpu.committedOps                          2585                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                           635                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
+system.cpu.cpi                              14.438685                       # CPI: cycles per instruction
+system.cpu.ipc                               0.069258                       # IPC: instructions per cycle
+system.cpu.tickCycles                            5337                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           31987                       # Total number of cycles that the object has spent stopped
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           118.813999                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                 739                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.313901                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   118.813999                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.058015                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.058015                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              2147                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2147                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst          739                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             739                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15455250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15455250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.231809                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.231809                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::cpu.inst          223                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           223                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14914750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14914750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231809                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          223                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses::cpu.inst          962                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          962                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69306.053812                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69306.053812                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66882.286996                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66882.286996                       # average overall mshr miss latency
 system.cpu.icache.demand_hits::cpu.inst           739                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total              739                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::cpu.inst     15455250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15455250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::cpu.inst     0.231809                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.231809                       # miss rate for demand accesses
+system.cpu.icache.overall_hits::cpu.inst          739                       # number of overall hits
+system.cpu.icache.overall_hits::total             739                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          223                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           223                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          223                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            223                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14914750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14914750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.231809                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses::cpu.inst          223                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
+system.cpu.icache.overall_misses::total           223                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15454750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15454750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15454750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15454750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15454750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15454750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          962                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          962                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          962                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          962                       # number of demand (read+write) accesses
 system.cpu.icache.overall_accesses::cpu.inst          962                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total          962                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69306.053812                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69306.053812                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66882.286996                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66882.286996                       # average overall mshr miss latency
-system.cpu.icache.overall_hits::cpu.inst          739                       # number of overall hits
-system.cpu.icache.overall_hits::total             739                       # number of overall hits
-system.cpu.icache.overall_miss_latency::cpu.inst     15455250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15455250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.231809                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.231809                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.231809                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.231809                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.231809                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.231809                       # miss rate for overall accesses
-system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
-system.cpu.icache.overall_misses::total           223                       # number of overall misses
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14914750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14914750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.231809                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69303.811659                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69303.811659                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69303.811659                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69303.811659                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69303.811659                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69303.811659                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          223                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          223                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
-system.cpu.icache.tags.avg_refs              3.313901                       # Average number of references to valid blocks.
-system.cpu.icache.tags.data_accesses             2147                       # Number of data accesses
-system.cpu.icache.tags.occ_blocks::cpu.inst   118.799156                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.058007                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.058007                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.108887                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.tag_accesses              2147                       # Number of tag accesses
-system.cpu.icache.tags.tagsinuse           118.799156                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 739                       # Total number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.idleCycles                           31983                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.ipc                               0.069258                       # IPC: instructions per cycle
-system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.itb.data_acv                             0                       # DTB access violations
-system.cpu.itb.data_hits                            0                       # DTB hits
-system.cpu.itb.data_misses                          0                       # DTB misses
-system.cpu.itb.fetch_accesses                     974                       # ITB accesses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_hits                         962                       # ITB hits
-system.cpu.itb.fetch_misses                        12                       # ITB misses
-system.cpu.itb.read_accesses                        0                       # DTB read accesses
-system.cpu.itb.read_acv                             0                       # DTB read access violations
-system.cpu.itb.read_hits                            0                       # DTB read hits
-system.cpu.itb.read_misses                          0                       # DTB read misses
-system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.write_acv                            0                       # DTB write access violations
-system.cpu.itb.write_hits                           0                       # DTB write hits
-system.cpu.itb.write_misses                         0                       # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           27                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst        66750                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        66750                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54490.740741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54490.740741                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      1802250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1802250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14914250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14914250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14914250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14914250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14914250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14914250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231809                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.231809                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231809                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.231809                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66880.044843                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843                       # average overall mshr miss latency
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput              1056264066                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          446                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               616                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          19712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             19712                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        381750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        136250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          146.987026                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.987026                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004486                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004486                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          139                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008575                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             2772                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            2772                       # Number of data accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          281                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          281                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.inst           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1471250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1471250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           27                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_misses::cpu.inst          308                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           308                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          308                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18929750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18929750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      1803250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1803250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20733000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     20733000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20733000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     20733000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          281                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          281                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67356.761566                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67356.761566                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54830.071174                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54830.071174                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18927250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18927250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses::cpu.inst           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          308                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          308                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          308                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          308                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          281                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          281                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15407250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15407250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          281                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67365.658363                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67365.658363                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66787.037037                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66787.037037                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67314.935065                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67314.935065                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67314.935065                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67314.935065                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses::cpu.inst          308                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          308                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67303.571429                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67303.571429                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54800.324675                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54800.324675                       # average overall mshr miss latency
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20729500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20729500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses::cpu.inst          308                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           308                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16878500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16878500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          308                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          308                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses::cpu.inst          308                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          308                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67303.571429                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67303.571429                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54800.324675                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54800.324675                       # average overall mshr miss latency
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20729500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20729500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses::cpu.inst          308                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16878500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16878500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          308                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          139                       # Occupied blocks per task id
-system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.data_accesses            2772                       # Number of data accesses
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.968700                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004485                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004485                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008575                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.tag_accesses             2772                       # Number of tag accesses
-system.cpu.l2cache.tags.tagsinuse          146.968700                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.numCycles                            37324                       # number of cpu cycles simulated
-system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.tickCycles                            5341                       # Number of cycles that the CPU actually ticked
-system.cpu.toL2Bus.data_through_bus             19712                       # Total data (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          446                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               616                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        381750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        136250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.throughput              1056264066                       # Throughput (bytes/s)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        14272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          19712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           27                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           27                       # Transaction distribution
-system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.membus.data_through_bus                  19712                       # Total data (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    616                       # Packet count per connected master and slave (bytes)
-system.membus.reqLayer0.occupancy              362500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2871000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             15.4                       # Layer utilization (%)
-system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.throughput                   1056264066                       # Throughput (bytes/s)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        19712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               19712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
-system.membus.trans_dist::ReadResp                281                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                27                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               27                       # Transaction distribution
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgGap                        60324.68                       # Average gap between requests
-system.physmem.avgMemAccLat                  24109.58                       # Average memory access latency per DRAM burst
-system.physmem.avgQLat                        5359.58                       # Average queueing delay per DRAM burst
-system.physmem.avgRdBW                        1056.26                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1056.26                       # Average system read bandwidth in MiByte/s
-system.physmem.avgRdQLen                         1.25                       # Average read queue length when enqueuing
-system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
-system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.busUtil                           8.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       8.25                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.bw_inst_read::cpu.inst       764762619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          764762619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst           1056264066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1056264066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1056264066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1056264066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytesPerActivate::samples           44                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      411.636364                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     270.438338                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.932860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127             11     25.00%     25.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255            7     15.91%     40.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383            4      9.09%     50.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511            3      6.82%     56.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639            6     13.64%     70.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767            5     11.36%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895            3      6.82%     88.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023            1      2.27%     90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151            4      9.09%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             44                       # Bytes accessed per row activation
-system.physmem.bytesReadDRAM                    19712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadSys                     19712                       # Total read bytes from the system interface side
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
-system.physmem.bytes_inst_read::cpu.inst        14272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           14272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_read::cpu.inst             19712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                19712                       # Number of bytes read from this memory
-system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
-system.physmem.memoryStateTime::REF            520000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15310750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.num_reads::cpu.inst                308                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
-system.physmem.pageHitRate                      83.12                       # Row buffer hit rate, read and write combined
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.perBankRdBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                   1                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                   3                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  24                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                  21                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                  27                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                  47                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                  68                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                   2                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                 15                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                 14                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                 18                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                 52                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                 15                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                  1                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
-system.physmem.rdQLenPdf::0                       242                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.readBursts                         308                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     308                       # Read request sizes (log2)
-system.physmem.readReqs                           308                       # Number of read requests accepted
-system.physmem.readRowHitRate                   83.12                       # Row buffer hit rate for reads
-system.physmem.readRowHits                        256                       # Number of row buffer hits during reads
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
-system.physmem.totGap                        18580000                       # Total gap between requests
-system.physmem.totMemAccLat                   7425750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totQLat                        1650750                       # Total ticks spent queuing
-system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15410750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15410750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1471750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1471750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16882500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16882500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16882500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54842.526690                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54842.526690                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54509.259259                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54509.259259                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54813.311688                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54813.311688                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54813.311688                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54813.311688                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            48.699994                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 687                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.082353                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst    48.699994                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.011890                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011890                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              1667                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1667                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst          436                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             436                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst          251                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst           687                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              687                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst          687                       # number of overall hits
+system.cpu.dcache.overall_hits::total             687                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst           61                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst           43                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst          104                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
+system.cpu.dcache.overall_misses::total           104                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4631500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4631500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3005500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3005500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst      7637000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7637000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst      7637000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7637000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst          497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          497                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst          791                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          791                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst          791                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          791                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.122736                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.122736                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.146259                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst     0.131479                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.131479                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst     0.131479                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.131479                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75926.229508                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75926.229508                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69895.348837                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69895.348837                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73432.692308                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73432.692308                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73432.692308                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73432.692308                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           16                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           58                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4297000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4297000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      1830750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1830750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6127750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6127750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6127750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6127750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.116700                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.116700                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.107459                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.107459                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.107459                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74086.206897                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74086.206897                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67805.555556                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67805.555556                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72091.176471                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72091.176471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72091.176471                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72091.176471                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------