Clear last error message

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 0276618b4fb6917a5408694c6263820d298ea22a..632dc51fde637c7c2ee84c4d44ea6774ad489da0 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2354,8 +2354,10 @@ struct VerificPass : public Pass {
                        while (argidx < GetSize(args))
                                file_names.Insert(args[argidx++].c_str());
 
-                       if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
+                       if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+                                       verific_error_msg.clear();
                                        log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+                       }
 
                        verific_import_pending = true;
                        goto check_error;