Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v

diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
index 0097b1c9841746fe064a4cc73281b730eb50ecda..2e944895073622e9d1d7882e9067253ff2a58829 100644 (file)
--- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
+++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
@@ -4,11 +4,13 @@ reg req_0 , req_1 ,  req_2 , req_3;
 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
 
 initial begin
+  // $dumpfile("testbench.vcd");
+  // $dumpvars(0, testbench);
   $display("Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
   $monitor("%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
     $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
   clock = 0;
-  reset = 0;
+  reset = 1;
   req_0 = 0;
   req_1 = 0;
   req_2 = 0;