system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'
-Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simout
-Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simerr
+Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 31 2017 18:33:59
-gem5 started May 31 2017 18:34:12
-gem5 executing on boldrock, pid 15707
-command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing
+gem5 compiled Jul 13 2017 17:37:52
+gem5 started Jul 13 2017 18:03:36
+gem5 executing on boldrock, pid 21568
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 41515000 because exiting with last active thread context
+Exiting @ tick 37069000 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042
-sim_ticks 41515000
-final_tick 41515000
+sim_seconds 0.000037
+sim_ticks 37069000
+final_tick 37069000
sim_freq 1000000000000
-host_inst_rate 25426
-host_op_rate 25461
-host_tick_rate 189862237
-host_mem_usage 277956
-host_seconds 0.22
-sim_insts 5559
-sim_ops 5567
+host_inst_rate 9833
+host_op_rate 9849
+host_tick_rate 65547568
+host_mem_usage 261772
+host_seconds 0.57
+sim_insts 5561
+sim_ops 5570
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 41515000
-system.physmem.bytes_read::cpu.inst 25024
-system.physmem.bytes_read::cpu.data 9536
-system.physmem.bytes_read::total 34560
-system.physmem.bytes_inst_read::cpu.inst 25024
-system.physmem.bytes_inst_read::total 25024
-system.physmem.num_reads::cpu.inst 391
-system.physmem.num_reads::cpu.data 149
-system.physmem.num_reads::total 540
-system.physmem.bw_read::cpu.inst 602770083
-system.physmem.bw_read::cpu.data 229700108
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-system.physmem.bw_inst_read::cpu.inst 602770083
-system.physmem.bw_inst_read::total 602770083
-system.physmem.bw_total::cpu.inst 602770083
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-system.physmem.bw_total::total 832470191
-system.physmem.readReqs 540
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+system.physmem.bw_total::cpu.inst 562842267
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system.physmem.writeReqs 0
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system.physmem.writeBursts 0
-system.physmem.bytesReadDRAM 34560
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system.physmem.bytesReadWrQ 0
system.physmem.bytesWritten 0
-system.physmem.bytesReadSys 34560
+system.physmem.bytesReadSys 30208
system.physmem.bytesWrittenSys 0
system.physmem.servicedByWrQ 0
system.physmem.mergedWrBursts 0
system.physmem.neitherReadNorWriteReqs 0
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system.physmem.perBankWrBursts::0 0
system.physmem.perBankWrBursts::1 0
system.physmem.perBankWrBursts::2 0
system.physmem.perBankWrBursts::15 0
system.physmem.numRdRetry 0
system.physmem.numWrRetry 0
-system.physmem.totGap 41434000
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system.physmem.readPktSize::0 0
system.physmem.readPktSize::1 0
system.physmem.readPktSize::2 0
system.physmem.readPktSize::3 0
system.physmem.readPktSize::4 0
system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 540
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system.physmem.writePktSize::0 0
system.physmem.writePktSize::1 0
system.physmem.writePktSize::2 0
system.physmem.writePktSize::4 0
system.physmem.writePktSize::5 0
system.physmem.writePktSize::6 0
-system.physmem.rdQLenPdf::0 454
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-system.physmem.rdQLenPdf::2 9
+system.physmem.rdQLenPdf::0 391
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system.physmem.rdQLenPdf::3 0
system.physmem.rdQLenPdf::4 0
system.physmem.rdQLenPdf::5 0
system.physmem.wrQLenPdf::61 0
system.physmem.wrQLenPdf::62 0
system.physmem.wrQLenPdf::63 0
-system.physmem.bytesPerActivate::samples 93
-system.physmem.bytesPerActivate::mean 353.720430
-system.physmem.bytesPerActivate::gmean 232.715538
-system.physmem.bytesPerActivate::stdev 313.050293
-system.physmem.bytesPerActivate::0-127 22 23.66% 23.66%
-system.physmem.bytesPerActivate::128-255 24 25.81% 49.46%
-system.physmem.bytesPerActivate::256-383 13 13.98% 63.44%
-system.physmem.bytesPerActivate::384-511 8 8.60% 72.04%
-system.physmem.bytesPerActivate::512-639 8 8.60% 80.65%
-system.physmem.bytesPerActivate::640-767 4 4.30% 84.95%
-system.physmem.bytesPerActivate::768-895 3 3.23% 88.17%
-system.physmem.bytesPerActivate::896-1023 2 2.15% 90.32%
-system.physmem.bytesPerActivate::1024-1151 9 9.68% 100.00%
-system.physmem.bytesPerActivate::total 93
-system.physmem.totQLat 6561250
-system.physmem.totMemAccLat 16686250
-system.physmem.totBusLat 2700000
-system.physmem.avgQLat 12150.46
+system.physmem.bytesPerActivate::samples 88
+system.physmem.bytesPerActivate::mean 316.363636
+system.physmem.bytesPerActivate::gmean 211.085787
+system.physmem.bytesPerActivate::stdev 287.751896
+system.physmem.bytesPerActivate::0-127 24 27.27% 27.27%
+system.physmem.bytesPerActivate::128-255 19 21.59% 48.86%
+system.physmem.bytesPerActivate::256-383 18 20.45% 69.32%
+system.physmem.bytesPerActivate::384-511 8 9.09% 78.41%
+system.physmem.bytesPerActivate::512-639 5 5.68% 84.09%
+system.physmem.bytesPerActivate::640-767 4 4.55% 88.64%
+system.physmem.bytesPerActivate::768-895 2 2.27% 90.91%
+system.physmem.bytesPerActivate::896-1023 2 2.27% 93.18%
+system.physmem.bytesPerActivate::1024-1151 6 6.82% 100.00%
+system.physmem.bytesPerActivate::total 88
+system.physmem.totQLat 6564750
+system.physmem.totMemAccLat 15414750
+system.physmem.totBusLat 2360000
+system.physmem.avgQLat 13908.37
system.physmem.avgBusLat 5000.00
-system.physmem.avgMemAccLat 30900.46
-system.physmem.avgRdBW 832.47
+system.physmem.avgMemAccLat 32658.37
+system.physmem.avgRdBW 814.91
system.physmem.avgWrBW 0.00
-system.physmem.avgRdBWSys 832.47
+system.physmem.avgRdBWSys 814.91
system.physmem.avgWrBWSys 0.00
system.physmem.peakBW 12800.00
-system.physmem.busUtil 6.50
-system.physmem.busUtilRead 6.50
+system.physmem.busUtil 6.37
+system.physmem.busUtilRead 6.37
system.physmem.busUtilWrite 0.00
-system.physmem.avgRdQLen 1.17
+system.physmem.avgRdQLen 1.21
system.physmem.avgWrQLen 0.00
-system.physmem.readRowHits 441
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system.physmem.writeRowHits 0
-system.physmem.readRowHitRate 81.67
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system.physmem.writeRowHitRate nan
-system.physmem.avgGap 76729.63
-system.physmem.pageHitRate 81.67
-system.physmem_0.actEnergy 506940
-system.physmem_0.preEnergy 254265
+system.physmem.avgGap 78362.29
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system.physmem_0.readEnergy 2663220
system.physmem_0.writeEnergy 0
-system.physmem_0.refreshEnergy 3073200.000000
-system.physmem_0.actBackEnergy 5192700
-system.physmem_0.preBackEnergy 69600
-system.physmem_0.actPowerDownEnergy 13337430
-system.physmem_0.prePowerDownEnergy 267840
+system.physmem_0.refreshEnergy 2458560.000000
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system.physmem_0.selfRefreshEnergy 0
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-system.physmem_0.averagePower 610.988679
-system.physmem_0.totalIdleTime 29614500
-system.physmem_0.memoryStateTime::IDLE 42000
-system.physmem_0.memoryStateTime::REF 1300000
+system.physmem_0.totalEnergy 22852560
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system.physmem_0.memoryStateTime::SREF 0
-system.physmem_0.memoryStateTime::PRE_PDN 697500
-system.physmem_0.memoryStateTime::ACT 10229750
-system.physmem_0.memoryStateTime::ACT_PDN 29245750
-system.physmem_1.actEnergy 199920
-system.physmem_1.preEnergy 98670
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+system.physmem_0.memoryStateTime::PRE_PDN 3750
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+system.physmem_1.actEnergy 128520
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system.physmem_1.writeEnergy 0
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system.physmem_1.selfRefreshEnergy 0
-system.physmem_1.totalEnergy 23245800
-system.physmem_1.averagePower 559.937372
-system.physmem_1.totalIdleTime 34511250
-system.physmem_1.memoryStateTime::IDLE 951000
-system.physmem_1.memoryStateTime::REF 1300000
+system.physmem_1.totalEnergy 20065260
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system.physmem_1.memoryStateTime::SREF 0
-system.physmem_1.memoryStateTime::PRE_PDN 2357000
-system.physmem_1.memoryStateTime::ACT 4708500
-system.physmem_1.memoryStateTime::ACT_PDN 32198500
-system.pwrStateResidencyTicks::UNDEFINED 41515000
-system.cpu.branchPred.lookups 2636
-system.cpu.branchPred.condPredicted 1784
-system.cpu.branchPred.condIncorrect 465
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-system.cpu.branchPred.BTBHits 368
+system.physmem_1.memoryStateTime::PRE_PDN 1867000
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+system.physmem_1.memoryStateTime::ACT_PDN 30345500
+system.pwrStateResidencyTicks::UNDEFINED 37069000
+system.cpu.branchPred.lookups 2799
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system.cpu.branchPred.BTBCorrect 0
-system.cpu.branchPred.BTBHitPct 15.719778
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system.cpu.branchPred.usedRAS 0
system.cpu.branchPred.RASInCorrect 0
-system.cpu.branchPred.indirectLookups 365
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-system.cpu.branchPred.indirectMisses 344
-system.cpu.branchPredindirectMispredicted 123
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system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
-system.cpu.pwrStateResidencyTicks::ON 41515000
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+system.cpu.numCycles 74138
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5559
-system.cpu.committedOps 5567
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system.cpu.numFetchSuspends 0
-system.cpu.cpi 14.936140
-system.cpu.ipc 0.066952
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system.cpu.op_class_0::No_OpClass 10 0.18% 0.18%
-system.cpu.op_class_0::IntAlu 3353 60.23% 60.41%
-system.cpu.op_class_0::IntMult 2 0.04% 60.45%
-system.cpu.op_class_0::IntDiv 4 0.07% 60.52%
-system.cpu.op_class_0::FloatAdd 0 0.00% 60.52%
-system.cpu.op_class_0::FloatCmp 0 0.00% 60.52%
-system.cpu.op_class_0::FloatCvt 0 0.00% 60.52%
-system.cpu.op_class_0::FloatMult 0 0.00% 60.52%
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class_0::FloatDiv 0 0.00% 60.52%
-system.cpu.op_class_0::FloatMisc 0 0.00% 60.52%
-system.cpu.op_class_0::FloatSqrt 0 0.00% 60.52%
-system.cpu.op_class_0::SimdAdd 0 0.00% 60.52%
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdAlu 0 0.00% 60.52%
-system.cpu.op_class_0::SimdCmp 0 0.00% 60.52%
-system.cpu.op_class_0::SimdCvt 0 0.00% 60.52%
-system.cpu.op_class_0::SimdMisc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdMult 0 0.00% 60.52%
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdShift 0 0.00% 60.52%
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdSqrt 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.52%
-system.cpu.op_class_0::MemRead 1101 19.78% 80.29%
-system.cpu.op_class_0::MemWrite 1085 19.49% 99.78%
+system.cpu.op_class_0::IntAlu 3392 60.90% 61.08%
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system.cpu.op_class_0::FloatMemRead 0 0.00% 99.78%
system.cpu.op_class_0::FloatMemWrite 12 0.22% 100.00%
system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class_0::total 5567
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system.cpu.dcache.tags.replacements 0
-system.cpu.dcache.tags.tagsinuse 91.498917
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system.cpu.dcache.tags.warmup_cycle 0
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+system.membus.trans_dist::ReadExReq 82
+system.membus.trans_dist::ReadExResp 82
+system.membus.trans_dist::ReadSharedReq 390
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 944
+system.membus.pkt_count::total 944
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30208
+system.membus.pkt_size::total 30208
system.membus.snoops 0
system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 540
+system.membus.snoop_fanout::samples 472
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 540 100.00% 100.00%
+system.membus.snoop_fanout::0 472 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 540
-system.membus.reqLayer0.occupancy 612000
-system.membus.reqLayer0.utilization 1.5
-system.membus.respLayer1.occupancy 2866750
-system.membus.respLayer1.utilization 6.9
+system.membus.snoop_fanout::total 472
+system.membus.reqLayer0.occupancy 530000
+system.membus.reqLayer0.utilization 1.4
+system.membus.respLayer1.occupancy 2511750
+system.membus.respLayer1.utilization 6.8
---------- End Simulation Statistics ----------
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
+numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
system=system
tracer=system.cpu.tracer
trapLatency=13
+wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
"switched_out": false,
"smtLSQPolicy": "Partitioned",
"fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
"cacheStorePorts": 200,
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"default_p_state": "UNDEFINED",
"type": "DerivO3CPU",
"wbWidth": 8,
+ "numPhysVecRegs": 256,
"interrupts": [
{
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'
-Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simout
-Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simerr
+Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 31 2017 18:33:59
-gem5 started May 31 2017 18:34:13
-gem5 executing on boldrock, pid 15720
-command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
+gem5 compiled Jul 13 2017 17:37:52
+gem5 started Jul 13 2017 18:03:36
+gem5 executing on boldrock, pid 21571
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 21876000 because exiting with last active thread context
+Exiting @ tick 22347000 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022
-sim_ticks 21876000
-final_tick 21876000
+sim_ticks 22347000
+final_tick 22347000
sim_freq 1000000000000
-host_inst_rate 17054
-host_op_rate 17078
-host_tick_rate 67215440
-host_mem_usage 279228
-host_seconds 0.33
-sim_insts 5550
-sim_ops 5558
+host_inst_rate 10860
+host_op_rate 10877
+host_tick_rate 43710468
+host_mem_usage 261260
+host_seconds 0.51
+sim_insts 5552
+sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 21876000
-system.physmem.bytes_read::cpu.inst 25344
-system.physmem.bytes_read::cpu.data 9856
-system.physmem.bytes_read::total 35200
-system.physmem.bytes_inst_read::cpu.inst 25344
-system.physmem.bytes_inst_read::total 25344
-system.physmem.num_reads::cpu.inst 396
-system.physmem.num_reads::cpu.data 154
-system.physmem.num_reads::total 550
-system.physmem.bw_read::cpu.inst 1158529896
-system.physmem.bw_read::cpu.data 450539404
-system.physmem.bw_read::total 1609069300
-system.physmem.bw_inst_read::cpu.inst 1158529896
-system.physmem.bw_inst_read::total 1158529896
-system.physmem.bw_total::cpu.inst 1158529896
-system.physmem.bw_total::cpu.data 450539404
-system.physmem.bw_total::total 1609069300
-system.physmem.readReqs 550
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22347000
+system.physmem.bytes_read::cpu.inst 19776
+system.physmem.bytes_read::cpu.data 9344
+system.physmem.bytes_read::total 29120
+system.physmem.bytes_inst_read::cpu.inst 19776
+system.physmem.bytes_inst_read::total 19776
+system.physmem.num_reads::cpu.inst 309
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+system.physmem.num_reads::total 455
+system.physmem.bw_read::cpu.inst 884951000
+system.physmem.bw_read::cpu.data 418132188
+system.physmem.bw_read::total 1303083188
+system.physmem.bw_inst_read::cpu.inst 884951000
+system.physmem.bw_inst_read::total 884951000
+system.physmem.bw_total::cpu.inst 884951000
+system.physmem.bw_total::cpu.data 418132188
+system.physmem.bw_total::total 1303083188
+system.physmem.readReqs 455
system.physmem.writeReqs 0
-system.physmem.readBursts 550
+system.physmem.readBursts 455
system.physmem.writeBursts 0
-system.physmem.bytesReadDRAM 35200
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system.physmem.bytesReadWrQ 0
system.physmem.bytesWritten 0
-system.physmem.bytesReadSys 35200
+system.physmem.bytesReadSys 29120
system.physmem.bytesWrittenSys 0
system.physmem.servicedByWrQ 0
system.physmem.mergedWrBursts 0
system.physmem.neitherReadNorWriteReqs 0
-system.physmem.perBankRdBursts::0 59
-system.physmem.perBankRdBursts::1 84
-system.physmem.perBankRdBursts::2 53
-system.physmem.perBankRdBursts::3 46
-system.physmem.perBankRdBursts::4 34
-system.physmem.perBankRdBursts::5 35
-system.physmem.perBankRdBursts::6 43
-system.physmem.perBankRdBursts::7 24
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-system.physmem.perBankRdBursts::10 23
-system.physmem.perBankRdBursts::11 18
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-system.physmem.perBankRdBursts::13 5
-system.physmem.perBankRdBursts::14 6
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+system.physmem.perBankRdBursts::0 32
+system.physmem.perBankRdBursts::1 0
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+system.physmem.perBankRdBursts::10 0
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+system.physmem.perBankRdBursts::12 2
+system.physmem.perBankRdBursts::13 2
+system.physmem.perBankRdBursts::14 1
+system.physmem.perBankRdBursts::15 0
system.physmem.perBankWrBursts::0 0
system.physmem.perBankWrBursts::1 0
system.physmem.perBankWrBursts::2 0
system.physmem.perBankWrBursts::15 0
system.physmem.numRdRetry 0
system.physmem.numWrRetry 0
-system.physmem.totGap 21770000
+system.physmem.totGap 22262000
system.physmem.readPktSize::0 0
system.physmem.readPktSize::1 0
system.physmem.readPktSize::2 0
system.physmem.readPktSize::3 0
system.physmem.readPktSize::4 0
system.physmem.readPktSize::5 0
-system.physmem.readPktSize::6 550
+system.physmem.readPktSize::6 455
system.physmem.writePktSize::0 0
system.physmem.writePktSize::1 0
system.physmem.writePktSize::2 0
system.physmem.writePktSize::4 0
system.physmem.writePktSize::5 0
system.physmem.writePktSize::6 0
-system.physmem.rdQLenPdf::0 249
-system.physmem.rdQLenPdf::1 182
-system.physmem.rdQLenPdf::2 70
-system.physmem.rdQLenPdf::3 35
-system.physmem.rdQLenPdf::4 11
+system.physmem.rdQLenPdf::0 236
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+system.physmem.rdQLenPdf::4 6
system.physmem.rdQLenPdf::5 3
system.physmem.rdQLenPdf::6 0
system.physmem.rdQLenPdf::7 0
system.physmem.wrQLenPdf::61 0
system.physmem.wrQLenPdf::62 0
system.physmem.wrQLenPdf::63 0
-system.physmem.bytesPerActivate::samples 94
-system.physmem.bytesPerActivate::mean 345.191489
-system.physmem.bytesPerActivate::gmean 213.340807
-system.physmem.bytesPerActivate::stdev 332.118818
-system.physmem.bytesPerActivate::0-127 29 30.85% 30.85%
-system.physmem.bytesPerActivate::128-255 21 22.34% 53.19%
-system.physmem.bytesPerActivate::256-383 12 12.77% 65.96%
-system.physmem.bytesPerActivate::384-511 7 7.45% 73.40%
-system.physmem.bytesPerActivate::512-639 6 6.38% 79.79%
-system.physmem.bytesPerActivate::640-767 4 4.26% 84.04%
-system.physmem.bytesPerActivate::768-895 2 2.13% 86.17%
-system.physmem.bytesPerActivate::1024-1151 13 13.83% 100.00%
-system.physmem.bytesPerActivate::total 94
-system.physmem.totQLat 7873000
-system.physmem.totMemAccLat 18185500
-system.physmem.totBusLat 2750000
-system.physmem.avgQLat 14314.55
+system.physmem.bytesPerActivate::samples 100
+system.physmem.bytesPerActivate::mean 271.360000
+system.physmem.bytesPerActivate::gmean 169.923942
+system.physmem.bytesPerActivate::stdev 289.967867
+system.physmem.bytesPerActivate::0-127 35 35.00% 35.00%
+system.physmem.bytesPerActivate::128-255 30 30.00% 65.00%
+system.physmem.bytesPerActivate::256-383 11 11.00% 76.00%
+system.physmem.bytesPerActivate::384-511 6 6.00% 82.00%
+system.physmem.bytesPerActivate::512-639 4 4.00% 86.00%
+system.physmem.bytesPerActivate::640-767 3 3.00% 89.00%
+system.physmem.bytesPerActivate::768-895 2 2.00% 91.00%
+system.physmem.bytesPerActivate::896-1023 2 2.00% 93.00%
+system.physmem.bytesPerActivate::1024-1151 7 7.00% 100.00%
+system.physmem.bytesPerActivate::total 100
+system.physmem.totQLat 7985750
+system.physmem.totMemAccLat 16517000
+system.physmem.totBusLat 2275000
+system.physmem.avgQLat 17551.10
system.physmem.avgBusLat 5000.00
-system.physmem.avgMemAccLat 33064.55
-system.physmem.avgRdBW 1609.07
+system.physmem.avgMemAccLat 36301.10
+system.physmem.avgRdBW 1303.08
system.physmem.avgWrBW 0.00
-system.physmem.avgRdBWSys 1609.07
+system.physmem.avgRdBWSys 1303.08
system.physmem.avgWrBWSys 0.00
system.physmem.peakBW 12800.00
-system.physmem.busUtil 12.57
-system.physmem.busUtilRead 12.57
+system.physmem.busUtil 10.18
+system.physmem.busUtilRead 10.18
system.physmem.busUtilWrite 0.00
-system.physmem.avgRdQLen 2.14
+system.physmem.avgRdQLen 1.85
system.physmem.avgWrQLen 0.00
-system.physmem.readRowHits 445
+system.physmem.readRowHits 345
system.physmem.writeRowHits 0
-system.physmem.readRowHitRate 80.91
+system.physmem.readRowHitRate 75.82
system.physmem.writeRowHitRate nan
-system.physmem.avgGap 39581.82
-system.physmem.pageHitRate 80.91
-system.physmem_0.actEnergy 564060
-system.physmem_0.preEnergy 273240
-system.physmem_0.readEnergy 2698920
+system.physmem.avgGap 48927.47
+system.physmem.pageHitRate 75.82
+system.physmem_0.actEnergy 628320
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+system.physmem_0.readEnergy 2584680
system.physmem_0.writeEnergy 0
system.physmem_0.refreshEnergy 1229280.000000
-system.physmem_0.actBackEnergy 3964920
-system.physmem_0.preBackEnergy 25920
-system.physmem_0.actPowerDownEnergy 5979870
-system.physmem_0.prePowerDownEnergy 0
+system.physmem_0.actBackEnergy 4082340
+system.physmem_0.preBackEnergy 28320
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system.physmem_0.selfRefreshEnergy 0
-system.physmem_0.totalEnergy 14736210
-system.physmem_0.averagePower 673.616822
-system.physmem_0.totalIdleTime 13059500
-system.physmem_0.memoryStateTime::IDLE 11500
+system.physmem_0.totalEnergy 14934735
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+system.physmem_0.totalIdleTime 13169250
+system.physmem_0.memoryStateTime::IDLE 17500
system.physmem_0.memoryStateTime::REF 520000
system.physmem_0.memoryStateTime::SREF 0
-system.physmem_0.memoryStateTime::PRE_PDN 0
-system.physmem_0.memoryStateTime::ACT 8222000
-system.physmem_0.memoryStateTime::ACT_PDN 13122500
-system.physmem_1.actEnergy 185640
-system.physmem_1.preEnergy 83490
-system.physmem_1.readEnergy 1228080
+system.physmem_0.memoryStateTime::PRE_PDN 1250
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+system.physmem_0.memoryStateTime::ACT_PDN 13310000
+system.physmem_1.actEnergy 157080
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system.physmem_1.writeEnergy 0
system.physmem_1.refreshEnergy 1229280.000000
-system.physmem_1.actBackEnergy 2123820
-system.physmem_1.preBackEnergy 198720
-system.physmem_1.actPowerDownEnergy 7360410
-system.physmem_1.prePowerDownEnergy 215040
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system.physmem_1.selfRefreshEnergy 0
-system.physmem_1.totalEnergy 12624480
-system.physmem_1.averagePower 577.086109
-system.physmem_1.totalIdleTime 16628250
-system.physmem_1.memoryStateTime::IDLE 448500
+system.physmem_1.totalEnergy 12180825
+system.physmem_1.averagePower 545.064325
+system.physmem_1.totalIdleTime 18795500
+system.physmem_1.memoryStateTime::IDLE 472250
system.physmem_1.memoryStateTime::REF 520000
system.physmem_1.memoryStateTime::SREF 0
-system.physmem_1.memoryStateTime::PRE_PDN 559250
-system.physmem_1.memoryStateTime::ACT 4203750
-system.physmem_1.memoryStateTime::ACT_PDN 16144500
-system.pwrStateResidencyTicks::UNDEFINED 21876000
-system.cpu.branchPred.lookups 3602
-system.cpu.branchPred.condPredicted 2403
-system.cpu.branchPred.condIncorrect 615
-system.cpu.branchPred.BTBLookups 3064
-system.cpu.branchPred.BTBHits 820
+system.physmem_1.memoryStateTime::PRE_PDN 1293000
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+system.pwrStateResidencyTicks::UNDEFINED 22347000
+system.cpu.branchPred.lookups 2633
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system.cpu.branchPred.BTBCorrect 0
-system.cpu.branchPred.BTBHitPct 26.762402
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system.cpu.branchPred.usedRAS 0
system.cpu.branchPred.RASInCorrect 0
-system.cpu.branchPred.indirectLookups 552
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+system.cpu.branchPredindirectMispredicted 203
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
-system.cpu.pwrStateResidencyTicks::ON 21876000
-system.cpu.numCycles 43754
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system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
-system.cpu.fetch.icacheStallCycles 9412
-system.cpu.fetch.Insts 15646
-system.cpu.fetch.Branches 3602
-system.cpu.fetch.predictedBranches 846
-system.cpu.fetch.Cycles 4159
-system.cpu.fetch.SquashCycles 1256
-system.cpu.fetch.MiscStallCycles 8
-system.cpu.fetch.IcacheWaitRetryStallCycles 99
-system.cpu.fetch.CacheLines 2183
-system.cpu.fetch.IcacheSquashes 446
-system.cpu.fetch.rateDist::samples 14306
-system.cpu.fetch.rateDist::mean 1.096323
-system.cpu.fetch.rateDist::stdev 2.511814
+system.cpu.fetch.icacheStallCycles 7412
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+system.cpu.fetch.Branches 2633
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+system.cpu.fetch.Cycles 8264
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+system.cpu.fetch.MiscStallCycles 3
+system.cpu.fetch.IcacheWaitRetryStallCycles 53
+system.cpu.fetch.CacheLines 1371
+system.cpu.fetch.IcacheSquashes 238
+system.cpu.fetch.rateDist::samples 16449
+system.cpu.fetch.rateDist::mean 0.677062
+system.cpu.fetch.rateDist::stdev 1.083698
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
-system.cpu.fetch.rateDist::0 11573 80.90% 80.90%
-system.cpu.fetch.rateDist::1 217 1.52% 82.41%
-system.cpu.fetch.rateDist::2 240 1.68% 84.09%
-system.cpu.fetch.rateDist::3 172 1.20% 85.29%
-system.cpu.fetch.rateDist::4 322 2.25% 87.54%
-system.cpu.fetch.rateDist::5 235 1.64% 89.19%
-system.cpu.fetch.rateDist::6 104 0.73% 89.91%
-system.cpu.fetch.rateDist::7 160 1.12% 91.03%
-system.cpu.fetch.rateDist::8 1283 8.97% 100.00%
+system.cpu.fetch.rateDist::0 9314 56.62% 56.62%
+system.cpu.fetch.rateDist::1 5053 30.72% 87.34%
+system.cpu.fetch.rateDist::2 1133 6.89% 94.23%
+system.cpu.fetch.rateDist::3 492 2.99% 97.22%
+system.cpu.fetch.rateDist::4 212 1.29% 98.51%
+system.cpu.fetch.rateDist::5 105 0.64% 99.15%
+system.cpu.fetch.rateDist::6 66 0.40% 99.55%
+system.cpu.fetch.rateDist::7 19 0.12% 99.67%
+system.cpu.fetch.rateDist::8 55 0.33% 100.00%
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
system.cpu.fetch.rateDist::min_value 0
system.cpu.fetch.rateDist::max_value 8
-system.cpu.fetch.rateDist::total 14306
-system.cpu.fetch.branchRate 0.082324
-system.cpu.fetch.rate 0.357590
-system.cpu.decode.IdleCycles 7306
-system.cpu.decode.BlockedCycles 4223
-system.cpu.decode.RunCycles 2169
-system.cpu.decode.UnblockCycles 153
-system.cpu.decode.SquashCycles 455
-system.cpu.decode.BranchResolved 898
-system.cpu.decode.BranchMispred 180
-system.cpu.decode.DecodedInsts 12831
-system.cpu.decode.SquashedInsts 509
-system.cpu.rename.SquashCycles 455
-system.cpu.rename.IdleCycles 7513
-system.cpu.rename.BlockCycles 808
-system.cpu.rename.serializeStallCycles 2339
-system.cpu.rename.RunCycles 2094
-system.cpu.rename.UnblockCycles 1097
-system.cpu.rename.RenamedInsts 11937
-system.cpu.rename.IQFullEvents 8
-system.cpu.rename.LQFullEvents 48
-system.cpu.rename.SQFullEvents 1030
-system.cpu.rename.RenamedOperands 8187
-system.cpu.rename.RenameLookups 15598
-system.cpu.rename.int_rename_lookups 15586
+system.cpu.fetch.rateDist::total 16449
+system.cpu.fetch.branchRate 0.058910
+system.cpu.fetch.rate 0.248708
+system.cpu.decode.IdleCycles 6659
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+system.cpu.rename.SquashCycles 536
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+system.cpu.rename.RenamedInsts 9269
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system.cpu.rename.fp_rename_lookups 12
-system.cpu.rename.CommittedMaps 3562
-system.cpu.rename.UndoneMaps 4625
-system.cpu.rename.serializingInsts 43
-system.cpu.rename.tempSerializingInsts 46
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-system.cpu.memDep0.insertedLoads 2300
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-system.cpu.iq.iqInstsAdded 10454
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-system.cpu.iq.iqInstsIssued 9212
-system.cpu.iq.iqSquashedInstsIssued 89
-system.cpu.iq.iqSquashedInstsExamined 4951
-system.cpu.iq.iqSquashedOperandsExamined 2778
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-system.cpu.iq.issued_per_cycle::mean 0.643926
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
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-system.cpu.iq.issued_per_cycle::1 976 6.82% 84.91%
-system.cpu.iq.issued_per_cycle::2 626 4.38% 89.28%
-system.cpu.iq.issued_per_cycle::3 441 3.08% 92.37%
-system.cpu.iq.issued_per_cycle::4 429 3.00% 95.37%
-system.cpu.iq.issued_per_cycle::5 288 2.01% 97.38%
-system.cpu.iq.issued_per_cycle::6 199 1.39% 98.77%
-system.cpu.iq.issued_per_cycle::7 97 0.68% 99.45%
-system.cpu.iq.issued_per_cycle::8 79 0.55% 100.00%
+system.cpu.iq.issued_per_cycle::0 11408 69.35% 69.35%
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system.cpu.iq.issued_per_cycle::min_value 0
system.cpu.iq.issued_per_cycle::max_value 8
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
-system.cpu.iq.fu_full::IntAlu 41 13.58% 13.58%
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-system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.58%
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-system.cpu.iq.fu_full::MemRead 169 55.96% 69.54%
-system.cpu.iq.fu_full::MemWrite 89 29.47% 99.01%
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-system.cpu.iq.FU_type_0::FloatMemWrite 12 0.13% 100.00%
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+system.cpu.iq.FU_type_0::MemRead 1600 20.79% 83.53%
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00%
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00%
-system.cpu.iq.FU_type_0::total 9212
-system.cpu.iq.rate 0.210541
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system.cpu.commit.op_class_0::No_OpClass 1 0.02% 0.02%
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
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system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
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system.cpu.toL2Bus.snoops 0
system.cpu.toL2Bus.snoopTraffic 0
-system.cpu.toL2Bus.snoop_fanout::samples 554
-system.cpu.toL2Bus.snoop_fanout::mean 0.003610
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 552 99.64% 99.64%
-system.cpu.toL2Bus.snoop_fanout::1 2 0.36% 100.00%
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system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::min_value 0
-system.cpu.toL2Bus.snoop_fanout::max_value 1
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-system.cpu.toL2Bus.reqLayer0.occupancy 277000
-system.cpu.toL2Bus.reqLayer0.utilization 1.3
-system.cpu.toL2Bus.respLayer0.occupancy 597000
-system.cpu.toL2Bus.respLayer0.utilization 2.7
-system.cpu.toL2Bus.respLayer1.occupancy 231000
-system.cpu.toL2Bus.respLayer1.utilization 1.1
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+system.cpu.toL2Bus.reqLayer0.occupancy 227500
+system.cpu.toL2Bus.reqLayer0.utilization 1.0
+system.cpu.toL2Bus.respLayer0.occupancy 463500
+system.cpu.toL2Bus.respLayer0.utilization 2.1
+system.cpu.toL2Bus.respLayer1.occupancy 219000
+system.cpu.toL2Bus.respLayer1.utilization 1.0
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system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
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-system.membus.trans_dist::ReadResp 471
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-system.membus.trans_dist::ReadExResp 79
-system.membus.trans_dist::ReadSharedReq 471
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1100
-system.membus.pkt_count::total 1100
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 35200
-system.membus.pkt_size::total 35200
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+system.membus.trans_dist::ReadResp 375
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+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910
+system.membus.pkt_count::total 910
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120
+system.membus.pkt_size::total 29120
system.membus.snoops 0
system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 550
+system.membus.snoop_fanout::samples 455
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 550 100.00% 100.00%
+system.membus.snoop_fanout::0 455 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 550
-system.membus.reqLayer0.occupancy 681000
-system.membus.reqLayer0.utilization 3.1
-system.membus.respLayer1.occupancy 2898500
-system.membus.respLayer1.utilization 13.2
+system.membus.snoop_fanout::total 455
+system.membus.reqLayer0.occupancy 545000
+system.membus.reqLayer0.utilization 2.4
+system.membus.respLayer1.occupancy 2408250
+system.membus.respLayer1.utilization 10.8
---------- End Simulation Statistics ----------
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'
-Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simout
-Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simerr
+Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 31 2017 18:33:59
-gem5 started May 31 2017 18:34:14
-gem5 executing on boldrock, pid 15724
-command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic
+gem5 compiled Jul 13 2017 17:37:52
+gem5 started Jul 13 2017 18:03:36
+gem5 executing on boldrock, pid 21572
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 2783000 because exiting with last active thread context
+Exiting @ tick 3301500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003
-sim_ticks 2783000
-final_tick 2783000
+sim_ticks 3301500
+final_tick 3301500
sim_freq 1000000000000
-host_inst_rate 86590
-host_op_rate 86699
-host_tick_rate 43405073
-host_mem_usage 264628
-host_seconds 0.06
-sim_insts 5550
-sim_ops 5558
+host_inst_rate 10162
+host_op_rate 10178
+host_tick_rate 6042080
+host_mem_usage 248192
+host_seconds 0.55
+sim_insts 5552
+sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2783000
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-system.physmem.bytes_read::cpu.data 7346
-system.physmem.bytes_read::total 29582
-system.physmem.bytes_inst_read::cpu.inst 22236
-system.physmem.bytes_inst_read::total 22236
-system.physmem.bytes_written::cpu.data 8138
-system.physmem.bytes_written::total 8138
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-system.physmem.num_writes::cpu.data 1097
-system.physmem.num_writes::total 1097
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-system.pwrStateResidencyTicks::UNDEFINED 2783000
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+system.pwrStateResidencyTicks::UNDEFINED 3301500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
-system.cpu.pwrStateResidencyTicks::ON 2783000
-system.cpu.numCycles 5567
+system.cpu.pwrStateResidencyTicks::ON 3301500
+system.cpu.numCycles 6604
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5550
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+system.cpu.committedInsts 5552
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system.cpu.num_fp_alu_accesses 12
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system.cpu.num_conditional_control_insts 914
-system.cpu.num_int_insts 5557
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system.cpu.num_fp_insts 12
-system.cpu.num_int_register_reads 7540
-system.cpu.num_int_register_writes 3562
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system.cpu.num_fp_register_reads 12
system.cpu.num_fp_register_writes 0
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system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 5567
+system.cpu.num_busy_cycles 6604
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
-system.cpu.Branches 1205
+system.cpu.Branches 1196
system.cpu.op_class::No_OpClass 10 0.18% 0.18%
-system.cpu.op_class::IntAlu 3353 60.23% 60.41%
-system.cpu.op_class::IntMult 2 0.04% 60.45%
-system.cpu.op_class::IntDiv 4 0.07% 60.52%
-system.cpu.op_class::FloatAdd 0 0.00% 60.52%
-system.cpu.op_class::FloatCmp 0 0.00% 60.52%
-system.cpu.op_class::FloatCvt 0 0.00% 60.52%
-system.cpu.op_class::FloatMult 0 0.00% 60.52%
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class::FloatDiv 0 0.00% 60.52%
-system.cpu.op_class::FloatMisc 0 0.00% 60.52%
-system.cpu.op_class::FloatSqrt 0 0.00% 60.52%
-system.cpu.op_class::SimdAdd 0 0.00% 60.52%
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdAlu 0 0.00% 60.52%
-system.cpu.op_class::SimdCmp 0 0.00% 60.52%
-system.cpu.op_class::SimdCvt 0 0.00% 60.52%
-system.cpu.op_class::SimdMisc 0 0.00% 60.52%
-system.cpu.op_class::SimdMult 0 0.00% 60.52%
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdShift 0 0.00% 60.52%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdSqrt 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52%
-system.cpu.op_class::MemRead 1101 19.78% 80.29%
-system.cpu.op_class::MemWrite 1085 19.49% 99.78%
+system.cpu.op_class::IntAlu 3392 60.90% 61.08%
+system.cpu.op_class::IntMult 2 0.04% 61.11%
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+system.cpu.op_class::SimdAddAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdAlu 0 0.00% 61.18%
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+system.cpu.op_class::SimdCvt 0 0.00% 61.18%
+system.cpu.op_class::SimdMisc 0 0.00% 61.18%
+system.cpu.op_class::SimdMult 0 0.00% 61.18%
+system.cpu.op_class::SimdMultAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdShift 0 0.00% 61.18%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdSqrt 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatMult 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18%
+system.cpu.op_class::MemRead 1082 19.43% 80.61%
+system.cpu.op_class::MemWrite 1068 19.17% 99.78%
system.cpu.op_class::FloatMemRead 0 0.00% 99.78%
system.cpu.op_class::FloatMemWrite 12 0.22% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 5567
+system.cpu.op_class::total 5570
system.membus.snoop_filter.tot_requests 0
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 2783000
-system.membus.trans_dist::ReadReq 6652
-system.membus.trans_dist::ReadResp 6660
-system.membus.trans_dist::WriteReq 1089
-system.membus.trans_dist::WriteResp 1089
+system.membus.pwrStateResidencyTicks::UNDEFINED 3301500
+system.membus.trans_dist::ReadReq 7669
+system.membus.trans_dist::ReadResp 7677
+system.membus.trans_dist::WriteReq 1072
+system.membus.trans_dist::WriteResp 1072
system.membus.trans_dist::LoadLockedReq 8
system.membus.trans_dist::StoreCondReq 8
system.membus.trans_dist::StoreCondResp 8
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11118
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4396
-system.membus.pkt_count::total 15514
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22236
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484
-system.membus.pkt_size::total 37720
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13190
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4324
+system.membus.pkt_count::total 17514
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 26380
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15482
+system.membus.pkt_size::total 41862
system.membus.snoops 0
system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 7757
+system.membus.snoop_fanout::samples 8757
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 7757 100.00% 100.00%
+system.membus.snoop_fanout::0 8757 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 7757
+system.membus.snoop_fanout::total 8757
---------- End Simulation Statistics ----------
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
+addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
-transitions_per_cycle=4
+transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+addr_ranges=0:268435455:5:0:0:0
eventq_index=0
-numa_high_bit=5
-size=268435456
-system=system
-version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
+addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
- "cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
"support_data_reqs": true,
"is_cpu_sequencer": true
},
- "type": "L1Cache_Controller",
+ "cxx_class": "L1Cache_Controller",
"issue_latency": 2,
+ "type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
- "transitions_per_cycle": 4,
+ "transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
- "system": "system",
- "version": 0,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
- "type": "RubyDirectoryMemory",
- "numa_high_bit": 5,
- "size": 268435456
+ "type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
-Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout
-Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr
+Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 31 2017 18:33:59
-gem5 started May 31 2017 18:34:14
-gem5 executing on boldrock, pid 15732
-command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby
+gem5 compiled Jul 13 2017 17:37:52
+gem5 started Jul 13 2017 18:03:36
+gem5 executing on boldrock, pid 21569
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
Hello world!
-Exiting @ tick 99780 because exiting with last active thread context
+Exiting @ tick 96790 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000100
-sim_ticks 99780
-final_tick 99780
+sim_seconds 0.000097
+sim_ticks 96790
+final_tick 96790
sim_freq 1000000000
-host_inst_rate 16142
-host_op_rate 16165
-host_tick_rate 290191
-host_mem_usage 441524
-host_seconds 0.34
-sim_insts 5550
-sim_ops 5558
+host_inst_rate 12250
+host_op_rate 12270
+host_tick_rate 213561
+host_mem_usage 421516
+host_seconds 0.45
+sim_insts 5552
+sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 99780
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94784
-system.mem_ctrls.bytes_read::total 94784
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 94528
-system.mem_ctrls.bytes_written::total 94528
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1481
-system.mem_ctrls.num_reads::total 1481
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 1477
-system.mem_ctrls.num_writes::total 1477
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 949929846
-system.mem_ctrls.bw_read::total 949929846
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 947364201
-system.mem_ctrls.bw_write::total 947364201
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1897294047
-system.mem_ctrls.bw_total::total 1897294047
-system.mem_ctrls.readReqs 1481
-system.mem_ctrls.writeReqs 1477
-system.mem_ctrls.readBursts 1481
-system.mem_ctrls.writeBursts 1477
-system.mem_ctrls.bytesReadDRAM 53056
-system.mem_ctrls.bytesReadWrQ 41728
-system.mem_ctrls.bytesWritten 53760
-system.mem_ctrls.bytesReadSys 94784
-system.mem_ctrls.bytesWrittenSys 94528
-system.mem_ctrls.servicedByWrQ 652
-system.mem_ctrls.mergedWrBursts 618
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 96790
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 89856
+system.mem_ctrls.bytes_read::total 89856
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 89600
+system.mem_ctrls.bytes_written::total 89600
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1404
+system.mem_ctrls.num_reads::total 1404
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 1400
+system.mem_ctrls.num_writes::total 1400
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 928360368
+system.mem_ctrls.bw_read::total 928360368
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 925715466
+system.mem_ctrls.bw_write::total 925715466
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1854075834
+system.mem_ctrls.bw_total::total 1854075834
+system.mem_ctrls.readReqs 1404
+system.mem_ctrls.writeReqs 1400
+system.mem_ctrls.readBursts 1404
+system.mem_ctrls.writeBursts 1400
+system.mem_ctrls.bytesReadDRAM 47808
+system.mem_ctrls.bytesReadWrQ 42048
+system.mem_ctrls.bytesWritten 48000
+system.mem_ctrls.bytesReadSys 89856
+system.mem_ctrls.bytesWrittenSys 89600
+system.mem_ctrls.servicedByWrQ 657
+system.mem_ctrls.mergedWrBursts 628
system.mem_ctrls.neitherReadNorWriteReqs 0
-system.mem_ctrls.perBankRdBursts::0 66
-system.mem_ctrls.perBankRdBursts::1 132
-system.mem_ctrls.perBankRdBursts::2 108
-system.mem_ctrls.perBankRdBursts::3 130
-system.mem_ctrls.perBankRdBursts::4 52
-system.mem_ctrls.perBankRdBursts::5 42
-system.mem_ctrls.perBankRdBursts::6 42
-system.mem_ctrls.perBankRdBursts::7 14
-system.mem_ctrls.perBankRdBursts::8 89
-system.mem_ctrls.perBankRdBursts::9 41
-system.mem_ctrls.perBankRdBursts::10 34
-system.mem_ctrls.perBankRdBursts::11 13
-system.mem_ctrls.perBankRdBursts::12 46
+system.mem_ctrls.perBankRdBursts::0 51
+system.mem_ctrls.perBankRdBursts::1 0
+system.mem_ctrls.perBankRdBursts::2 41
+system.mem_ctrls.perBankRdBursts::3 15
+system.mem_ctrls.perBankRdBursts::4 69
+system.mem_ctrls.perBankRdBursts::5 176
+system.mem_ctrls.perBankRdBursts::6 162
+system.mem_ctrls.perBankRdBursts::7 136
+system.mem_ctrls.perBankRdBursts::8 58
+system.mem_ctrls.perBankRdBursts::9 31
+system.mem_ctrls.perBankRdBursts::10 0
+system.mem_ctrls.perBankRdBursts::11 2
+system.mem_ctrls.perBankRdBursts::12 2
system.mem_ctrls.perBankRdBursts::13 3
-system.mem_ctrls.perBankRdBursts::14 8
-system.mem_ctrls.perBankRdBursts::15 9
-system.mem_ctrls.perBankWrBursts::0 64
-system.mem_ctrls.perBankWrBursts::1 142
-system.mem_ctrls.perBankWrBursts::2 106
-system.mem_ctrls.perBankWrBursts::3 136
-system.mem_ctrls.perBankWrBursts::4 53
-system.mem_ctrls.perBankWrBursts::5 44
-system.mem_ctrls.perBankWrBursts::6 38
-system.mem_ctrls.perBankWrBursts::7 14
-system.mem_ctrls.perBankWrBursts::8 91
-system.mem_ctrls.perBankWrBursts::9 41
-system.mem_ctrls.perBankWrBursts::10 34
-system.mem_ctrls.perBankWrBursts::11 11
-system.mem_ctrls.perBankWrBursts::12 47
+system.mem_ctrls.perBankRdBursts::14 1
+system.mem_ctrls.perBankRdBursts::15 0
+system.mem_ctrls.perBankWrBursts::0 51
+system.mem_ctrls.perBankWrBursts::1 0
+system.mem_ctrls.perBankWrBursts::2 43
+system.mem_ctrls.perBankWrBursts::3 13
+system.mem_ctrls.perBankWrBursts::4 61
+system.mem_ctrls.perBankWrBursts::5 180
+system.mem_ctrls.perBankWrBursts::6 163
+system.mem_ctrls.perBankWrBursts::7 143
+system.mem_ctrls.perBankWrBursts::8 57
+system.mem_ctrls.perBankWrBursts::9 31
+system.mem_ctrls.perBankWrBursts::10 0
+system.mem_ctrls.perBankWrBursts::11 2
+system.mem_ctrls.perBankWrBursts::12 2
system.mem_ctrls.perBankWrBursts::13 3
-system.mem_ctrls.perBankWrBursts::14 7
-system.mem_ctrls.perBankWrBursts::15 9
+system.mem_ctrls.perBankWrBursts::14 1
+system.mem_ctrls.perBankWrBursts::15 0
system.mem_ctrls.numRdRetry 0
system.mem_ctrls.numWrRetry 0
-system.mem_ctrls.totGap 99716
+system.mem_ctrls.totGap 96722
system.mem_ctrls.readPktSize::0 0
system.mem_ctrls.readPktSize::1 0
system.mem_ctrls.readPktSize::2 0
system.mem_ctrls.readPktSize::3 0
system.mem_ctrls.readPktSize::4 0
system.mem_ctrls.readPktSize::5 0
-system.mem_ctrls.readPktSize::6 1481
+system.mem_ctrls.readPktSize::6 1404
system.mem_ctrls.writePktSize::0 0
system.mem_ctrls.writePktSize::1 0
system.mem_ctrls.writePktSize::2 0
system.mem_ctrls.writePktSize::3 0
system.mem_ctrls.writePktSize::4 0
system.mem_ctrls.writePktSize::5 0
-system.mem_ctrls.writePktSize::6 1477
-system.mem_ctrls.rdQLenPdf::0 829
+system.mem_ctrls.writePktSize::6 1400
+system.mem_ctrls.rdQLenPdf::0 747
system.mem_ctrls.rdQLenPdf::1 0
system.mem_ctrls.rdQLenPdf::2 0
system.mem_ctrls.rdQLenPdf::3 0
system.mem_ctrls.wrQLenPdf::12 1
system.mem_ctrls.wrQLenPdf::13 1
system.mem_ctrls.wrQLenPdf::14 1
-system.mem_ctrls.wrQLenPdf::15 9
-system.mem_ctrls.wrQLenPdf::16 9
-system.mem_ctrls.wrQLenPdf::17 45
-system.mem_ctrls.wrQLenPdf::18 55
-system.mem_ctrls.wrQLenPdf::19 53
-system.mem_ctrls.wrQLenPdf::20 54
-system.mem_ctrls.wrQLenPdf::21 57
-system.mem_ctrls.wrQLenPdf::22 51
-system.mem_ctrls.wrQLenPdf::23 51
-system.mem_ctrls.wrQLenPdf::24 51
-system.mem_ctrls.wrQLenPdf::25 51
-system.mem_ctrls.wrQLenPdf::26 51
-system.mem_ctrls.wrQLenPdf::27 51
-system.mem_ctrls.wrQLenPdf::28 51
-system.mem_ctrls.wrQLenPdf::29 51
-system.mem_ctrls.wrQLenPdf::30 51
-system.mem_ctrls.wrQLenPdf::31 51
-system.mem_ctrls.wrQLenPdf::32 51
-system.mem_ctrls.wrQLenPdf::33 1
+system.mem_ctrls.wrQLenPdf::15 6
+system.mem_ctrls.wrQLenPdf::16 8
+system.mem_ctrls.wrQLenPdf::17 42
+system.mem_ctrls.wrQLenPdf::18 48
+system.mem_ctrls.wrQLenPdf::19 48
+system.mem_ctrls.wrQLenPdf::20 48
+system.mem_ctrls.wrQLenPdf::21 50
+system.mem_ctrls.wrQLenPdf::22 47
+system.mem_ctrls.wrQLenPdf::23 46
+system.mem_ctrls.wrQLenPdf::24 46
+system.mem_ctrls.wrQLenPdf::25 46
+system.mem_ctrls.wrQLenPdf::26 46
+system.mem_ctrls.wrQLenPdf::27 46
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+system.mem_ctrls.wrQLenPdf::29 46
+system.mem_ctrls.wrQLenPdf::30 46
+system.mem_ctrls.wrQLenPdf::31 46
+system.mem_ctrls.wrQLenPdf::32 46
+system.mem_ctrls.wrQLenPdf::33 0
system.mem_ctrls.wrQLenPdf::34 0
system.mem_ctrls.wrQLenPdf::35 0
system.mem_ctrls.wrQLenPdf::36 0
system.mem_ctrls.wrQLenPdf::61 0
system.mem_ctrls.wrQLenPdf::62 0
system.mem_ctrls.wrQLenPdf::63 0
-system.mem_ctrls.bytesPerActivate::samples 272
-system.mem_ctrls.bytesPerActivate::mean 387.764706
-system.mem_ctrls.bytesPerActivate::gmean 254.750753
-system.mem_ctrls.bytesPerActivate::stdev 333.100037
-system.mem_ctrls.bytesPerActivate::0-127 58 21.32% 21.32%
-system.mem_ctrls.bytesPerActivate::128-255 65 23.90% 45.22%
-system.mem_ctrls.bytesPerActivate::256-383 37 13.60% 58.82%
-system.mem_ctrls.bytesPerActivate::384-511 29 10.66% 69.49%
-system.mem_ctrls.bytesPerActivate::512-639 16 5.88% 75.37%
-system.mem_ctrls.bytesPerActivate::640-767 14 5.15% 80.51%
-system.mem_ctrls.bytesPerActivate::768-895 8 2.94% 83.46%
-system.mem_ctrls.bytesPerActivate::896-1023 9 3.31% 86.76%
-system.mem_ctrls.bytesPerActivate::1024-1151 36 13.24% 100.00%
-system.mem_ctrls.bytesPerActivate::total 272
-system.mem_ctrls.rdPerTurnAround::samples 51
-system.mem_ctrls.rdPerTurnAround::mean 16.196078
-system.mem_ctrls.rdPerTurnAround::gmean 16.040148
-system.mem_ctrls.rdPerTurnAround::stdev 2.785818
-system.mem_ctrls.rdPerTurnAround::14-15 22 43.14% 43.14%
-system.mem_ctrls.rdPerTurnAround::16-17 24 47.06% 90.20%
-system.mem_ctrls.rdPerTurnAround::18-19 3 5.88% 96.08%
-system.mem_ctrls.rdPerTurnAround::20-21 1 1.96% 98.04%
-system.mem_ctrls.rdPerTurnAround::34-35 1 1.96% 100.00%
-system.mem_ctrls.rdPerTurnAround::total 51
-system.mem_ctrls.wrPerTurnAround::samples 51
-system.mem_ctrls.wrPerTurnAround::mean 16.470588
-system.mem_ctrls.wrPerTurnAround::gmean 16.444515
-system.mem_ctrls.wrPerTurnAround::stdev 0.966498
-system.mem_ctrls.wrPerTurnAround::16 40 78.43% 78.43%
-system.mem_ctrls.wrPerTurnAround::17 2 3.92% 82.35%
-system.mem_ctrls.wrPerTurnAround::18 5 9.80% 92.16%
-system.mem_ctrls.wrPerTurnAround::19 4 7.84% 100.00%
-system.mem_ctrls.wrPerTurnAround::total 51
-system.mem_ctrls.totQLat 14330
-system.mem_ctrls.totMemAccLat 30081
-system.mem_ctrls.totBusLat 4145
-system.mem_ctrls.avgQLat 17.29
+system.mem_ctrls.bytesPerActivate::samples 268
+system.mem_ctrls.bytesPerActivate::mean 349.134328
+system.mem_ctrls.bytesPerActivate::gmean 236.095994
+system.mem_ctrls.bytesPerActivate::stdev 304.006943
+system.mem_ctrls.bytesPerActivate::0-127 53 19.78% 19.78%
+system.mem_ctrls.bytesPerActivate::128-255 78 29.10% 48.88%
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system.ruby.clk_domain.clock 1
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system.ruby.delayHist::bucket_size 1
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system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
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system.ruby.latency_hist_seqr::bucket_size 64
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system.ruby.hit_latency_hist_seqr::bucket_size 1
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system.ruby.delayVCHist.vnet_2::max_bucket 9
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+system.ruby.Directory_Controller.Memory_Ack 1400 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 1404 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 1400 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 1404 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 1400 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1074 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6595 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 1088 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1404 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 1400 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 1400 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 532 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 568 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 304 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 542 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 6027 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 784 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 1400 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 1400 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1100 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 304 0.00% 0.00%
---------- End Simulation Statistics ----------
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
info: Entering event queue @ 0. Starting simulation...
warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello'
-Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simout
-Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simerr
+Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 31 2017 18:33:59
-gem5 started May 31 2017 18:34:14
-gem5 executing on boldrock, pid 15728
-command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
+gem5 compiled Jul 13 2017 17:37:52
+gem5 started Jul 13 2017 18:03:36
+gem5 executing on boldrock, pid 21570
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Hello world!
-Exiting @ tick 34045500 because exiting with last active thread context
+Exiting @ tick 31821500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000034
-sim_ticks 34045500
-final_tick 34045500
+sim_seconds 0.000032
+sim_ticks 31821500
+final_tick 31821500
sim_freq 1000000000000
-host_inst_rate 83295
-host_op_rate 83403
-host_tick_rate 510821707
-host_mem_usage 275396
-host_seconds 0.07
-sim_insts 5550
-sim_ops 5558
+host_inst_rate 11620
+host_op_rate 11638
+host_tick_rate 66593131
+host_mem_usage 258956
+host_seconds 0.48
+sim_insts 5552
+sim_ops 5561
system.voltage_domain.voltage 1
system.clk_domain.clock 1000
-system.physmem.pwrStateResidencyTicks::UNDEFINED 34045500
-system.physmem.bytes_read::cpu.inst 17856
-system.physmem.bytes_read::cpu.data 9280
-system.physmem.bytes_read::total 27136
-system.physmem.bytes_inst_read::cpu.inst 17856
-system.physmem.bytes_inst_read::total 17856
-system.physmem.num_reads::cpu.inst 279
-system.physmem.num_reads::cpu.data 145
-system.physmem.num_reads::total 424
-system.physmem.bw_read::cpu.inst 524474600
-system.physmem.bw_read::cpu.data 272576405
-system.physmem.bw_read::total 797051005
-system.physmem.bw_inst_read::cpu.inst 524474600
-system.physmem.bw_inst_read::total 524474600
-system.physmem.bw_total::cpu.inst 524474600
-system.physmem.bw_total::cpu.data 272576405
-system.physmem.bw_total::total 797051005
-system.pwrStateResidencyTicks::UNDEFINED 34045500
+system.physmem.pwrStateResidencyTicks::UNDEFINED 31821500
+system.physmem.bytes_read::cpu.inst 14592
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+system.physmem.bytes_read::total 23808
+system.physmem.bytes_inst_read::cpu.inst 14592
+system.physmem.bytes_inst_read::total 14592
+system.physmem.num_reads::cpu.inst 228
+system.physmem.num_reads::cpu.data 144
+system.physmem.num_reads::total 372
+system.physmem.bw_read::cpu.inst 458557893
+system.physmem.bw_read::cpu.data 289615512
+system.physmem.bw_read::total 748173405
+system.physmem.bw_inst_read::cpu.inst 458557893
+system.physmem.bw_inst_read::total 458557893
+system.physmem.bw_total::cpu.inst 458557893
+system.physmem.bw_total::cpu.data 289615512
+system.physmem.bw_total::total 748173405
+system.pwrStateResidencyTicks::UNDEFINED 31821500
system.cpu_clk_domain.clock 500
system.cpu.dtb.read_hits 0
system.cpu.dtb.read_misses 0
system.cpu.itb.misses 0
system.cpu.itb.accesses 0
system.cpu.workload.numSyscalls 9
-system.cpu.pwrStateResidencyTicks::ON 34045500
-system.cpu.numCycles 68091
+system.cpu.pwrStateResidencyTicks::ON 31821500
+system.cpu.numCycles 63643
system.cpu.numWorkItemsStarted 0
system.cpu.numWorkItemsCompleted 0
-system.cpu.committedInsts 5550
-system.cpu.committedOps 5558
-system.cpu.num_int_alu_accesses 5557
+system.cpu.committedInsts 5552
+system.cpu.committedOps 5561
+system.cpu.num_int_alu_accesses 5498
system.cpu.num_fp_alu_accesses 12
-system.cpu.num_func_calls 291
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 282
system.cpu.num_conditional_control_insts 914
-system.cpu.num_int_insts 5557
+system.cpu.num_int_insts 5498
system.cpu.num_fp_insts 12
-system.cpu.num_int_register_reads 7540
-system.cpu.num_int_register_writes 3562
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 7038
+system.cpu.num_int_register_writes 3414
system.cpu.num_fp_register_reads 12
system.cpu.num_fp_register_writes 0
-system.cpu.num_mem_refs 2198
-system.cpu.num_load_insts 1101
-system.cpu.num_store_insts 1097
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 2162
+system.cpu.num_load_insts 1082
+system.cpu.num_store_insts 1080
system.cpu.num_idle_cycles 0
-system.cpu.num_busy_cycles 68091
+system.cpu.num_busy_cycles 63643
system.cpu.not_idle_fraction 1
system.cpu.idle_fraction 0
-system.cpu.Branches 1205
+system.cpu.Branches 1196
system.cpu.op_class::No_OpClass 10 0.18% 0.18%
-system.cpu.op_class::IntAlu 3353 60.23% 60.41%
-system.cpu.op_class::IntMult 2 0.04% 60.45%
-system.cpu.op_class::IntDiv 4 0.07% 60.52%
-system.cpu.op_class::FloatAdd 0 0.00% 60.52%
-system.cpu.op_class::FloatCmp 0 0.00% 60.52%
-system.cpu.op_class::FloatCvt 0 0.00% 60.52%
-system.cpu.op_class::FloatMult 0 0.00% 60.52%
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class::FloatDiv 0 0.00% 60.52%
-system.cpu.op_class::FloatMisc 0 0.00% 60.52%
-system.cpu.op_class::FloatSqrt 0 0.00% 60.52%
-system.cpu.op_class::SimdAdd 0 0.00% 60.52%
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdAlu 0 0.00% 60.52%
-system.cpu.op_class::SimdCmp 0 0.00% 60.52%
-system.cpu.op_class::SimdCvt 0 0.00% 60.52%
-system.cpu.op_class::SimdMisc 0 0.00% 60.52%
-system.cpu.op_class::SimdMult 0 0.00% 60.52%
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdShift 0 0.00% 60.52%
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdSqrt 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52%
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52%
-system.cpu.op_class::MemRead 1101 19.78% 80.29%
-system.cpu.op_class::MemWrite 1085 19.49% 99.78%
+system.cpu.op_class::IntAlu 3392 60.90% 61.08%
+system.cpu.op_class::IntMult 2 0.04% 61.11%
+system.cpu.op_class::IntDiv 4 0.07% 61.18%
+system.cpu.op_class::FloatAdd 0 0.00% 61.18%
+system.cpu.op_class::FloatCmp 0 0.00% 61.18%
+system.cpu.op_class::FloatCvt 0 0.00% 61.18%
+system.cpu.op_class::FloatMult 0 0.00% 61.18%
+system.cpu.op_class::FloatMultAcc 0 0.00% 61.18%
+system.cpu.op_class::FloatDiv 0 0.00% 61.18%
+system.cpu.op_class::FloatMisc 0 0.00% 61.18%
+system.cpu.op_class::FloatSqrt 0 0.00% 61.18%
+system.cpu.op_class::SimdAdd 0 0.00% 61.18%
+system.cpu.op_class::SimdAddAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdAlu 0 0.00% 61.18%
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+system.cpu.op_class::SimdShift 0 0.00% 61.18%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 61.18%
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+system.cpu.op_class::SimdFloatAdd 0 0.00% 61.18%
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+system.cpu.op_class::SimdFloatMisc 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatMult 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.18%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.18%
+system.cpu.op_class::MemRead 1082 19.43% 80.61%
+system.cpu.op_class::MemWrite 1068 19.17% 99.78%
system.cpu.op_class::FloatMemRead 0 0.00% 99.78%
system.cpu.op_class::FloatMemWrite 12 0.22% 100.00%
system.cpu.op_class::IprAccess 0 0.00% 100.00%
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
-system.cpu.op_class::total 5567
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34045500
+system.cpu.op_class::total 5570
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system.cpu.dcache.tags.replacements 0
-system.cpu.dcache.tags.tagsinuse 88.524153
-system.cpu.dcache.tags.total_refs 2053
-system.cpu.dcache.tags.sampled_refs 145
-system.cpu.dcache.tags.avg_refs 14.158621
+system.cpu.dcache.tags.tagsinuse 86.061155
+system.cpu.dcache.tags.total_refs 2018
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+system.cpu.dcache.tags.avg_refs 14.013889
system.cpu.dcache.tags.warmup_cycle 0
-system.cpu.dcache.tags.occ_blocks::cpu.data 88.524153
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021612
-system.cpu.dcache.tags.occ_percent::total 0.021612
-system.cpu.dcache.tags.occ_task_id_blocks::1024 145
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 23
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 122
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.035400
-system.cpu.dcache.tags.tag_accesses 4541
-system.cpu.dcache.tags.data_accesses 4541
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34045500
-system.cpu.dcache.ReadReq_hits::cpu.data 1032
-system.cpu.dcache.ReadReq_hits::total 1032
-system.cpu.dcache.WriteReq_hits::cpu.data 1007
-system.cpu.dcache.WriteReq_hits::total 1007
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 6
-system.cpu.dcache.LoadLockedReq_hits::total 6
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.061155
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+system.cpu.dcache.tags.occ_task_id_blocks::1024 144
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+system.cpu.dcache.ReadReq_hits::cpu.data 1013
+system.cpu.dcache.ReadReq_hits::total 1013
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+system.cpu.dcache.LoadLockedReq_hits::cpu.data 7
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system.cpu.dcache.StoreCondReq_hits::cpu.data 8
system.cpu.dcache.StoreCondReq_hits::total 8
-system.cpu.dcache.demand_hits::cpu.data 2039
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-system.cpu.dcache.overall_hits::cpu.data 2039
-system.cpu.dcache.overall_hits::total 2039
+system.cpu.dcache.demand_hits::cpu.data 2003
+system.cpu.dcache.demand_hits::total 2003
+system.cpu.dcache.overall_hits::cpu.data 2003
+system.cpu.dcache.overall_hits::total 2003
system.cpu.dcache.ReadReq_misses::cpu.data 61
system.cpu.dcache.ReadReq_misses::total 61
system.cpu.dcache.WriteReq_misses::cpu.data 82
system.cpu.dcache.WriteReq_misses::total 82
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 2
-system.cpu.dcache.LoadLockedReq_misses::total 2
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system.cpu.dcache.demand_misses::cpu.data 143
system.cpu.dcache.demand_misses::total 143
system.cpu.dcache.overall_misses::cpu.data 143
system.cpu.dcache.ReadReq_miss_latency::total 3843000
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5166000
system.cpu.dcache.WriteReq_miss_latency::total 5166000
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000
-system.cpu.dcache.LoadLockedReq_miss_latency::total 126000
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 63000
system.cpu.dcache.demand_miss_latency::cpu.data 9009000
system.cpu.dcache.demand_miss_latency::total 9009000
system.cpu.dcache.overall_miss_latency::cpu.data 9009000
system.cpu.dcache.overall_miss_latency::total 9009000
-system.cpu.dcache.ReadReq_accesses::cpu.data 1093
-system.cpu.dcache.ReadReq_accesses::total 1093
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 8
system.cpu.dcache.LoadLockedReq_accesses::total 8
system.cpu.dcache.StoreCondReq_accesses::cpu.data 8
system.cpu.dcache.StoreCondReq_accesses::total 8
-system.cpu.dcache.demand_accesses::cpu.data 2182
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-system.cpu.dcache.overall_accesses::total 2182
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.055810
-system.cpu.dcache.ReadReq_miss_rate::total 0.055810
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.075298
-system.cpu.dcache.WriteReq_miss_rate::total 0.075298
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000
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+system.cpu.dcache.demand_accesses::cpu.data 2146
+system.cpu.dcache.demand_accesses::total 2146
+system.cpu.dcache.overall_accesses::cpu.data 2146
+system.cpu.dcache.overall_accesses::total 2146
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.056797
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+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.125000
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+system.cpu.dcache.demand_miss_rate::cpu.data 0.066636
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.066636
+system.cpu.dcache.overall_miss_rate::total 0.066636
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000
system.cpu.dcache.ReadReq_mshr_misses::total 61
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82
system.cpu.dcache.WriteReq_mshr_misses::total 82
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 2
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 1
system.cpu.dcache.demand_mshr_misses::cpu.data 143
system.cpu.dcache.demand_mshr_misses::total 143
system.cpu.dcache.overall_mshr_misses::cpu.data 143
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084000
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8866000
system.cpu.dcache.demand_mshr_miss_latency::total 8866000
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8866000
system.cpu.dcache.overall_mshr_miss_latency::total 8866000
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055810
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-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065536
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.192982
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.179245
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.792115
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.344086
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.192982
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.179245
-system.cpu.toL2Bus.snoop_filter.tot_requests 424
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.344086
+system.cpu.toL2Bus.snoop_filter.tot_requests 372
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
system.cpu.toL2Bus.snoop_filter.tot_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34045500
-system.cpu.toL2Bus.trans_dist::ReadResp 342
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31821500
+system.cpu.toL2Bus.trans_dist::ReadResp 290
system.cpu.toL2Bus.trans_dist::ReadExReq 82
system.cpu.toL2Bus.trans_dist::ReadExResp 82
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 279
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 63
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 290
-system.cpu.toL2Bus.pkt_count::total 848
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9280
-system.cpu.toL2Bus.pkt_size::total 27136
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 228
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 62
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288
+system.cpu.toL2Bus.pkt_count::total 744
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216
+system.cpu.toL2Bus.pkt_size::total 23808
system.cpu.toL2Bus.snoops 0
system.cpu.toL2Bus.snoopTraffic 0
-system.cpu.toL2Bus.snoop_fanout::samples 424
+system.cpu.toL2Bus.snoop_fanout::samples 372
system.cpu.toL2Bus.snoop_fanout::mean 0
system.cpu.toL2Bus.snoop_fanout::stdev 0
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
-system.cpu.toL2Bus.snoop_fanout::0 424 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::0 372 100.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
system.cpu.toL2Bus.snoop_fanout::min_value 0
system.cpu.toL2Bus.snoop_fanout::max_value 0
-system.cpu.toL2Bus.snoop_fanout::total 424
-system.cpu.toL2Bus.reqLayer0.occupancy 212000
+system.cpu.toL2Bus.snoop_fanout::total 372
+system.cpu.toL2Bus.reqLayer0.occupancy 186000
system.cpu.toL2Bus.reqLayer0.utilization 0.6
-system.cpu.toL2Bus.respLayer0.occupancy 418500
-system.cpu.toL2Bus.respLayer0.utilization 1.2
-system.cpu.toL2Bus.respLayer1.occupancy 217500
-system.cpu.toL2Bus.respLayer1.utilization 0.6
-system.membus.snoop_filter.tot_requests 424
+system.cpu.toL2Bus.respLayer0.occupancy 342000
+system.cpu.toL2Bus.respLayer0.utilization 1.1
+system.cpu.toL2Bus.respLayer1.occupancy 216000
+system.cpu.toL2Bus.respLayer1.utilization 0.7
+system.membus.snoop_filter.tot_requests 372
system.membus.snoop_filter.hit_single_requests 0
system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0
system.membus.snoop_filter.hit_single_snoops 0
system.membus.snoop_filter.hit_multi_snoops 0
-system.membus.pwrStateResidencyTicks::UNDEFINED 34045500
-system.membus.trans_dist::ReadResp 342
+system.membus.pwrStateResidencyTicks::UNDEFINED 31821500
+system.membus.trans_dist::ReadResp 290
system.membus.trans_dist::ReadExReq 82
system.membus.trans_dist::ReadExResp 82
-system.membus.trans_dist::ReadSharedReq 342
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 848
-system.membus.pkt_count::total 848
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27136
-system.membus.pkt_size::total 27136
+system.membus.trans_dist::ReadSharedReq 290
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 744
+system.membus.pkt_count::total 744
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23808
+system.membus.pkt_size::total 23808
system.membus.snoops 0
system.membus.snoopTraffic 0
-system.membus.snoop_fanout::samples 424
+system.membus.snoop_fanout::samples 372
system.membus.snoop_fanout::mean 0
system.membus.snoop_fanout::stdev 0
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
-system.membus.snoop_fanout::0 424 100.00% 100.00%
+system.membus.snoop_fanout::0 372 100.00% 100.00%
system.membus.snoop_fanout::1 0 0.00% 100.00%
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
system.membus.snoop_fanout::min_value 0
system.membus.snoop_fanout::max_value 0
-system.membus.snoop_fanout::total 424
-system.membus.reqLayer0.occupancy 424500
+system.membus.snoop_fanout::total 372
+system.membus.reqLayer0.occupancy 372500
system.membus.reqLayer0.utilization 1.2
-system.membus.respLayer1.occupancy 2120000
-system.membus.respLayer1.utilization 6.2
+system.membus.respLayer1.occupancy 1860000
+system.membus.respLayer1.utilization 5.8
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:29
-gem5 executing on zizzer, pid 34061
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:12:00
+gem5 executing on boldrock, pid 2001
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
-Exiting @ tick 167328500 because target called exit()
+Exiting @ tick 179565500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000167 # Number of seconds simulated
-sim_ticks 167318000 # Number of ticks simulated
-final_tick 167318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 259842 # Simulator instruction rate (inst/s)
-host_op_rate 259907 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 381385356 # Simulator tick rate (ticks/s)
-host_mem_usage 261864 # Number of bytes of host memory used
-host_seconds 0.44 # Real time elapsed on the host
-sim_insts 113991 # Number of instructions simulated
-sim_ops 114022 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 69760 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 314801755 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 102128880 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 416930635 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314801755 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314801755 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314801755 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 102128880 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 416930635 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1090 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 110 # Per bank write bursts
-system.physmem.perBankRdBursts::1 4 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9 # Per bank write bursts
-system.physmem.perBankRdBursts::3 124 # Per bank write bursts
-system.physmem.perBankRdBursts::4 62 # Per bank write bursts
-system.physmem.perBankRdBursts::5 92 # Per bank write bursts
-system.physmem.perBankRdBursts::6 88 # Per bank write bursts
-system.physmem.perBankRdBursts::7 18 # Per bank write bursts
-system.physmem.perBankRdBursts::8 55 # Per bank write bursts
-system.physmem.perBankRdBursts::9 86 # Per bank write bursts
-system.physmem.perBankRdBursts::10 90 # Per bank write bursts
-system.physmem.perBankRdBursts::11 38 # Per bank write bursts
-system.physmem.perBankRdBursts::12 113 # Per bank write bursts
-system.physmem.perBankRdBursts::13 94 # Per bank write bursts
-system.physmem.perBankRdBursts::14 101 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 166987000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1090 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation
-system.physmem.totQLat 15449500 # Total ticks spent queuing
-system.physmem.totMemAccLat 35887000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 14173.85 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 32923.85 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 416.93 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 416.93 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.26 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 874 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 153199.08 # Average gap between requests
-system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9302400 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 492960 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 55152630 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 7141920 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 92948520 # Total energy per rank (pJ)
-system.physmem_0.averagePower 555.517657 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 145123750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 18593750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 120934750 # Time in different power states
-system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 9796590 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 484800 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 44771220 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 12438240 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 4464180 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 90201825 # Total energy per rank (pJ)
-system.physmem_1.averagePower 539.101715 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 144258000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 13998250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 32388000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 98166000 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 31578 # Number of BP lookups
-system.cpu.branchPred.condPredicted 20002 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2179 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 27728 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 15512 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 55.943451 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 5649 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 3670 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1979 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 43 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 334636 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113991 # Number of instructions committed
-system.cpu.committedOps 114022 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 5891 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 2.935635 # CPI: cycles per instruction
-system.cpu.ipc 0.340642 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction
-system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction
-system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 114022 # Class of committed instruction
-system.cpu.tickCycles 171594 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 163042 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 215.201598 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 44063 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 164.414179 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 215.201598 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.052539 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.052539 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 89312 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 89312 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 24531 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 24531 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 44057 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 44057 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 44057 # number of overall hits
-system.cpu.dcache.overall_hits::total 44057 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses
-system.cpu.dcache.overall_misses::total 459 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8632500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 39369500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 39369500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 39369500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 39369500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24606 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24606 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 44516 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 44516 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 44516 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 44516 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.010311 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.010311 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.010311 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.010311 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115100 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 115100 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 85772.331155 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 85772.331155 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 85772.331155 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 185 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 185 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23917000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23917000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23917000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23917000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115413.043478 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115413.043478 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id
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-system.cpu.icache.overall_misses::total 823 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 69983000 # number of ReadReq miss cycles
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-system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
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-system.cpu.icache.overall_mshr_miss_latency::total 69160000 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016303 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total 0.016303 # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84034.021871 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84034.021871 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84034.021871 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 84034.021871 # average overall mshr miss latency
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-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 622.705265 # Cycle average of tags in use
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-system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.947689 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits
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-system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 823 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 823 # number of ReadCleanReq misses
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-system.cpu.l2cache.ReadSharedReq_misses::total 68 # number of ReadSharedReq misses
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-system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total 67925500 # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data 23501500 # number of overall miss cycles
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-system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88020.599251 # average overall miss latency
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-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59695500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59695500 # number of ReadCleanReq MSHR miss cycles
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72534.021871 # average ReadCleanReq mshr miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105404.411765 # average ReadSharedReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72534.021871 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78020.599251 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
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-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 167318000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 891 # Transaction distribution
-system.membus.trans_dist::ReadExReq 199 # Transaction distribution
-system.membus.trans_dist::ReadExResp 199 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1090 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1090 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1229000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
+sim_seconds 0.000180
+sim_ticks 179565500
+final_tick 179565500
+sim_freq 1000000000000
+host_inst_rate 6153
+host_op_rate 6167
+host_tick_rate 10087955
+host_mem_usage 272768
+host_seconds 17.80
+sim_insts 109528
+sim_ops 109773
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 179565500
+system.physmem.bytes_read::cpu.inst 61184
+system.physmem.bytes_read::cpu.data 29952
+system.physmem.bytes_read::total 91136
+system.physmem.bytes_inst_read::cpu.inst 61184
+system.physmem.bytes_inst_read::total 61184
+system.physmem.num_reads::cpu.inst 956
+system.physmem.num_reads::cpu.data 468
+system.physmem.num_reads::total 1424
+system.physmem.bw_read::cpu.inst 340733604
+system.physmem.bw_read::cpu.data 166802643
+system.physmem.bw_read::total 507536247
+system.physmem.bw_inst_read::cpu.inst 340733604
+system.physmem.bw_inst_read::total 340733604
+system.physmem.bw_total::cpu.inst 340733604
+system.physmem.bw_total::cpu.data 166802643
+system.physmem.bw_total::total 507536247
+system.physmem.readReqs 1424
+system.physmem.writeReqs 0
+system.physmem.readBursts 1424
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 91136
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 91136
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 150
+system.physmem.perBankRdBursts::1 98
+system.physmem.perBankRdBursts::2 131
+system.physmem.perBankRdBursts::3 90
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+system.physmem.perBankRdBursts::6 30
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+system.physmem.perBankRdBursts::8 86
+system.physmem.perBankRdBursts::9 121
+system.physmem.perBankRdBursts::10 196
+system.physmem.perBankRdBursts::11 159
+system.physmem.perBankRdBursts::12 54
+system.physmem.perBankRdBursts::13 56
+system.physmem.perBankRdBursts::14 52
+system.physmem.perBankRdBursts::15 47
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
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+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 179469000
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1424
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+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
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+system.physmem.writePktSize::6 0
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+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 280
+system.physmem.bytesPerActivate::mean 325.028571
+system.physmem.bytesPerActivate::gmean 221.322683
+system.physmem.bytesPerActivate::stdev 282.766211
+system.physmem.bytesPerActivate::0-127 66 23.57% 23.57%
+system.physmem.bytesPerActivate::128-255 73 26.07% 49.64%
+system.physmem.bytesPerActivate::256-383 52 18.57% 68.21%
+system.physmem.bytesPerActivate::384-511 23 8.21% 76.43%
+system.physmem.bytesPerActivate::512-639 18 6.43% 82.86%
+system.physmem.bytesPerActivate::640-767 15 5.36% 88.21%
+system.physmem.bytesPerActivate::768-895 9 3.21% 91.43%
+system.physmem.bytesPerActivate::896-1023 8 2.86% 94.29%
+system.physmem.bytesPerActivate::1024-1151 16 5.71% 100.00%
+system.physmem.bytesPerActivate::total 280
+system.physmem.totQLat 18481500
+system.physmem.totMemAccLat 45181500
+system.physmem.totBusLat 7120000
+system.physmem.avgQLat 12978.58
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 31728.58
+system.physmem.avgRdBW 507.54
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 507.54
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 3.97
+system.physmem.busUtilRead 3.97
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.15
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1142
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 80.20
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 126031.60
+system.physmem.pageHitRate 80.20
+system.physmem_0.actEnergy 828240
+system.physmem_0.preEnergy 436425
+system.physmem_0.readEnergy 4662420
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 14136720.000000
+system.physmem_0.actBackEnergy 11510580
+system.physmem_0.preBackEnergy 297600
+system.physmem_0.actPowerDownEnergy 64012140
+system.physmem_0.prePowerDownEnergy 5057760
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 100941885
+system.physmem_0.averagePower 562.142858
+system.physmem_0.totalIdleTime 153511750
+system.physmem_0.memoryStateTime::IDLE 126000
+system.physmem_0.memoryStateTime::REF 5980000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 13167500
+system.physmem_0.memoryStateTime::ACT 19901750
+system.physmem_0.memoryStateTime::ACT_PDN 140390250
+system.physmem_1.actEnergy 1185240
+system.physmem_1.preEnergy 626175
+system.physmem_1.readEnergy 5504940
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 14136720.000000
+system.physmem_1.actBackEnergy 12449940
+system.physmem_1.preBackEnergy 329760
+system.physmem_1.actPowerDownEnergy 64714950
+system.physmem_1.prePowerDownEnergy 3642720
+system.physmem_1.selfRefreshEnergy 0
+system.physmem_1.totalEnergy 102590445
+system.physmem_1.averagePower 571.323648
+system.physmem_1.totalIdleTime 151247750
+system.physmem_1.memoryStateTime::IDLE 223500
+system.physmem_1.memoryStateTime::REF 5980000
+system.physmem_1.memoryStateTime::SREF 0
+system.physmem_1.memoryStateTime::PRE_PDN 9481500
+system.physmem_1.memoryStateTime::ACT 21938750
+system.physmem_1.memoryStateTime::ACT_PDN 141941750
+system.pwrStateResidencyTicks::UNDEFINED 179565500
+system.cpu.branchPred.lookups 32783
+system.cpu.branchPred.condPredicted 22516
+system.cpu.branchPred.condIncorrect 2844
+system.cpu.branchPred.BTBLookups 25031
+system.cpu.branchPred.BTBHits 11486
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 45.887100
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 6560
+system.cpu.branchPred.indirectHits 3275
+system.cpu.branchPred.indirectMisses 3285
+system.cpu.branchPredindirectMispredicted 1342
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
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+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
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+system.cpu.workload.numSyscalls 43
+system.cpu.pwrStateResidencyTicks::ON 179565500
+system.cpu.numCycles 359131
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 109528
+system.cpu.committedOps 109773
+system.cpu.discardedOps 8007
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+system.cpu.cpi 3.278897
+system.cpu.ipc 0.304981
+system.cpu.op_class_0::No_OpClass 47 0.04% 0.04%
+system.cpu.op_class_0::IntAlu 67339 61.34% 61.39%
+system.cpu.op_class_0::IntMult 107 0.10% 61.48%
+system.cpu.op_class_0::IntDiv 4 0.00% 61.49%
+system.cpu.op_class_0::FloatAdd 0 0.00% 61.49%
+system.cpu.op_class_0::FloatCmp 0 0.00% 61.49%
+system.cpu.op_class_0::FloatCvt 0 0.00% 61.49%
+system.cpu.op_class_0::FloatMult 0 0.00% 61.49%
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.49%
+system.cpu.op_class_0::FloatDiv 0 0.00% 61.49%
+system.cpu.op_class_0::FloatMisc 0 0.00% 61.49%
+system.cpu.op_class_0::FloatSqrt 0 0.00% 61.49%
+system.cpu.op_class_0::SimdAdd 0 0.00% 61.49%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdAlu 0 0.00% 61.49%
+system.cpu.op_class_0::SimdCmp 0 0.00% 61.49%
+system.cpu.op_class_0::SimdCvt 0 0.00% 61.49%
+system.cpu.op_class_0::SimdMisc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdMult 0 0.00% 61.49%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdShift 0 0.00% 61.49%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.49%
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.49%
+system.cpu.op_class_0::MemRead 25597 23.32% 84.81%
+system.cpu.op_class_0::MemWrite 16667 15.18% 99.99%
+system.cpu.op_class_0::FloatMemRead 0 0.00% 99.99%
+system.cpu.op_class_0::FloatMemWrite 12 0.01% 100.00%
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class_0::total 109773
+system.cpu.tickCycles 168707
+system.cpu.idleCycles 190424
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 179565500
+system.cpu.dcache.tags.replacements 0
+system.cpu.dcache.tags.tagsinuse 310.080119
+system.cpu.dcache.tags.total_refs 42815
+system.cpu.dcache.tags.sampled_refs 469
+system.cpu.dcache.tags.avg_refs 91.289979
+system.cpu.dcache.tags.warmup_cycle 0
+system.cpu.dcache.tags.occ_blocks::cpu.data 310.080119
+system.cpu.dcache.tags.occ_percent::cpu.data 0.075703
+system.cpu.dcache.tags.occ_percent::total 0.075703
+system.cpu.dcache.tags.occ_task_id_blocks::1024 469
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 14
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 154
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 301
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.114502
+system.cpu.dcache.tags.tag_accesses 87381
+system.cpu.dcache.tags.data_accesses 87381
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 179565500
+system.cpu.dcache.ReadReq_hits::cpu.data 26260
+system.cpu.dcache.ReadReq_hits::total 26260
+system.cpu.dcache.WriteReq_hits::cpu.data 16004
+system.cpu.dcache.WriteReq_hits::total 16004
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 275
+system.cpu.dcache.LoadLockedReq_hits::total 275
+system.cpu.dcache.StoreCondReq_hits::cpu.data 276
+system.cpu.dcache.StoreCondReq_hits::total 276
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74994.658120
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72687.017544
+system.cpu.toL2Bus.snoop_filter.tot_requests 1527
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 95
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 179565500
+system.cpu.toL2Bus.trans_dist::ReadResp 1205
+system.cpu.toL2Bus.trans_dist::WritebackClean 94
+system.cpu.toL2Bus.trans_dist::ReadExReq 227
+system.cpu.toL2Bus.trans_dist::ReadExResp 227
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 964
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 242
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2021
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 938
+system.cpu.toL2Bus.pkt_count::total 2959
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+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30016
+system.cpu.toL2Bus.pkt_size::total 97664
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1433
+system.cpu.toL2Bus.snoop_fanout::mean 0.000698
+system.cpu.toL2Bus.snoop_fanout::stdev 0.026417
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1432 99.93% 99.93%
+system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 1433
+system.cpu.toL2Bus.reqLayer0.occupancy 857500
+system.cpu.toL2Bus.reqLayer0.utilization 0.5
+system.cpu.toL2Bus.respLayer0.occupancy 1444500
+system.cpu.toL2Bus.respLayer0.utilization 0.8
+system.cpu.toL2Bus.respLayer1.occupancy 703500
+system.cpu.toL2Bus.respLayer1.utilization 0.4
+system.membus.snoop_filter.tot_requests 1424
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 179565500
+system.membus.trans_dist::ReadResp 1197
+system.membus.trans_dist::ReadExReq 227
+system.membus.trans_dist::ReadExResp 227
+system.membus.trans_dist::ReadSharedReq 1197
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2848
+system.membus.pkt_count::total 2848
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 91136
+system.membus.pkt_size::total 91136
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1424
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1424 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1424
+system.membus.reqLayer0.occupancy 1641000
+system.membus.reqLayer0.utilization 0.9
+system.membus.respLayer1.occupancy 7572000
+system.membus.respLayer1.utilization 4.2
---------- End Simulation Statistics ----------
--- /dev/null
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+
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+
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+
+[system.cpu.branchPred]
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+
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+
+[system.cpu.dcache.tags]
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+
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+
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+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
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+default_p_state=UNDEFINED
+demand_mshr_reserve=1
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+is_read_only=false
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+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.038000
+IDD3P12=0.000000
+IDD4R=0.157000
+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+max_accesses_per_row=16
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+min_writes_per_switch=16
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1000,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.157",
+ "burst_length": 8,
+ "tRTP": 7500,
+ "IDD4W": "0.125",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "power_model": null,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 6000,
+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
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+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
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+ "smtLSQThreshold": 100,
+ "fetchTrapLatency": 1,
+ "iewToRenameDelay": 1,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
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+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
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+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
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+ "name": "tags",
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+ "eventq_index": 0,
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+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
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+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
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+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "fetchWidth": 8,
+ "max_loads_all_threads": 0,
+ "cpu_id": 0,
+ "fetchToDecodeDelay": 1,
+ "renameToDecodeDelay": 1,
+ "do_quiesce": true,
+ "renameToROBDelay": 1,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "decodeWidth": 8,
+ "commitToFetchDelay": 1,
+ "needsTSO": false,
+ "smtIQThreshold": 100,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "SSITSize": 1024,
+ "activity": 0,
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ },
+ "decodeToFetchDelay": 1,
+ "renameWidth": 8,
+ "numThreads": 1,
+ "syscallRetryLatency": 10000,
+ "squashWidth": 8,
+ "function_trace": false,
+ "backComSize": 5,
+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
+ "point_of_coherency": false,
+ "system": "system",
+ "response_latency": 1,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "p_state_clk_gate_min": 1000,
+ "fuPool": {
+ "name": "fuPool",
+ "FUList": [
+ {
+ "count": 6,
+ "opList": [
+ {
+ "opClass": "IntAlu",
+ "opLat": 1,
+ "name": "opList",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList0.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList0",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList0",
+ "type": "FUDesc"
+ },
+ {
+ "count": 2,
+ "opList": [
+ {
+ "opClass": "IntMult",
+ "opLat": 3,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList1.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "IntDiv",
+ "opLat": 20,
+ "name": "opList1",
+ "pipelined": false,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList1.opList1",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList1",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList1",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "opClass": "FloatAdd",
+ "opLat": 2,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatCmp",
+ "opLat": 2,
+ "name": "opList1",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatCvt",
+ "opLat": 2,
+ "name": "opList2",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList2",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList2",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList2",
+ "type": "FUDesc"
+ },
+ {
+ "count": 2,
+ "opList": [
+ {
+ "opClass": "FloatMult",
+ "opLat": 4,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList0",
+ "type": "OpDesc"
+ },
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+ "role": "MASTER"
+ },
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+ "writeback_clean": true,
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+ "eventq_index": 0,
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+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
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+ "type": "LRU",
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+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
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+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
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+ "tag_latency": 2,
+ "name": "icache",
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+ "sequential_access": false,
+ "assoc": 2
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+ "numRobs": 1,
+ "switched_out": false,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "smtROBThreshold": 100,
+ "numIQEntries": 64,
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+ "BTBEntries": 4096,
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+ "type": "TournamentBP",
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+ "choiceCtrBits": 2,
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+ "path": "system.cpu.branchPred",
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+ "globalPredictorSize": 8192,
+ "name": "branchPred",
+ "indirectHashTargets": true,
+ "instShiftAmt": 2,
+ "indirectTagSize": 16,
+ "BTBTagSize": 16
+ },
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "smtROBPolicy": "Partitioned",
+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "dcache": {
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+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
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+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
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+ "tag_latency": 2,
+ "name": "tags",
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+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "numPhysVecRegs": 256,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "smtCommitPolicy": "RoundRobin",
+ "issueToExecuteDelay": 1,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
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+ "fetchQueueSize": 32,
+ "iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 0,
+ "renameToIEWDelay": 2,
+ "p_state_clk_gate_bins": 20,
+ "progress_interval": 0,
+ "LQEntries": 32
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6011
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/o3-timing
+
+Global frequency set at 1000000000000 ticks per second
+lr.w/sc.w: PASS
+sc.w, no preceding lr.d: PASS
+amoswap.w: PASS
+amoswap.w, sign extend: PASS
+amoswap.w, truncate: PASS
+amoadd.w: PASS
+amoadd.w, truncate/overflow: PASS
+amoadd.w, sign extend: PASS
+amoxor.w, truncate: PASS
+amoxor.w, sign extend: PASS
+amoand.w, truncate: PASS
+amoand.w, sign extend: PASS
+amoor.w, truncate: PASS
+amoor.w, sign extend: PASS
+amomin.w, truncate: PASS
+amomin.w, sign extend: PASS
+amomax.w, truncate: PASS
+amomax.w, sign extend: PASS
+amominu.w, truncate: PASS
+amominu.w, sign extend: PASS
+amomaxu.w, truncate: PASS
+amomaxu.w, sign extend: PASS
+lr.d/sc.d: PASS
+sc.d, no preceding lr.d: PASS
+amoswap.d: PASS
+amoadd.d: PASS
+amoadd.d, overflow: PASS
+amoxor.d (1): PASS
+amoxor.d (0): PASS
+amoand.d: PASS
+amoor.d: PASS
+amomin.d: PASS
+amomax.d: PASS
+amominu.d: PASS
+amomaxu.d: PASS
+Exiting @ tick 125677500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000126
+sim_ticks 125677500
+final_tick 125677500
+sim_freq 1000000000000
+host_inst_rate 4939
+host_op_rate 4950
+host_tick_rate 5669654
+host_mem_usage 272252
+host_seconds 22.17
+sim_insts 109485
+sim_ops 109730
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 125677500
+system.physmem.bytes_read::cpu.inst 55552
+system.physmem.bytes_read::cpu.data 30016
+system.physmem.bytes_read::total 85568
+system.physmem.bytes_inst_read::cpu.inst 55552
+system.physmem.bytes_inst_read::total 55552
+system.physmem.num_reads::cpu.inst 868
+system.physmem.num_reads::cpu.data 469
+system.physmem.num_reads::total 1337
+system.physmem.bw_read::cpu.inst 442020250
+system.physmem.bw_read::cpu.data 238833522
+system.physmem.bw_read::total 680853773
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+system.physmem.bytesPerActivate::384-511 25 8.33% 81.00%
+system.physmem.bytesPerActivate::512-639 15 5.00% 86.00%
+system.physmem.bytesPerActivate::640-767 14 4.67% 90.67%
+system.physmem.bytesPerActivate::768-895 6 2.00% 92.67%
+system.physmem.bytesPerActivate::896-1023 7 2.33% 95.00%
+system.physmem.bytesPerActivate::1024-1151 15 5.00% 100.00%
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+system.cpu.iq.issued_per_cycle::7 96 0.06% 99.95%
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+system.cpu.iq.FU_type_0::FloatMult 34 0.03% 62.45%
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+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45%
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+system.cpu.iq.FU_type_0::MemRead 28636 23.30% 85.75%
+system.cpu.iq.FU_type_0::MemWrite 17490 14.23% 99.97%
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+system.cpu.iq.FU_type_0::FloatMemWrite 31 0.03% 100.00%
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+system.cpu.iq.FU_type_0::total 122918
+system.cpu.iq.rate 0.489020
+system.cpu.iq.fu_busy_cnt 266
+system.cpu.iq.fu_busy_rate 0.002164
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+system.cpu.l2cache.WritebackClean_hits::total 70
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+system.cpu.l2cache.demand_hits::total 10
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+system.cpu.l2cache.WritebackClean_accesses::total 70
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+system.cpu.l2cache.demand_accesses::cpu.inst 878
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85021.889401
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+system.cpu.l2cache.overall_avg_miss_latency::total 86278.608826
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 218
+system.cpu.l2cache.ReadExReq_mshr_misses::total 218
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 868
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 868
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 251
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 868
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+system.cpu.l2cache.demand_mshr_misses::total 1337
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+system.cpu.toL2Bus.trans_dist::ReadResp 1128
+system.cpu.toL2Bus.trans_dist::WritebackClean 70
+system.cpu.toL2Bus.trans_dist::ReadExReq 218
+system.cpu.toL2Bus.trans_dist::ReadExResp 218
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 878
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+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 938
+system.cpu.toL2Bus.pkt_count::total 2763
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60608
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30016
+system.cpu.toL2Bus.pkt_size::total 90624
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1347
+system.cpu.toL2Bus.snoop_fanout::mean 0
+system.cpu.toL2Bus.snoop_fanout::stdev 0
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1347 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 0
+system.cpu.toL2Bus.snoop_fanout::total 1347
+system.cpu.toL2Bus.reqLayer0.occupancy 778500
+system.cpu.toL2Bus.reqLayer0.utilization 0.6
+system.cpu.toL2Bus.respLayer0.occupancy 1315500
+system.cpu.toL2Bus.respLayer0.utilization 1.0
+system.cpu.toL2Bus.respLayer1.occupancy 703500
+system.cpu.toL2Bus.respLayer1.utilization 0.6
+system.membus.snoop_filter.tot_requests 1337
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 125677500
+system.membus.trans_dist::ReadResp 1119
+system.membus.trans_dist::ReadExReq 218
+system.membus.trans_dist::ReadExResp 218
+system.membus.trans_dist::ReadSharedReq 1119
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2674
+system.membus.pkt_count::total 2674
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85568
+system.membus.pkt_size::total 85568
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1337
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1337 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1337
+system.membus.reqLayer0.occupancy 1642500
+system.membus.reqLayer0.utilization 1.3
+system.membus.respLayer1.occupancy 7097750
+system.membus.respLayer1.utilization 5.6
+
+---------- End Simulation Statistics ----------
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:29
-gem5 executing on zizzer, pid 34062
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:10:21
+gem5 executing on boldrock, pid 1519
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
lr.w/sc.w: PASS
sc.w, no preceding lr.d: PASS
amoswap.w: PASS
amomax.d: PASS
amominu.d: PASS
amomaxu.d: PASS
-Exiting @ tick 57010500 because target called exit()
+Exiting @ tick 68573500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000057 # Number of seconds simulated
-sim_ticks 57010500 # Number of ticks simulated
-final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 83371 # Simulator instruction rate (inst/s)
-host_op_rate 83392 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41711101 # Simulator tick rate (ticks/s)
-host_mem_usage 233576 # Number of bytes of host memory used
-host_seconds 1.37 # Real time elapsed on the host
-sim_insts 113947 # Number of instructions simulated
-sim_ops 113978 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory
-system.physmem.bytes_read::total 612818 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory
-system.physmem.bytes_written::total 111519 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 43 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 114022 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113947 # Number of instructions committed
-system.cpu.committedOps 113978 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 8601 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls
-system.cpu.num_int_insts 113979 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 152039 # number of times the integer registers were read
-system.cpu.num_int_register_writes 76786 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 43694 # number of memory refs
-system.cpu.num_load_insts 23779 # Number of load instructions
-system.cpu.num_store_insts 19915 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 114022 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 25914 # Number of branches fetched
-system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction
-system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction
-system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction
-system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 114022 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 137768 # Transaction distribution
-system.membus.trans_dist::ReadResp 137770 # Transaction distribution
-system.membus.trans_dist::WriteReq 19910 # Transaction distribution
-system.membus.trans_dist::WriteResp 19910 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 4 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 4 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 157684 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 157684 # Request fanout histogram
+sim_seconds 0.000069
+sim_ticks 68573500
+final_tick 68573500
+sim_freq 1000000000000
+host_inst_rate 3619
+host_op_rate 3627
+host_tick_rate 2266534
+host_mem_usage 259192
+host_seconds 30.26
+sim_insts 109485
+sim_ops 109730
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 68573500
+system.physmem.bytes_read::cpu.inst 547612
+system.physmem.bytes_read::cpu.data 174025
+system.physmem.bytes_read::total 721637
+system.physmem.bytes_inst_read::cpu.inst 547612
+system.physmem.bytes_inst_read::total 547612
+system.physmem.bytes_written::cpu.data 113591
+system.physmem.bytes_written::total 113591
+system.physmem.num_reads::cpu.inst 136903
+system.physmem.num_reads::cpu.data 25597
+system.physmem.num_reads::total 162500
+system.physmem.num_writes::cpu.data 16677
+system.physmem.num_writes::total 16677
+system.physmem.bw_read::cpu.inst 7985767097
+system.physmem.bw_read::cpu.data 2537787921
+system.physmem.bw_read::total 10523555018
+system.physmem.bw_inst_read::cpu.inst 7985767097
+system.physmem.bw_inst_read::total 7985767097
+system.physmem.bw_write::cpu.data 1656485377
+system.physmem.bw_write::total 1656485377
+system.physmem.bw_total::cpu.inst 7985767097
+system.physmem.bw_total::cpu.data 4194273298
+system.physmem.bw_total::total 12180040395
+system.pwrStateResidencyTicks::UNDEFINED 68573500
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 43
+system.cpu.pwrStateResidencyTicks::ON 68573500
+system.cpu.numCycles 137148
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 109485
+system.cpu.committedOps 109730
+system.cpu.num_int_alu_accesses 109164
+system.cpu.num_fp_alu_accesses 12
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 6221
+system.cpu.num_conditional_control_insts 18218
+system.cpu.num_int_insts 109164
+system.cpu.num_fp_insts 12
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 137211
+system.cpu.num_int_register_writes 72083
+system.cpu.num_fp_register_reads 12
+system.cpu.num_fp_register_writes 0
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 42276
+system.cpu.num_load_insts 25597
+system.cpu.num_store_insts 16679
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 137148
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 24439
+system.cpu.op_class::No_OpClass 47 0.04% 0.04%
+system.cpu.op_class::IntAlu 67339 61.34% 61.39%
+system.cpu.op_class::IntMult 107 0.10% 61.48%
+system.cpu.op_class::IntDiv 4 0.00% 61.49%
+system.cpu.op_class::FloatAdd 0 0.00% 61.49%
+system.cpu.op_class::FloatCmp 0 0.00% 61.49%
+system.cpu.op_class::FloatCvt 0 0.00% 61.49%
+system.cpu.op_class::FloatMult 0 0.00% 61.49%
+system.cpu.op_class::FloatMultAcc 0 0.00% 61.49%
+system.cpu.op_class::FloatDiv 0 0.00% 61.49%
+system.cpu.op_class::FloatMisc 0 0.00% 61.49%
+system.cpu.op_class::FloatSqrt 0 0.00% 61.49%
+system.cpu.op_class::SimdAdd 0 0.00% 61.49%
+system.cpu.op_class::SimdAddAcc 0 0.00% 61.49%
+system.cpu.op_class::SimdAlu 0 0.00% 61.49%
+system.cpu.op_class::SimdCmp 0 0.00% 61.49%
+system.cpu.op_class::SimdCvt 0 0.00% 61.49%
+system.cpu.op_class::SimdMisc 0 0.00% 61.49%
+system.cpu.op_class::SimdMult 0 0.00% 61.49%
+system.cpu.op_class::SimdMultAcc 0 0.00% 61.49%
+system.cpu.op_class::SimdShift 0 0.00% 61.49%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 61.49%
+system.cpu.op_class::SimdSqrt 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMult 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49%
+system.cpu.op_class::MemRead 25597 23.32% 84.81%
+system.cpu.op_class::MemWrite 16667 15.18% 99.99%
+system.cpu.op_class::FloatMemRead 0 0.00% 99.99%
+system.cpu.op_class::FloatMemWrite 12 0.01% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 109773
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 68573500
+system.membus.trans_dist::ReadReq 162224
+system.membus.trans_dist::ReadResp 162500
+system.membus.trans_dist::WriteReq 16401
+system.membus.trans_dist::WriteResp 16401
+system.membus.trans_dist::LoadLockedReq 276
+system.membus.trans_dist::StoreCondReq 276
+system.membus.trans_dist::StoreCondResp 276
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 273806
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 84548
+system.membus.pkt_count::total 358354
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 547612
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 287616
+system.membus.pkt_size::total 835228
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 179177
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 179177 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 179177
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
+addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
-transitions_per_cycle=4
+transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+addr_ranges=0:268435455:5:0:0:0
eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
+addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
- "cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
"support_data_reqs": true,
"is_cpu_sequencer": true
},
- "type": "L1Cache_Controller",
+ "cxx_class": "L1Cache_Controller",
"issue_latency": 2,
+ "type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
- "transitions_per_cycle": 4,
+ "transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
- "version": 0,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
- "type": "RubyDirectoryMemory",
- "numa_high_bit": 5,
- "size": 268435456
+ "type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:31
-gem5 executing on zizzer, pid 34069
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:52
+gem5 executing on boldrock, pid 1958
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-lr.w/sc.w: \e[1;31mFAIL\e[0m (expected (-1, 0); found (-1, 1))
-Exiting @ tick 796036 because target called exit()
+lr.w/sc.w: PASS
+sc.w, no preceding lr.d: PASS
+amoswap.w: PASS
+amoswap.w, sign extend: PASS
+amoswap.w, truncate: PASS
+amoadd.w: PASS
+amoadd.w, truncate/overflow: PASS
+amoadd.w, sign extend: PASS
+amoxor.w, truncate: PASS
+amoxor.w, sign extend: PASS
+amoand.w, truncate: PASS
+amoand.w, sign extend: PASS
+amoor.w, truncate: PASS
+amoor.w, sign extend: PASS
+amomin.w, truncate: PASS
+amomin.w, sign extend: PASS
+amomax.w, truncate: PASS
+amomax.w, sign extend: PASS
+amominu.w, truncate: PASS
+amominu.w, sign extend: PASS
+amomaxu.w, truncate: PASS
+amomaxu.w, sign extend: PASS
+lr.d/sc.d: PASS
+sc.d, no preceding lr.d: PASS
+amoswap.d: PASS
+amoadd.d: PASS
+amoadd.d, overflow: PASS
+amoxor.d (1): PASS
+amoxor.d (0): PASS
+amoand.d: PASS
+amoor.d: PASS
+amomin.d: PASS
+amomax.d: PASS
+amominu.d: PASS
+amomaxu.d: PASS
+Exiting @ tick 1861905 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000796 # Number of seconds simulated
-sim_ticks 796036 # Number of ticks simulated
-final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 163786 # Simulator instruction rate (inst/s)
-host_op_rate 163781 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1970174 # Simulator tick rate (ticks/s)
-host_mem_usage 428500 # Number of bytes of host memory used
-host_seconds 0.40 # Real time elapsed on the host
-sim_insts 66173 # Number of instructions simulated
-sim_ops 66173 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 14050 # Number of read requests accepted
-system.mem_ctrls.writeReqs 14046 # Number of write requests accepted
-system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 795950 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 72649 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 28.33 # Average gap between requests
-system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states
-system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.cpu.clk_domain.clock 1 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 9 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 796036 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 66173 # Number of instructions committed
-system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 5169 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
-system.cpu.num_int_insts 66174 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
-system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 24255 # number of memory refs
-system.cpu.num_load_insts 11810 # Number of load instructions
-system.cpu.num_store_insts 12445 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 796036 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 15480 # Number of branches fetched
-system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
-system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
-system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
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-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
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-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
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-system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
-system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 66183 # Class of executed instruction
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 1 # delay histogram for all message
-system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 28096 # delay histogram for all message
-system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 28096 # delay histogram for all message
+sim_seconds 0.001862
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+system.cpu.op_class::SimdShift 0 0.00% 61.49%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 61.49%
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+system.cpu.op_class::SimdFloatCvt 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMult 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.49%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.49%
+system.cpu.op_class::MemRead 25597 23.32% 84.81%
+system.cpu.op_class::MemWrite 16667 15.18% 99.99%
+system.cpu.op_class::FloatMemRead 0 0.00% 99.99%
+system.cpu.op_class::FloatMemWrite 12 0.01% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 109773
+system.ruby.clk_domain.clock 1
+system.ruby.pwrStateResidencyTicks::UNDEFINED 1861905
+system.ruby.delayHist::bucket_size 1
+system.ruby.delayHist::max_bucket 9
+system.ruby.delayHist::samples 56808
+system.ruby.delayHist | 56808 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.delayHist::total 56808
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 90437
+system.ruby.outstanding_req_hist_seqr::samples 179178
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 90437
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 179178 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 179178
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 90436
-system.ruby.latency_hist_seqr::mean 7.802203
-system.ruby.latency_hist_seqr::gmean 1.774694
-system.ruby.latency_hist_seqr::stdev 20.056111
-system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00%
-system.ruby.latency_hist_seqr::total 90436
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+system.ruby.latency_hist_seqr::mean 9.391429
+system.ruby.latency_hist_seqr::gmean 1.842545
+system.ruby.latency_hist_seqr::stdev 24.126992
+system.ruby.latency_hist_seqr | 167034 93.22% 93.22% | 11341 6.33% 99.55% | 523 0.29% 99.84% | 82 0.05% 99.89% | 110 0.06% 99.95% | 70 0.04% 99.99% | 5 0.00% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00%
+system.ruby.latency_hist_seqr::total 179177
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 76386
+system.ruby.hit_latency_hist_seqr::samples 150771
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 76386
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 150771 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 14050
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-system.ruby.miss_latency_hist_seqr::gmean 40.136483
-system.ruby.miss_latency_hist_seqr::stdev 31.144722
-system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
-system.ruby.miss_latency_hist_seqr::total 14050
-system.ruby.Directory.incomplete_times_seqr 14049
-system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.017645 # Average number of messages in buffer
-system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.999377 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.035295 # Average number of messages in buffer
-system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.715164 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.017650 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999913 # Average number of cycles messages are stalled in this MB
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-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses
-system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.017645 # Average number of messages in buffer
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-system.ruby.network.routers0.percent_links_utilized 8.823722
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-system.ruby.network.routers0.msg_bytes.Data::2 1011312
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-system.ruby.network.routers1.msg_count.Control::2 14050
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-system.ruby.network.routers1.msg_bytes.Data::2 1011312
-system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368
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-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.017645 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 3.997493 # Average number of cycles messages are stalled in this MB
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-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 8.823722
-system.ruby.network.routers2.msg_count.Control::2 14050
-system.ruby.network.routers2.msg_count.Data::2 14046
-system.ruby.network.routers2.msg_count.Response_Data::4 14050
-system.ruby.network.routers2.msg_count.Writeback_Control::3 14046
-system.ruby.network.routers2.msg_bytes.Control::2 112400
-system.ruby.network.routers2.msg_bytes.Data::2 1011312
-system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 42150
-system.ruby.network.msg_count.Data 42138
-system.ruby.network.msg_count.Response_Data 42150
-system.ruby.network.msg_count.Writeback_Control 42138
-system.ruby.network.msg_byte.Control 337200
-system.ruby.network.msg_byte.Data 3033936
-system.ruby.network.msg_byte.Response_Data 3034800
-system.ruby.network.msg_byte.Writeback_Control 337104
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 8.824727
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368
-system.ruby.network.routers0.throttle1.link_utilization 8.822717
-system.ruby.network.routers0.throttle1.msg_count.Control::2 14050
-system.ruby.network.routers0.throttle1.msg_count.Data::2 14046
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312
-system.ruby.network.routers1.throttle0.link_utilization 8.822717
-system.ruby.network.routers1.throttle0.msg_count.Control::2 14050
-system.ruby.network.routers1.throttle0.msg_count.Data::2 14046
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312
-system.ruby.network.routers1.throttle1.link_utilization 8.824727
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368
-system.ruby.network.routers2.throttle0.link_utilization 8.824727
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368
-system.ruby.network.routers2.throttle1.link_utilization 8.822717
-system.ruby.network.routers2.throttle1.msg_count.Control::2 14050
-system.ruby.network.routers2.throttle1.msg_count.Data::2 14046
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312
-system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2
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+system.ruby.miss_latency_hist_seqr::gmean 47.226043
+system.ruby.miss_latency_hist_seqr::stdev 36.253574
+system.ruby.miss_latency_hist_seqr | 16263 57.25% 57.25% | 11341 39.92% 97.18% | 523 1.84% 99.02% | 82 0.29% 99.31% | 110 0.39% 99.69% | 70 0.25% 99.94% | 5 0.02% 99.96% | 2 0.01% 99.96% | 0 0.00% 99.96% | 10 0.04% 100.00%
+system.ruby.miss_latency_hist_seqr::total 28406
+system.ruby.Directory.incomplete_times_seqr 28405
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+system.ruby.l1_cntrl0.cacheMemory.demand_hits 150771
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+system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999999
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+system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999997
+system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015256
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+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1861905
+system.ruby.memctrl_clk_domain.clock 3
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+system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755204
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1861905
+system.ruby.network.routers0.percent_links_utilized 7.627672
+system.ruby.network.routers0.msg_count.Control::2 28406
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+system.ruby.network.routers0.msg_count.Response_Data::4 28406
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+system.ruby.network.routers0.msg_bytes.Control::2 227248
+system.ruby.network.routers0.msg_bytes.Data::2 2044944
+system.ruby.network.routers0.msg_bytes.Response_Data::4 2045232
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 227216
+system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030511
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+system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.miss_latency_hist_seqr::total 5
+system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.latency_hist_seqr::samples 276
+system.ruby.Store_Conditional.latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 276 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.latency_hist_seqr::total 276
+system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 276
+system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 276 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.hit_latency_hist_seqr::total 276
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722
-system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 28406
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.930754
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.226043
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.253574
+system.ruby.Directory.miss_mach_latency_hist_seqr | 16263 57.25% 57.25% | 11341 39.92% 97.18% | 523 1.84% 99.02% | 82 0.29% 99.31% | 110 0.39% 99.69% | 70 0.25% 99.94% | 5 0.02% 99.96% | 2 0.01% 99.96% | 0 0.00% 99.96% | 10 0.04% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 28406
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 12392
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.915349
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.325075
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.201666
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7402 59.73% 59.73% | 4640 37.44% 97.18% | 239 1.93% 99.10% | 35 0.28% 99.39% | 45 0.36% 99.75% | 25 0.20% 99.95% | 3 0.02% 99.98% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 12392
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5633
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.495473
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.095323
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.999863
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4415 78.38% 78.38% | 1128 20.02% 98.40% | 65 1.15% 99.56% | 4 0.07% 99.63% | 8 0.14% 99.77% | 8 0.14% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5633
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825
-system.ruby.Directory_Controller.GETX 14050 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 10376
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 60.809079
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 53.543726
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.587150
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4444 42.83% 42.83% | 5570 53.68% 96.51% | 219 2.11% 98.62% | 43 0.41% 99.04% | 57 0.55% 99.59% | 37 0.36% 99.94% | 2 0.02% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.04% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 10376
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 5
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 53
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 49.854558
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 19.170290
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 5
+system.ruby.Directory_Controller.GETX 28406 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 28402 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 28406 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 28402 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 28406 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 28402 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 28406 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 28402 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 25321 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 136903 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 16953 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 28406 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 28402 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 28402 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 12392 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 10376 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 5638 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 12929 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 126527 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 11315 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 28402 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 28402 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 22768 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 5638 0.00% 0.00%
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:30
-gem5 executing on zizzer, pid 34063
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1346
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-lr.w/sc.w: \e[1;31mFAIL\e[0m (expected (-1, 0); found (-1, 1))
-Exiting @ tick 138549500 because target called exit()
+lr.w/sc.w: PASS
+sc.w, no preceding lr.d: PASS
+amoswap.w: PASS
+amoswap.w, sign extend: PASS
+amoswap.w, truncate: PASS
+amoadd.w: PASS
+amoadd.w, truncate/overflow: PASS
+amoadd.w, sign extend: PASS
+amoxor.w, truncate: PASS
+amoxor.w, sign extend: PASS
+amoand.w, truncate: PASS
+amoand.w, sign extend: PASS
+amoor.w, truncate: PASS
+amoor.w, sign extend: PASS
+amomin.w, truncate: PASS
+amomin.w, sign extend: PASS
+amomax.w, truncate: PASS
+amomax.w, sign extend: PASS
+amominu.w, truncate: PASS
+amominu.w, sign extend: PASS
+amomaxu.w, truncate: PASS
+amomaxu.w, sign extend: PASS
+lr.d/sc.d: PASS
+sc.d, no preceding lr.d: PASS
+amoswap.d: PASS
+amoadd.d: PASS
+amoadd.d, overflow: PASS
+amoxor.d (1): PASS
+amoxor.d (0): PASS
+amoand.d: PASS
+amoor.d: PASS
+amomin.d: PASS
+amomax.d: PASS
+amominu.d: PASS
+amomaxu.d: PASS
+Exiting @ tick 250490500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000139 # Number of seconds simulated
-sim_ticks 138549500 # Number of ticks simulated
-final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 338688 # Simulator instruction rate (inst/s)
-host_op_rate 338651 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 708977788 # Simulator tick rate (ticks/s)
-host_mem_usage 242940 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
-sim_insts 66173 # Number of instructions simulated
-sim_ops 66173 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory
-system.physmem.bytes_read::total 49664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 776 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 9 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 277099 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 66173 # Number of instructions committed
-system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 5169 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
-system.cpu.num_int_insts 66174 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
-system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 24255 # number of memory refs
-system.cpu.num_load_insts 11810 # Number of load instructions
-system.cpu.num_store_insts 12445 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 277099 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 15480 # Number of branches fetched
-system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
-system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
-system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction
-system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
-system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 66183 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits
-system.cpu.dcache.overall_hits::total 24001 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses
-system.cpu.dcache.overall_misses::total 251 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004319 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016073 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016073 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.010350 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.010350 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 10 # number of replacements
-system.cpu.icache.tags.tagsinuse 190.684855 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 65659 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 125.064762 # Average number of references to valid blocks.
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-system.cpu.icache.tags.occ_blocks::cpu.inst 190.684855 # Average occupied blocks per requestor
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-system.cpu.icache.tags.occ_percent::total 0.093108 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 515 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.251465 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 132893 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 132893 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 65659 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 65659 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 65659 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 65659 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 65659 # number of overall hits
-system.cpu.icache.overall_hits::total 65659 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 525 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 525 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 525 # number of overall misses
-system.cpu.icache.overall_misses::total 525 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 33076500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 33076500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 33076500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 33076500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 66184 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 66184 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 66184 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 66184 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 66184 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 66184 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.857143 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 63002.857143 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 63002.857143 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 63002.857143 # average overall miss latency
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-system.cpu.icache.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 525 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 32551500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32551500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 32551500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32551500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 32551500 # number of overall MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_rate::total 0.007932 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.007932 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.857143 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.857143 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 386.887852 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 776 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.012887 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.808508 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 195.079344 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.023682 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 7064 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 7064 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 200 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 200 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 525 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 525 # number of ReadCleanReq misses
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+system.cpu.toL2Bus.snoop_filter.hit_single_requests 38
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+system.cpu.toL2Bus.trans_dist::ReadResp 924
+system.cpu.toL2Bus.trans_dist::WritebackClean 38
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+system.cpu.toL2Bus.trans_dist::ReadExResp 227
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 689
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 235
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1416
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 924
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+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29568
+system.cpu.toL2Bus.pkt_size::total 76096
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1151
+system.cpu.toL2Bus.snoop_fanout::mean 0
+system.cpu.toL2Bus.snoop_fanout::stdev 0
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1151 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 0
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+system.cpu.toL2Bus.reqLayer0.occupancy 632500
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 1033500
+system.cpu.toL2Bus.respLayer0.utilization 0.4
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+system.cpu.toL2Bus.respLayer1.utilization 0.3
+system.membus.snoop_filter.tot_requests 1150
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+system.membus.snoop_filter.hit_multi_requests 0
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+system.membus.pwrStateResidencyTicks::UNDEFINED 250490500
+system.membus.trans_dist::ReadResp 923
+system.membus.trans_dist::ReadExReq 227
+system.membus.trans_dist::ReadExResp 227
+system.membus.trans_dist::ReadSharedReq 923
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2300
+system.membus.pkt_count::total 2300
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73600
+system.membus.pkt_size::total 73600
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1150
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1150 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1150
+system.membus.reqLayer0.occupancy 1151000
+system.membus.reqLayer0.utilization 0.5
+system.membus.respLayer1.occupancy 5750000
+system.membus.respLayer1.utilization 2.3
---------- End Simulation Statistics ----------
--- /dev/null
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+opClass=MemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
+type=MinorOpClass
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+opClass=MemWrite
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemRead
+
+[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3]
+type=MinorOpClass
+eventq_index=0
+opClass=FloatMemWrite
+
+[system.cpu.executeFuncUnits.funcUnits5.timings]
+type=MinorFUTiming
+children=opClasses
+description=Mem
+eventq_index=0
+extraAssumedLat=2
+extraCommitLat=0
+extraCommitLatExpr=Null
+mask=0
+match=0
+opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
+srcRegsRelativeLats=1
+suppress=false
+
+[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
+type=MinorOpClassSet
+eventq_index=0
+opClasses=
+
+[system.cpu.executeFuncUnits.funcUnits6]
+type=MinorFU
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+cantForwardFromFUIndices=
+eventq_index=0
+issueLat=1
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
+opLat=1
+timings=
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses]
+type=MinorOpClassSet
+children=opClasses0 opClasses1
+eventq_index=0
+opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
+type=MinorOpClass
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+opClass=IprAccess
+
+[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
+type=MinorOpClass
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+opClass=InstPrefetch
+
+[system.cpu.icache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
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+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
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+default_p_state=UNDEFINED
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+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
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+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
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+default_p_state=UNDEFINED
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+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.038000
+IDD3P12=0.000000
+IDD4R=0.157000
+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
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+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
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+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
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+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1000,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.157",
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+ "tRTP": 7500,
+ "IDD4W": "0.125",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "power_model": null,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 6000,
+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
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+ "do_statistics_insts": true,
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+ "fetch1LineSnapWidth": 0,
+ "fetch1ToFetch2BackwardDelay": 1,
+ "fetch1FetchLimit": 1,
+ "executeIssueLimit": 2,
+ "system": "system",
+ "executeLSQMaxStoreBufferStoresPerCycle": 2,
+ "icache": {
+ "cpu_side": {
+ "peer": "system.cpu.icache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 131072,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": true,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 131072,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "decodeInputWidth": 2,
+ "cxx_class": "MinorCPU",
+ "max_loads_all_threads": 0,
+ "executeMemoryIssueLimit": 1,
+ "decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
+ "max_loads_any_thread": 0,
+ "executeLSQTransfersQueueSize": 2,
+ "p_state_clk_gate_max": 1000000000000,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "executeMemoryWidth": 0,
+ "default_p_state": "UNDEFINED",
+ "executeBranchDelay": 1,
+ "executeMemoryCommitLimit": 1,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 2097152,
+ "tag_latency": 20,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "do_quiesce": true,
+ "type": "MinorCPU",
+ "executeCycleInput": true,
+ "executeAllowEarlyMemoryIssue": true,
+ "executeInputBufferSize": 7,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "socket_id": 0,
+ "progress_interval": 0,
+ "p_state_clk_gate_min": 1000,
+ "toL2Bus": {
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+ "indirectPathLength": 3,
+ "globalCtrBits": 2,
+ "choicePredictorSize": 8192,
+ "indirectHashGHR": true,
+ "eventq_index": 0,
+ "localHistoryTableSize": 2048,
+ "type": "TournamentBP",
+ "indirectSets": 256,
+ "indirectWays": 2,
+ "choiceCtrBits": 2,
+ "useIndirect": true,
+ "localCtrBits": 2,
+ "path": "system.cpu.branchPred",
+ "localPredictorSize": 2048,
+ "RASSize": 16,
+ "globalPredictorSize": 8192,
+ "name": "branchPred",
+ "indirectHashTargets": true,
+ "instShiftAmt": 2,
+ "indirectTagSize": 16,
+ "BTBTagSize": 16
+ },
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 262144,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "path": "system.cpu",
+ "fetch1ToFetch2ForwardDelay": 1,
+ "decodeInputBufferSize": 3
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6004
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/minor-timing
+
+Global frequency set at 1000000000000 ticks per second
+c.lwsp: PASS
+c.ldsp: PASS
+c.fldsp: PASS
+c.swsp: PASS
+c.sdsp: PASS
+c.fsdsp: PASS
+c.lw, positive: PASS
+c.lw, negative: PASS
+c.ld: PASS
+c.fld: PASS
+c.sw: PASS
+c.sd: PASS
+c.fsd: PASS
+c.j: PASS
+c.jr: PASS
+c.jalr: PASS
+c.beqz, zero: PASS
+c.beqz, not zero: PASS
+c.bnez, not zero: PASS
+c.bnez, zero: PASS
+c.li: PASS
+c.li, sign extend: PASS
+c.lui: PASS
+c.addi: PASS
+c.addiw: PASS
+c.addiw, overflow: PASS
+c.addiw, truncate: PASS
+c.addi16sp: PASS
+c.addi4spn: PASS
+c.slli: PASS
+c.slli, overflow: PASS
+c.srli: PASS
+c.srli, overflow: PASS
+c.srli, -1: PASS
+c.srai: PASS
+c.srai, overflow: PASS
+c.srai, -1: PASS
+c.andi (0): PASS
+c.andi (1): PASS
+c.mv: PASS
+c.add: PASS
+c.and (0): PASS
+c.and (-1): PASS
+c.or (1): PASS
+c.or (A): PASS
+c.xor (1): PASS
+c.xor (0): PASS
+c.sub: PASS
+c.addw: PASS
+c.addw, overflow: PASS
+c.addw, truncate: PASS
+c.subw: PASS
+c.subw, "overflow": PASS
+c.subw, truncate: PASS
+Exiting @ tick 196383500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000196
+sim_ticks 196383500
+final_tick 196383500
+sim_freq 1000000000000
+host_inst_rate 4107
+host_op_rate 4117
+host_tick_rate 6138676
+host_mem_usage 272768
+host_seconds 31.99
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+sim_ops 131710
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 196383500
+system.physmem.bytes_read::cpu.inst 63296
+system.physmem.bytes_read::cpu.data 29824
+system.physmem.bytes_read::total 93120
+system.physmem.bytes_inst_read::cpu.inst 63296
+system.physmem.bytes_inst_read::total 63296
+system.physmem.num_reads::cpu.inst 989
+system.physmem.num_reads::cpu.data 466
+system.physmem.num_reads::total 1455
+system.physmem.bw_read::cpu.inst 322308136
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+system.physmem.bw_inst_read::total 322308136
+system.physmem.bw_total::cpu.inst 322308136
+system.physmem.bw_total::cpu.data 151866119
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+system.physmem.readReqs 1455
+system.physmem.writeReqs 0
+system.physmem.readBursts 1455
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 93120
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 93120
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
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+system.cpu_clk_domain.clock 500
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+system.cpu.op_class_0::IntDiv 4 0.00% 60.62%
+system.cpu.op_class_0::FloatAdd 2 0.00% 60.63%
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+system.cpu.op_class_0::FloatCvt 2 0.00% 60.63%
+system.cpu.op_class_0::FloatMult 0 0.00% 60.63%
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+system.cpu.op_class_0::FloatDiv 0 0.00% 60.63%
+system.cpu.op_class_0::FloatMisc 0 0.00% 60.63%
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+system.cpu.op_class_0::SimdAdd 0 0.00% 60.63%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdAlu 0 0.00% 60.63%
+system.cpu.op_class_0::SimdCmp 0 0.00% 60.63%
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+system.cpu.op_class_0::SimdMisc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdMult 0 0.00% 60.63%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdShift 0 0.00% 60.63%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.63%
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.63%
+system.cpu.op_class_0::MemRead 31653 24.03% 84.66%
+system.cpu.op_class_0::MemWrite 20162 15.30% 99.97%
+system.cpu.op_class_0::FloatMemRead 14 0.01% 99.98%
+system.cpu.op_class_0::FloatMemWrite 19 0.01% 99.99%
+system.cpu.op_class_0::IprAccess 0 0.00% 99.99%
+system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99%
+system.cpu.op_class_0::total 131710
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+system.cpu.dcache.tags.replacements 0
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72686.126373
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72032.828282
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74074.034334
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72686.126373
+system.cpu.toL2Bus.snoop_filter.tot_requests 1564
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 97
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 196383500
+system.cpu.toL2Bus.trans_dist::ReadResp 1246
+system.cpu.toL2Bus.trans_dist::WritebackClean 96
+system.cpu.toL2Bus.trans_dist::ReadExReq 221
+system.cpu.toL2Bus.trans_dist::ReadExResp 221
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1001
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 246
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2097
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 934
+system.cpu.toL2Bus.pkt_count::total 3031
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70144
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29888
+system.cpu.toL2Bus.pkt_size::total 100032
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1468
+system.cpu.toL2Bus.snoop_fanout::mean 0.000681
+system.cpu.toL2Bus.snoop_fanout::stdev 0.026099
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1467 99.93% 99.93%
+system.cpu.toL2Bus.snoop_fanout::1 1 0.06% 99.99%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 1468
+system.cpu.toL2Bus.reqLayer0.occupancy 878000
+system.cpu.toL2Bus.reqLayer0.utilization 0.4
+system.cpu.toL2Bus.respLayer0.occupancy 1500000
+system.cpu.toL2Bus.respLayer0.utilization 0.7
+system.cpu.toL2Bus.respLayer1.occupancy 700500
+system.cpu.toL2Bus.respLayer1.utilization 0.3
+system.membus.snoop_filter.tot_requests 1455
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 196383500
+system.membus.trans_dist::ReadResp 1234
+system.membus.trans_dist::ReadExReq 221
+system.membus.trans_dist::ReadExResp 221
+system.membus.trans_dist::ReadSharedReq 1234
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2910
+system.membus.pkt_count::total 2910
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 93120
+system.membus.pkt_size::total 93120
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1455
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1455 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1455
+system.membus.reqLayer0.occupancy 1688000
+system.membus.reqLayer0.utilization 0.8
+system.membus.respLayer1.occupancy 7746500
+system.membus.respLayer1.utilization 3.9
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=DerivO3CPU
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu.branchPred
+cacheStorePorts=200
+checker=Null
+clk_domain=system.cpu_clk_domain
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+default_p_state=UNDEFINED
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
+fetchQueueSize=32
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysCCRegs=0
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numPhysVecRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wait_for_remote_gdb=false
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=TournamentBP
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+useIndirect=true
+
+[system.cpu.dcache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=262144
+tag_latency=2
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+eventq_index=0
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+eventq_index=0
+opClass=IntAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+eventq_index=0
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+eventq_index=0
+opClass=IntMult
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+eventq_index=0
+opClass=IntDiv
+opLat=20
+pipelined=false
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+eventq_index=0
+opClass=FloatAdd
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatCmp
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatCvt
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2 opList3 opList4
+count=2
+eventq_index=0
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+eventq_index=0
+opClass=FloatMult
+opLat=4
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatDiv
+opLat=12
+pipelined=false
+
+[system.cpu.fuPool.FUList3.opList4]
+type=OpDesc
+eventq_index=0
+opClass=FloatSqrt
+opLat=24
+pipelined=false
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0 opList1
+count=0
+eventq_index=0
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+eventq_index=0
+opClass=SimdAdd
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+eventq_index=0
+opClass=SimdAddAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+eventq_index=0
+opClass=SimdAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+eventq_index=0
+opClass=SimdCmp
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+eventq_index=0
+opClass=SimdCvt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+eventq_index=0
+opClass=SimdMisc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+eventq_index=0
+opClass=SimdMult
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+eventq_index=0
+opClass=SimdMultAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+eventq_index=0
+opClass=SimdShift
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+eventq_index=0
+opClass=SimdShiftAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+eventq_index=0
+opClass=SimdSqrt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatAdd
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatCmp
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatCvt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatDiv
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMisc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMult
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMultAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatSqrt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=0
+eventq_index=0
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1 opList2 opList3
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+eventq_index=0
+opClass=MemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+eventq_index=0
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+eventq_index=0
+opClass=IprAccess
+opLat=3
+pipelined=false
+
+[system.cpu.icache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
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+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
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+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
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+default_p_state=UNDEFINED
+demand_mshr_reserve=1
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+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.038000
+IDD3P12=0.000000
+IDD4R=0.157000
+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1000,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.157",
+ "burst_length": 8,
+ "tRTP": 7500,
+ "IDD4W": "0.125",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "power_model": null,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 6000,
+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
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+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "SQEntries": 32,
+ "smtLSQThreshold": 100,
+ "fetchTrapLatency": 1,
+ "iewToRenameDelay": 1,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
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+ "system": "system",
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+ "response_latency": 20,
+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
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+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
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+ "tag_latency": 20,
+ "name": "tags",
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+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
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+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "fetchWidth": 8,
+ "max_loads_all_threads": 0,
+ "cpu_id": 0,
+ "fetchToDecodeDelay": 1,
+ "renameToDecodeDelay": 1,
+ "do_quiesce": true,
+ "renameToROBDelay": 1,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "decodeWidth": 8,
+ "commitToFetchDelay": 1,
+ "needsTSO": false,
+ "smtIQThreshold": 100,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "SSITSize": 1024,
+ "activity": 0,
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ },
+ "decodeToFetchDelay": 1,
+ "renameWidth": 8,
+ "numThreads": 1,
+ "syscallRetryLatency": 10000,
+ "squashWidth": 8,
+ "function_trace": false,
+ "backComSize": 5,
+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
+ "point_of_coherency": false,
+ "system": "system",
+ "response_latency": 1,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "p_state_clk_gate_min": 1000,
+ "fuPool": {
+ "name": "fuPool",
+ "FUList": [
+ {
+ "count": 6,
+ "opList": [
+ {
+ "opClass": "IntAlu",
+ "opLat": 1,
+ "name": "opList",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList0.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList0",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList0",
+ "type": "FUDesc"
+ },
+ {
+ "count": 2,
+ "opList": [
+ {
+ "opClass": "IntMult",
+ "opLat": 3,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList1.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "IntDiv",
+ "opLat": 20,
+ "name": "opList1",
+ "pipelined": false,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList1.opList1",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList1",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList1",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "opClass": "FloatAdd",
+ "opLat": 2,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatCmp",
+ "opLat": 2,
+ "name": "opList1",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatCvt",
+ "opLat": 2,
+ "name": "opList2",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList2",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList2",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList2",
+ "type": "FUDesc"
+ },
+ {
+ "count": 2,
+ "opList": [
+ {
+ "opClass": "FloatMult",
+ "opLat": 4,
+ "name": "opList0",
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+ },
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+ "cxx_class": "LRU",
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+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
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+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
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+ "tag_latency": 2,
+ "name": "icache",
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+ "sequential_access": false,
+ "assoc": 2
+ },
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+ "switched_out": false,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "smtROBThreshold": 100,
+ "numIQEntries": 64,
+ "branchPred": {
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+ "BTBEntries": 4096,
+ "cxx_class": "TournamentBP",
+ "indirectPathLength": 3,
+ "globalCtrBits": 2,
+ "choicePredictorSize": 8192,
+ "indirectHashGHR": true,
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+ "type": "TournamentBP",
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+ "indirectWays": 2,
+ "choiceCtrBits": 2,
+ "useIndirect": true,
+ "localCtrBits": 2,
+ "path": "system.cpu.branchPred",
+ "localPredictorSize": 2048,
+ "RASSize": 16,
+ "globalPredictorSize": 8192,
+ "name": "branchPred",
+ "indirectHashTargets": true,
+ "instShiftAmt": 2,
+ "indirectTagSize": 16,
+ "BTBTagSize": 16
+ },
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
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+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
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+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 262144,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "numPhysVecRegs": 256,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "smtCommitPolicy": "RoundRobin",
+ "issueToExecuteDelay": 1,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
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+ "fetchQueueSize": 32,
+ "iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 0,
+ "renameToIEWDelay": 2,
+ "p_state_clk_gate_bins": 20,
+ "progress_interval": 0,
+ "LQEntries": 32
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6007
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/o3-timing
+
+Global frequency set at 1000000000000 ticks per second
+c.lwsp: PASS
+c.ldsp: PASS
+c.fldsp: PASS
+c.swsp: PASS
+c.sdsp: PASS
+c.fsdsp: PASS
+c.lw, positive: PASS
+c.lw, negative: PASS
+c.ld: PASS
+c.fld: PASS
+c.sw: PASS
+c.sd: PASS
+c.fsd: PASS
+c.j: PASS
+c.jr: PASS
+c.jalr: PASS
+c.beqz, zero: PASS
+c.beqz, not zero: PASS
+c.bnez, not zero: PASS
+c.bnez, zero: PASS
+c.li: PASS
+c.li, sign extend: PASS
+c.lui: PASS
+c.addi: PASS
+c.addiw: PASS
+c.addiw, overflow: PASS
+c.addiw, truncate: PASS
+c.addi16sp: PASS
+c.addi4spn: PASS
+c.slli: PASS
+c.slli, overflow: PASS
+c.srli: PASS
+c.srli, overflow: PASS
+c.srli, -1: PASS
+c.srai: PASS
+c.srai, overflow: PASS
+c.srai, -1: PASS
+c.andi (0): PASS
+c.andi (1): PASS
+c.mv: PASS
+c.add: PASS
+c.and (0): PASS
+c.and (-1): PASS
+c.or (1): PASS
+c.or (A): PASS
+c.xor (1): PASS
+c.xor (0): PASS
+c.sub: PASS
+c.addw: PASS
+c.addw, overflow: PASS
+c.addw, truncate: PASS
+c.subw: PASS
+c.subw, "overflow": PASS
+c.subw, truncate: PASS
+Exiting @ tick 141034000 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000141
+sim_ticks 141034000
+final_tick 141034000
+sim_freq 1000000000000
+host_inst_rate 4027
+host_op_rate 4036
+host_tick_rate 4324346
+host_mem_usage 272260
+host_seconds 32.61
+sim_insts 131348
+sim_ops 131648
+system.voltage_domain.voltage 1
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+system.membus.snoop_filter.hit_multi_requests 0
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+system.membus.trans_dist::ReadExReq 216
+system.membus.trans_dist::ReadExResp 216
+system.membus.trans_dist::ReadSharedReq 1147
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+system.membus.pkt_count::total 2726
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 87232
+system.membus.pkt_size::total 87232
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1363
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1363 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1363
+system.membus.reqLayer0.occupancy 1668500
+system.membus.reqLayer0.utilization 1.1
+system.membus.respLayer1.occupancy 7241500
+system.membus.respLayer1.utilization 5.1
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
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+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
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+mem_ranges=
+memories=system.physmem
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+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
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+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
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+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:134217727:0:0:0:0
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.icache_port",
+ "system.cpu.dcache_port"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "range": "0:134217727:0:0:0:0",
+ "latency": 30000,
+ "name": "physmem",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "kvm_map": true,
+ "clk_domain": "system.clk_domain",
+ "power_model": null,
+ "latency_var": 0,
+ "bandwidth": "73.000000",
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.physmem",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "atomic",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simulate_data_stalls": false,
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "AtomicSimpleCPU",
+ "max_loads_all_threads": 0,
+ "system": "system",
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "width": 1,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "do_quiesce": true,
+ "type": "AtomicSimpleCPU",
+ "fastmem": false,
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "simulate_inst_stalls": false,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6005
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-atomic
+
+Global frequency set at 1000000000000 ticks per second
+c.lwsp: PASS
+c.ldsp: PASS
+c.fldsp: PASS
+c.swsp: PASS
+c.sdsp: PASS
+c.fsdsp: PASS
+c.lw, positive: PASS
+c.lw, negative: PASS
+c.ld: PASS
+c.fld: PASS
+c.sw: PASS
+c.sd: PASS
+c.fsd: PASS
+c.j: PASS
+c.jr: PASS
+c.jalr: PASS
+c.beqz, zero: PASS
+c.beqz, not zero: PASS
+c.bnez, not zero: PASS
+c.bnez, zero: PASS
+c.li: PASS
+c.li, sign extend: PASS
+c.lui: PASS
+c.addi: PASS
+c.addiw: PASS
+c.addiw, overflow: PASS
+c.addiw, truncate: PASS
+c.addi16sp: PASS
+c.addi4spn: PASS
+c.slli: PASS
+c.slli, overflow: PASS
+c.srli: PASS
+c.srli, overflow: PASS
+c.srli, -1: PASS
+c.srai: PASS
+c.srai, overflow: PASS
+c.srai, -1: PASS
+c.andi (0): PASS
+c.andi (1): PASS
+c.mv: PASS
+c.add: PASS
+c.and (0): PASS
+c.and (-1): PASS
+c.or (1): PASS
+c.or (A): PASS
+c.xor (1): PASS
+c.xor (0): PASS
+c.sub: PASS
+c.addw: PASS
+c.addw, overflow: PASS
+c.addw, truncate: PASS
+c.subw: PASS
+c.subw, "overflow": PASS
+c.subw, truncate: PASS
+Exiting @ tick 76505000 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000076
+sim_ticks 76505000
+final_tick 76505000
+sim_freq 1000000000000
+host_inst_rate 4162
+host_op_rate 4172
+host_tick_rate 2424659
+host_mem_usage 259192
+host_seconds 31.55
+sim_insts 131348
+sim_ops 131648
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 76505000
+system.physmem.bytes_read::cpu.inst 610844
+system.physmem.bytes_read::cpu.data 214914
+system.physmem.bytes_read::total 825758
+system.physmem.bytes_inst_read::cpu.inst 610844
+system.physmem.bytes_inst_read::total 610844
+system.physmem.bytes_written::cpu.data 137066
+system.physmem.bytes_written::total 137066
+system.physmem.num_reads::cpu.inst 152711
+system.physmem.num_reads::cpu.data 31667
+system.physmem.num_reads::total 184378
+system.physmem.num_writes::cpu.data 20181
+system.physmem.num_writes::total 20181
+system.physmem.bw_read::cpu.inst 7984367034
+system.physmem.bw_read::cpu.data 2809149728
+system.physmem.bw_read::total 10793516763
+system.physmem.bw_inst_read::cpu.inst 7984367034
+system.physmem.bw_inst_read::total 7984367034
+system.physmem.bw_write::cpu.data 1791595320
+system.physmem.bw_write::total 1791595320
+system.physmem.bw_total::cpu.inst 7984367034
+system.physmem.bw_total::cpu.data 4600745049
+system.physmem.bw_total::total 12585112084
+system.pwrStateResidencyTicks::UNDEFINED 76505000
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 62
+system.cpu.pwrStateResidencyTicks::ON 76505000
+system.cpu.numCycles 153011
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 131348
+system.cpu.committedOps 131648
+system.cpu.num_int_alu_accesses 130924
+system.cpu.num_fp_alu_accesses 40
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 7702
+system.cpu.num_conditional_control_insts 21044
+system.cpu.num_int_insts 130924
+system.cpu.num_fp_insts 40
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 163963
+system.cpu.num_int_register_writes 87008
+system.cpu.num_fp_register_reads 31
+system.cpu.num_fp_register_writes 16
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 51848
+system.cpu.num_load_insts 31667
+system.cpu.num_store_insts 20181
+system.cpu.num_idle_cycles -0
+system.cpu.num_busy_cycles 153011
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction -0
+system.cpu.Branches 28746
+system.cpu.op_class::No_OpClass 66 0.05% 0.05%
+system.cpu.op_class::IntAlu 79621 60.45% 60.50%
+system.cpu.op_class::IntMult 164 0.12% 60.62%
+system.cpu.op_class::IntDiv 4 0.00% 60.62%
+system.cpu.op_class::FloatAdd 2 0.00% 60.63%
+system.cpu.op_class::FloatCmp 3 0.00% 60.63%
+system.cpu.op_class::FloatCvt 2 0.00% 60.63%
+system.cpu.op_class::FloatMult 0 0.00% 60.63%
+system.cpu.op_class::FloatMultAcc 0 0.00% 60.63%
+system.cpu.op_class::FloatDiv 0 0.00% 60.63%
+system.cpu.op_class::FloatMisc 0 0.00% 60.63%
+system.cpu.op_class::FloatSqrt 0 0.00% 60.63%
+system.cpu.op_class::SimdAdd 0 0.00% 60.63%
+system.cpu.op_class::SimdAddAcc 0 0.00% 60.63%
+system.cpu.op_class::SimdAlu 0 0.00% 60.63%
+system.cpu.op_class::SimdCmp 0 0.00% 60.63%
+system.cpu.op_class::SimdCvt 0 0.00% 60.63%
+system.cpu.op_class::SimdMisc 0 0.00% 60.63%
+system.cpu.op_class::SimdMult 0 0.00% 60.63%
+system.cpu.op_class::SimdMultAcc 0 0.00% 60.63%
+system.cpu.op_class::SimdShift 0 0.00% 60.63%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 60.63%
+system.cpu.op_class::SimdSqrt 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatMult 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.63%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.63%
+system.cpu.op_class::MemRead 31653 24.03% 84.66%
+system.cpu.op_class::MemWrite 20162 15.30% 99.97%
+system.cpu.op_class::FloatMemRead 14 0.01% 99.98%
+system.cpu.op_class::FloatMemWrite 19 0.01% 99.99%
+system.cpu.op_class::IprAccess 0 0.00% 99.99%
+system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
+system.cpu.op_class::total 131710
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 76505000
+system.membus.trans_dist::ReadReq 184044
+system.membus.trans_dist::ReadResp 184378
+system.membus.trans_dist::WriteReq 19847
+system.membus.trans_dist::WriteResp 19847
+system.membus.trans_dist::LoadLockedReq 334
+system.membus.trans_dist::StoreCondReq 334
+system.membus.trans_dist::StoreCondResp 334
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 305422
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 103696
+system.membus.pkt_count::total 409118
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 610844
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 351980
+system.membus.pkt_size::total 962824
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 204559
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 204559 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 204559
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=0:268435455:0:0:0:0
+memories=system.mem_ctrls
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=clk_domain dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu.clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+workload=system.cpu.workload
+dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
+icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
+
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000
+
+[system.mem_ctrls]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.038000
+IDD3P12=0.000000
+IDD4R=0.157000
+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
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--- /dev/null
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+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers06",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers07",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers07",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers08",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers08",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers09",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers09",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers10",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers10",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers11",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers11",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers12",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers12",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers13",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers13",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers14",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers14",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers15",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers15",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers16",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers16",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers17",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers17",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers18",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers18",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers19",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers19",
+ "type": "MessageBuffer"
+ }
+ ]
+ }
+ ],
+ "power_model": null,
+ "netifs": [],
+ "control_msg_size": 8,
+ "buffer_size": 0,
+ "endpoint_bandwidth": 1000,
+ "ruby_system": "system.ruby",
+ "name": "network",
+ "p_state_clk_gate_bins": 20,
+ "ext_links": [
+ {
+ "latency": 1,
+ "name": "ext_links0",
+ "weight": 1,
+ "ext_node": "system.ruby.l1_cntrl0",
+ "link_id": 0,
+ "eventq_index": 0,
+ "cxx_class": "SimpleExtLink",
+ "path": "system.ruby.network.ext_links0",
+ "int_node": "system.ruby.network.routers0",
+ "type": "SimpleExtLink",
+ "bandwidth_factor": 16
+ },
+ {
+ "latency": 1,
+ "name": "ext_links1",
+ "weight": 1,
+ "ext_node": "system.ruby.dir_cntrl0",
+ "link_id": 1,
+ "eventq_index": 0,
+ "cxx_class": "SimpleExtLink",
+ "path": "system.ruby.network.ext_links1",
+ "int_node": "system.ruby.network.routers1",
+ "type": "SimpleExtLink",
+ "bandwidth_factor": 16
+ }
+ ],
+ "number_of_virtual_networks": 5,
+ "path": "system.ruby.network"
+ },
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.ruby.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "phys_mem": null,
+ "type": "RubySystem",
+ "p_state_clk_gate_min": 1,
+ "hot_lines": false,
+ "power_model": null,
+ "path": "system.ruby",
+ "memctrl_clk_domain": {
+ "name": "memctrl_clk_domain",
+ "clk_domain": "system.ruby.clk_domain",
+ "eventq_index": 0,
+ "cxx_class": "DerivedClockDomain",
+ "path": "system.ruby.memctrl_clk_domain",
+ "type": "DerivedClockDomain",
+ "clk_divider": 3
+ },
+ "name": "ruby",
+ "p_state_clk_gate_bins": 20,
+ "block_size_bytes": 64,
+ "access_backing_store": false,
+ "number_of_virtual_networks": 5,
+ "num_of_sequencers": 1,
+ "dir_cntrl0": {
+ "system": "system",
+ "cluster_id": 0,
+ "responseFromMemory": {
+ "ordered": false,
+ "name": "responseFromMemory",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.responseFromMemory",
+ "type": "MessageBuffer"
+ },
+ "cxx_class": "Directory_Controller",
+ "forwardFromDir": {
+ "ordered": false,
+ "name": "forwardFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[4]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.forwardFromDir",
+ "type": "MessageBuffer"
+ },
+ "dmaRequestToDir": {
+ "ordered": true,
+ "name": "dmaRequestToDir",
+ "cxx_class": "MessageBuffer",
+ "slave": {
+ "peer": "system.ruby.network.master[3]",
+ "role": "SLAVE"
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.dmaRequestToDir",
+ "type": "MessageBuffer"
+ },
+ "type": "Directory_Controller",
+ "recycle_latency": 10,
+ "clk_domain": "system.ruby.clk_domain",
+ "version": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "directory_latency": 12,
+ "number_of_TBEs": 256,
+ "to_memory_controller_latency": 1,
+ "p_state_clk_gate_min": 1,
+ "responseFromDir": {
+ "ordered": false,
+ "name": "responseFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[2]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.responseFromDir",
+ "type": "MessageBuffer"
+ },
+ "transitions_per_cycle": 32,
+ "memory": {
+ "peer": "system.mem_ctrls.port",
+ "role": "MASTER"
+ },
+ "power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
+ "buffer_size": 0,
+ "ruby_system": "system.ruby",
+ "requestToDir": {
+ "ordered": true,
+ "name": "requestToDir",
+ "cxx_class": "MessageBuffer",
+ "slave": {
+ "peer": "system.ruby.network.master[2]",
+ "role": "SLAVE"
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.requestToDir",
+ "type": "MessageBuffer"
+ },
+ "dmaResponseFromDir": {
+ "ordered": true,
+ "name": "dmaResponseFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[3]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.dmaResponseFromDir",
+ "type": "MessageBuffer"
+ },
+ "name": "dir_cntrl0",
+ "p_state_clk_gate_bins": 20,
+ "directory": {
+ "name": "directory",
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
+ "eventq_index": 0,
+ "cxx_class": "DirectoryMemory",
+ "path": "system.ruby.dir_cntrl0.directory",
+ "type": "RubyDirectoryMemory"
+ },
+ "path": "system.ruby.dir_cntrl0"
+ }
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "system": "system",
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "TimingSimpleCPU",
+ "max_loads_all_threads": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "do_quiesce": true,
+ "type": "TimingSimpleCPU",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ },
+ "multi_thread": false,
+ "mem_ctrls": [
+ {
+ "static_frontend_latency": 10,
+ "tRFC": 260,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 8,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.ruby.dir_cntrl0.memory",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6,
+ "tRTW": 3,
+ "IDD4R": "0.157",
+ "burst_length": 8,
+ "tRTP": 8,
+ "IDD4W": "0.125",
+ "tWR": 15,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 14,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 3,
+ "power_model": null,
+ "tCL": 14,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1,
+ "tRAS": 35,
+ "tRP": 14,
+ "tBURST": 5,
+ "path": "system.mem_ctrls",
+ "tXP": 6,
+ "tXS": 270,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "mem_ctrls",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30,
+ "write_low_thresh_perc": 50,
+ "range": "0:268435455:5:19:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800
+ }
+ ],
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6003
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby
+
+Global frequency set at 1000000000 ticks per second
+c.lwsp: PASS
+c.ldsp: PASS
+c.fldsp: PASS
+c.swsp: PASS
+c.sdsp: PASS
+c.fsdsp: PASS
+c.lw, positive: PASS
+c.lw, negative: PASS
+c.ld: PASS
+c.fld: PASS
+c.sw: PASS
+c.sd: PASS
+c.fsd: PASS
+c.j: PASS
+c.jr: PASS
+c.jalr: PASS
+c.beqz, zero: PASS
+c.beqz, not zero: PASS
+c.bnez, not zero: PASS
+c.bnez, zero: PASS
+c.li: PASS
+c.li, sign extend: PASS
+c.lui: PASS
+c.addi: PASS
+c.addiw: PASS
+c.addiw, overflow: PASS
+c.addiw, truncate: PASS
+c.addi16sp: PASS
+c.addi4spn: PASS
+c.slli: PASS
+c.slli, overflow: PASS
+c.srli: PASS
+c.srli, overflow: PASS
+c.srli, -1: PASS
+c.srai: PASS
+c.srai, overflow: PASS
+c.srai, -1: PASS
+c.andi (0): PASS
+c.andi (1): PASS
+c.mv: PASS
+c.add: PASS
+c.and (0): PASS
+c.and (-1): PASS
+c.or (1): PASS
+c.or (A): PASS
+c.xor (1): PASS
+c.xor (0): PASS
+c.sub: PASS
+c.addw: PASS
+c.addw, overflow: PASS
+c.addw, truncate: PASS
+c.subw: PASS
+c.subw, "overflow": PASS
+c.subw, truncate: PASS
+Exiting @ tick 2280417 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.002280
+sim_ticks 2280417
+final_tick 2280417
+sim_freq 1000000000
+host_inst_rate 4031
+host_op_rate 4040
+host_tick_rate 69995
+host_mem_usage 438656
+host_seconds 32.57
+sim_insts 131348
+sim_ops 131648
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 2280417
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 2256640
+system.mem_ctrls.bytes_read::total 2256640
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 2256384
+system.mem_ctrls.bytes_written::total 2256384
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 35260
+system.mem_ctrls.num_reads::total 35260
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 35256
+system.mem_ctrls.num_writes::total 35256
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 989573398
+system.mem_ctrls.bw_read::total 989573398
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 989461138
+system.mem_ctrls.bw_write::total 989461138
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1979034536
+system.mem_ctrls.bw_total::total 1979034536
+system.mem_ctrls.readReqs 35260
+system.mem_ctrls.writeReqs 35256
+system.mem_ctrls.readBursts 35260
+system.mem_ctrls.writeBursts 35256
+system.mem_ctrls.bytesReadDRAM 1018944
+system.mem_ctrls.bytesReadWrQ 1237696
+system.mem_ctrls.bytesWritten 1071232
+system.mem_ctrls.bytesReadSys 2256640
+system.mem_ctrls.bytesWrittenSys 2256384
+system.mem_ctrls.servicedByWrQ 19339
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+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 15995
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.554360
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.340340
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.955680
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 9424 58.91% 58.91% | 6164 38.53% 97.45% | 288 1.80% 99.25% | 45 0.28% 99.53% | 40 0.25% 99.78% | 30 0.18% 99.97% | 2 0.01% 99.98% | 1 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 15995
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 6175
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.750283
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.834879
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.422439
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4729 76.58% 76.58% | 1320 21.37% 97.95% | 91 1.47% 99.43% | 15 0.24% 99.67% | 8 0.12% 99.80% | 5 0.08% 99.88% | 2 0.03% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 5 0.08% 99.99%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 6175
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13086
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 60.322940
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 53.219754
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.495192
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 5654 43.20% 43.20% | 7004 53.52% 96.72% | 266 2.03% 98.76% | 49 0.37% 99.13% | 66 0.50% 99.64% | 38 0.29% 99.93% | 5 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 4 0.03% 99.99%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13086
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 4
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 58.250000
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 55.698512
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 17.500000
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 4
+system.ruby.Directory_Controller.GETX 35260 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 35256 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 35260 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 35256 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 35260 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 35256 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 35260 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 35256 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 31333 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 152711 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 20515 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 35260 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 35256 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 35256 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 15995 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 13086 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 6179 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 15338 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 139625 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 14336 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 35256 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 35256 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 29081 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 6179 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=262144
+tag_latency=2
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=20
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:134217727:0:0:0:0
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "range": "0:134217727:0:0:0:0",
+ "latency": 30000,
+ "name": "physmem",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "kvm_map": true,
+ "clk_domain": "system.clk_domain",
+ "power_model": null,
+ "latency_var": 0,
+ "bandwidth": "73.000000",
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.physmem",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "system": "system",
+ "icache": {
+ "cpu_side": {
+ "peer": "system.cpu.icache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 131072,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": true,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 131072,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "TimingSimpleCPU",
+ "max_loads_all_threads": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
+ "point_of_coherency": false,
+ "system": "system",
+ "response_latency": 1,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "do_quiesce": true,
+ "type": "TimingSimpleCPU",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 2097152,
+ "tag_latency": 20,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64c/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 262144,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64c/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6010
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64c/simple-timing
+
+Global frequency set at 1000000000000 ticks per second
+c.lwsp: PASS
+c.ldsp: PASS
+c.fldsp: PASS
+c.swsp: PASS
+c.sdsp: PASS
+c.fsdsp: PASS
+c.lw, positive: PASS
+c.lw, negative: PASS
+c.ld: PASS
+c.fld: PASS
+c.sw: PASS
+c.sd: PASS
+c.fsd: PASS
+c.j: PASS
+c.jr: PASS
+c.jalr: PASS
+c.beqz, zero: PASS
+c.beqz, not zero: PASS
+c.bnez, not zero: PASS
+c.bnez, zero: PASS
+c.li: PASS
+c.li, sign extend: PASS
+c.lui: PASS
+c.addi: PASS
+c.addiw: PASS
+c.addiw, overflow: PASS
+c.addiw, truncate: PASS
+c.addi16sp: PASS
+c.addi4spn: PASS
+c.slli: PASS
+c.slli, overflow: PASS
+c.srli: PASS
+c.srli, overflow: PASS
+c.srli, -1: PASS
+c.srai: PASS
+c.srai, overflow: PASS
+c.srai, -1: PASS
+c.andi (0): PASS
+c.andi (1): PASS
+c.mv: PASS
+c.add: PASS
+c.and (0): PASS
+c.and (-1): PASS
+c.or (1): PASS
+c.or (A): PASS
+c.xor (1): PASS
+c.xor (0): PASS
+c.sub: PASS
+c.addw: PASS
+c.addw, overflow: PASS
+c.addw, truncate: PASS
+c.subw: PASS
+c.subw, "overflow": PASS
+c.subw, truncate: PASS
+Exiting @ tick 277930500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
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+final_tick 277930500
+sim_freq 1000000000000
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+system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
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+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 277930500
+system.membus.trans_dist::ReadResp 961
+system.membus.trans_dist::ReadExReq 222
+system.membus.trans_dist::ReadExResp 222
+system.membus.trans_dist::ReadSharedReq 961
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2366
+system.membus.pkt_count::total 2366
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 75712
+system.membus.pkt_size::total 75712
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1183
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1183 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1183
+system.membus.reqLayer0.occupancy 1184000
+system.membus.reqLayer0.utilization 0.4
+system.membus.respLayer1.occupancy 5915000
+system.membus.respLayer1.utilization 2.1
+
+---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:31
-gem5 executing on zizzer, pid 34070
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1350
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 339160000 because target called exit()
+fcvt.w.d, underflow: PASS
+fcvt.w.d, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, -infinity: PASS
+fcvt.w.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.wu.d, truncate positive: PASS
+fcvt.wu.d, truncate negative: PASS
+fcvt.wu.d, 0.0: PASS
+fcvt.wu.d, -0.0: PASS
+fcvt.wu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, underflow: PASS
+fcvt.wu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, -infinity: PASS
+fcvt.wu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, signaling NaN: PASS
+fcvt.d.w, 0: PASS
+fcvt.d.w, negative: PASS
+fcvt.d.w, truncate: PASS
+fcvt.d.wu, 0: PASS
+fcvt.d.wu: PASS
+fcvt.d.wu, truncate: PASS
+fcvt.l.d, truncate positive: PASS
+fcvt.l.d, truncate negative: PASS
+fcvt.l.d, 0.0: PASS
+fcvt.l.d, -0.0: PASS
+fcvt.l.d, 32-bit overflow: PASS
+fcvt.l.d, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, underflow: PASS
+fcvt.l.d, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, -infinity: PASS
+fcvt.l.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.lu.d, truncate positive: PASS
+fcvt.lu.d, truncate negative: PASS
+fcvt.lu.d, 0.0: PASS
+fcvt.lu.d, -0.0: PASS
+fcvt.lu.d, 32-bit overflow: PASS
+fcvt.lu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, underflow: PASS
+fcvt.lu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, -infinity: PASS
+fcvt.lu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, signaling NaN: PASS
+fmv.x.d, positive: PASS
+fmv.x.d, negative: PASS
+fmv.x.d, 0.0: PASS
+fmv.x.d, -0.0: PASS
+fcvt.d.l, 0: PASS
+fcvt.d.l, negative: PASS
+fcvt.d.l, 32-bit truncate: PASS
+fcvt.d.lu, 0: PASS
+fcvt.d.lu: PASS
+fcvt.d.lu, 32-bit truncate: PASS
+fmv.d.x: PASS
+Exiting @ tick 432134500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000339 # Number of seconds simulated
-sim_ticks 339173000 # Number of ticks simulated
-final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 215547 # Simulator instruction rate (inst/s)
-host_op_rate 215545 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 244214530 # Simulator tick rate (ticks/s)
-host_mem_usage 263004 # Number of bytes of host memory used
-host_seconds 1.39 # Real time elapsed on the host
-sim_insts 299354 # Number of instructions simulated
-sim_ops 299354 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 95040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1485 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 175 # Per bank write bursts
-system.physmem.perBankRdBursts::1 68 # Per bank write bursts
-system.physmem.perBankRdBursts::2 18 # Per bank write bursts
-system.physmem.perBankRdBursts::3 72 # Per bank write bursts
-system.physmem.perBankRdBursts::4 169 # Per bank write bursts
-system.physmem.perBankRdBursts::5 291 # Per bank write bursts
-system.physmem.perBankRdBursts::6 95 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9 # Per bank write bursts
-system.physmem.perBankRdBursts::9 115 # Per bank write bursts
-system.physmem.perBankRdBursts::10 155 # Per bank write bursts
-system.physmem.perBankRdBursts::11 169 # Per bank write bursts
-system.physmem.perBankRdBursts::12 48 # Per bank write bursts
-system.physmem.perBankRdBursts::13 55 # Per bank write bursts
-system.physmem.perBankRdBursts::14 15 # Per bank write bursts
-system.physmem.perBankRdBursts::15 27 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 338956500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1485 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation
-system.physmem.totQLat 20061750 # Total ticks spent queuing
-system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.19 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 1195 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 228253.54 # Average gap between requests
-system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ)
-system.physmem_0.averagePower 553.841711 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states
-system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ)
-system.physmem_1.averagePower 536.767851 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 80662 # Number of BP lookups
-system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 38260 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 162 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 678346 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 299354 # Number of instructions committed
-system.cpu.committedOps 299354 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 2.266033 # CPI: cycles per instruction
-system.cpu.ipc 0.441300 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction
-system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction
-system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 299354 # Class of committed instruction
-system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits
-system.cpu.dcache.overall_hits::total 119892 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
-system.cpu.dcache.overall_misses::total 511 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 80 # number of replacements
-system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 273390 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits
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-system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1178 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses
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-system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
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-system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
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-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
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-system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
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-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes)
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-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1283 # Transaction distribution
-system.membus.trans_dist::ReadExReq 202 # Transaction distribution
-system.membus.trans_dist::ReadExResp 202 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1485 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1485 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
+sim_seconds 0.000432
+sim_ticks 432134500
+final_tick 432134500
+sim_freq 1000000000000
+host_inst_rate 3359
+host_op_rate 3369
+host_tick_rate 3337861
+host_mem_usage 272860
+host_seconds 129.46
+sim_insts 434949
+sim_ops 436252
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 432134500
+system.physmem.bytes_read::cpu.inst 85184
+system.physmem.bytes_read::cpu.data 34432
+system.physmem.bytes_read::total 119616
+system.physmem.bytes_inst_read::cpu.inst 85184
+system.physmem.bytes_inst_read::total 85184
+system.physmem.num_reads::cpu.inst 1331
+system.physmem.num_reads::cpu.data 538
+system.physmem.num_reads::total 1869
+system.physmem.bw_read::cpu.inst 197123812
+system.physmem.bw_read::cpu.data 79678896
+system.physmem.bw_read::total 276802708
+system.physmem.bw_inst_read::cpu.inst 197123812
+system.physmem.bw_inst_read::total 197123812
+system.physmem.bw_total::cpu.inst 197123812
+system.physmem.bw_total::cpu.data 79678896
+system.physmem.bw_total::total 276802708
+system.physmem.readReqs 1869
+system.physmem.writeReqs 0
+system.physmem.readBursts 1869
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 119616
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 119616
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 257
+system.physmem.perBankRdBursts::1 275
+system.physmem.perBankRdBursts::2 180
+system.physmem.perBankRdBursts::3 185
+system.physmem.perBankRdBursts::4 157
+system.physmem.perBankRdBursts::5 101
+system.physmem.perBankRdBursts::6 126
+system.physmem.perBankRdBursts::7 65
+system.physmem.perBankRdBursts::8 51
+system.physmem.perBankRdBursts::9 72
+system.physmem.perBankRdBursts::10 18
+system.physmem.perBankRdBursts::11 38
+system.physmem.perBankRdBursts::12 89
+system.physmem.perBankRdBursts::13 78
+system.physmem.perBankRdBursts::14 74
+system.physmem.perBankRdBursts::15 103
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 432038000
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1869
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1648
+system.physmem.rdQLenPdf::1 209
+system.physmem.rdQLenPdf::2 12
+system.physmem.rdQLenPdf::3 0
+system.physmem.rdQLenPdf::4 0
+system.physmem.rdQLenPdf::5 0
+system.physmem.rdQLenPdf::6 0
+system.physmem.rdQLenPdf::7 0
+system.physmem.rdQLenPdf::8 0
+system.physmem.rdQLenPdf::9 0
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+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 0
+system.physmem.wrQLenPdf::1 0
+system.physmem.wrQLenPdf::2 0
+system.physmem.wrQLenPdf::3 0
+system.physmem.wrQLenPdf::4 0
+system.physmem.wrQLenPdf::5 0
+system.physmem.wrQLenPdf::6 0
+system.physmem.wrQLenPdf::7 0
+system.physmem.wrQLenPdf::8 0
+system.physmem.wrQLenPdf::9 0
+system.physmem.wrQLenPdf::10 0
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+system.physmem.wrQLenPdf::12 0
+system.physmem.wrQLenPdf::13 0
+system.physmem.wrQLenPdf::14 0
+system.physmem.wrQLenPdf::15 0
+system.physmem.wrQLenPdf::16 0
+system.physmem.wrQLenPdf::17 0
+system.physmem.wrQLenPdf::18 0
+system.physmem.wrQLenPdf::19 0
+system.physmem.wrQLenPdf::20 0
+system.physmem.wrQLenPdf::21 0
+system.physmem.wrQLenPdf::22 0
+system.physmem.wrQLenPdf::23 0
+system.physmem.wrQLenPdf::24 0
+system.physmem.wrQLenPdf::25 0
+system.physmem.wrQLenPdf::26 0
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+system.physmem.wrQLenPdf::32 0
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+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 414
+system.physmem.bytesPerActivate::mean 284.599033
+system.physmem.bytesPerActivate::gmean 203.186885
+system.physmem.bytesPerActivate::stdev 239.597136
+system.physmem.bytesPerActivate::0-127 97 23.42% 23.42%
+system.physmem.bytesPerActivate::128-255 125 30.19% 53.62%
+system.physmem.bytesPerActivate::256-383 69 16.66% 70.28%
+system.physmem.bytesPerActivate::384-511 58 14.00% 84.29%
+system.physmem.bytesPerActivate::512-639 23 5.55% 89.85%
+system.physmem.bytesPerActivate::640-767 14 3.38% 93.23%
+system.physmem.bytesPerActivate::768-895 8 1.93% 95.16%
+system.physmem.bytesPerActivate::896-1023 8 1.93% 97.10%
+system.physmem.bytesPerActivate::1024-1151 12 2.89% 99.99%
+system.physmem.bytesPerActivate::total 414
+system.physmem.totQLat 27138750
+system.physmem.totMemAccLat 62182500
+system.physmem.totBusLat 9345000
+system.physmem.avgQLat 14520.46
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 33270.46
+system.physmem.avgRdBW 276.80
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 276.80
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 2.16
+system.physmem.busUtilRead 2.16
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.06
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1445
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 77.31
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 231159.97
+system.physmem.pageHitRate 77.31
+system.physmem_0.actEnergy 2156280
+system.physmem_0.preEnergy 1130910
+system.physmem_0.readEnergy 9610440
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 33805200
+system.physmem_0.actBackEnergy 22735020
+system.physmem_0.preBackEnergy 728640
+system.physmem_0.actPowerDownEnergy 167294430
+system.physmem_0.prePowerDownEnergy 5186400
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 242647320
+system.physmem_0.averagePower 561.508139
+system.physmem_0.totalIdleTime 380124250
+system.physmem_0.memoryStateTime::IDLE 312000
+system.physmem_0.memoryStateTime::REF 14300000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 13499750
+system.physmem_0.memoryStateTime::ACT 37116000
+system.physmem_0.memoryStateTime::ACT_PDN 366906750
+system.physmem_1.actEnergy 871080
+system.physmem_1.preEnergy 440220
+system.physmem_1.readEnergy 3734220
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 15366000
+system.physmem_1.actBackEnergy 9609630
+system.physmem_1.preBackEnergy 719520
+system.physmem_1.actPowerDownEnergy 53643840
+system.physmem_1.prePowerDownEnergy 14784960
+system.physmem_1.selfRefreshEnergy 62387520
+system.physmem_1.totalEnergy 161556990
+system.physmem_1.averagePower 373.857683
+system.physmem_1.totalIdleTime 409147000
+system.physmem_1.memoryStateTime::IDLE 1209000
+system.physmem_1.memoryStateTime::REF 6518000
+system.physmem_1.memoryStateTime::SREF 253044500
+system.physmem_1.memoryStateTime::PRE_PDN 38497750
+system.physmem_1.memoryStateTime::ACT 15214500
+system.physmem_1.memoryStateTime::ACT_PDN 117650750
+system.pwrStateResidencyTicks::UNDEFINED 432134500
+system.cpu.branchPred.lookups 119617
+system.cpu.branchPred.condPredicted 84602
+system.cpu.branchPred.condIncorrect 8795
+system.cpu.branchPred.BTBLookups 74150
+system.cpu.branchPred.BTBHits 39240
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 52.919757
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 24116
+system.cpu.branchPred.indirectHits 14470
+system.cpu.branchPred.indirectMisses 9646
+system.cpu.branchPredindirectMispredicted 4958
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 220
+system.cpu.pwrStateResidencyTicks::ON 432134500
+system.cpu.numCycles 864269
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 434949
+system.cpu.committedOps 436252
+system.cpu.discardedOps 24002
+system.cpu.numFetchSuspends 0
+system.cpu.cpi 1.987058
+system.cpu.ipc 0.503256
+system.cpu.op_class_0::No_OpClass 224 0.05% 0.05%
+system.cpu.op_class_0::IntAlu 256681 58.83% 58.88%
+system.cpu.op_class_0::IntMult 710 0.16% 59.05%
+system.cpu.op_class_0::IntDiv 992 0.22% 59.27%
+system.cpu.op_class_0::FloatAdd 133 0.03% 59.30%
+system.cpu.op_class_0::FloatCmp 170 0.03% 59.34%
+system.cpu.op_class_0::FloatCvt 128 0.02% 59.37%
+system.cpu.op_class_0::FloatMult 30 0.00% 59.38%
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.38%
+system.cpu.op_class_0::FloatDiv 11 0.00% 59.38%
+system.cpu.op_class_0::FloatMisc 0 0.00% 59.38%
+system.cpu.op_class_0::FloatSqrt 5 0.00% 59.38%
+system.cpu.op_class_0::SimdAdd 0 0.00% 59.38%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdAlu 0 0.00% 59.38%
+system.cpu.op_class_0::SimdCmp 0 0.00% 59.38%
+system.cpu.op_class_0::SimdCvt 0 0.00% 59.38%
+system.cpu.op_class_0::SimdMisc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdMult 0 0.00% 59.38%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdShift 0 0.00% 59.38%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.38%
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.38%
+system.cpu.op_class_0::MemRead 109574 25.11% 84.50%
+system.cpu.op_class_0::MemWrite 66842 15.32% 99.82%
+system.cpu.op_class_0::FloatMemRead 571 0.13% 99.95%
+system.cpu.op_class_0::FloatMemWrite 181 0.04% 99.99%
+system.cpu.op_class_0::IprAccess 0 0.00% 99.99%
+system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99%
+system.cpu.op_class_0::total 436252
+system.cpu.tickCycles 588283
+system.cpu.idleCycles 275986
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 432134500
+system.cpu.dcache.tags.replacements 1
+system.cpu.dcache.tags.tagsinuse 417.816714
+system.cpu.dcache.tags.total_refs 180665
+system.cpu.dcache.tags.sampled_refs 539
+system.cpu.dcache.tags.avg_refs 335.185528
+system.cpu.dcache.tags.warmup_cycle 0
+system.cpu.dcache.tags.occ_blocks::cpu.data 417.816714
+system.cpu.dcache.tags.occ_percent::cpu.data 0.102006
+system.cpu.dcache.tags.occ_percent::total 0.102006
+system.cpu.dcache.tags.occ_task_id_blocks::1024 538
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 13
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 21
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 504
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.131347
+system.cpu.dcache.tags.tag_accesses 363297
+system.cpu.dcache.tags.data_accesses 363297
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 432134500
+system.cpu.dcache.ReadReq_hits::cpu.data 112284
+system.cpu.dcache.ReadReq_hits::total 112284
+system.cpu.dcache.WriteReq_hits::cpu.data 64864
+system.cpu.dcache.WriteReq_hits::total 64864
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1758
+system.cpu.dcache.LoadLockedReq_hits::total 1758
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1759
+system.cpu.dcache.StoreCondReq_hits::total 1759
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+system.cpu.dcache.demand_hits::total 177148
+system.cpu.dcache.overall_hits::cpu.data 177148
+system.cpu.dcache.overall_hits::total 177148
+system.cpu.dcache.ReadReq_misses::cpu.data 313
+system.cpu.dcache.ReadReq_misses::total 313
+system.cpu.dcache.WriteReq_misses::cpu.data 400
+system.cpu.dcache.WriteReq_misses::total 400
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 1
+system.cpu.dcache.LoadLockedReq_misses::total 1
+system.cpu.dcache.demand_misses::cpu.data 713
+system.cpu.dcache.demand_misses::total 713
+system.cpu.dcache.overall_misses::cpu.data 713
+system.cpu.dcache.overall_misses::total 713
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 28002500
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+system.cpu.dcache.WriteReq_miss_latency::cpu.data 33938000
+system.cpu.dcache.WriteReq_miss_latency::total 33938000
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92000
+system.cpu.dcache.LoadLockedReq_miss_latency::total 92000
+system.cpu.dcache.demand_miss_latency::cpu.data 61940500
+system.cpu.dcache.demand_miss_latency::total 61940500
+system.cpu.dcache.overall_miss_latency::cpu.data 61940500
+system.cpu.dcache.overall_miss_latency::total 61940500
+system.cpu.dcache.ReadReq_accesses::cpu.data 112597
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+system.cpu.dcache.WriteReq_accesses::cpu.data 65264
+system.cpu.dcache.WriteReq_accesses::total 65264
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1759
+system.cpu.dcache.LoadLockedReq_accesses::total 1759
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1759
+system.cpu.dcache.StoreCondReq_accesses::total 1759
+system.cpu.dcache.demand_accesses::cpu.data 177861
+system.cpu.dcache.demand_accesses::total 177861
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+system.cpu.toL2Bus.snoop_fanout::samples 1878
+system.cpu.toL2Bus.snoop_fanout::mean 0.000532
+system.cpu.toL2Bus.snoop_fanout::stdev 0.023075
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1877 99.94% 99.94%
+system.cpu.toL2Bus.snoop_fanout::1 1 0.05% 99.99%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 1878
+system.cpu.toL2Bus.reqLayer0.occupancy 1111500
+system.cpu.toL2Bus.reqLayer0.utilization 0.2
+system.cpu.toL2Bus.respLayer0.occupancy 2007000
+system.cpu.toL2Bus.respLayer0.utilization 0.4
+system.cpu.toL2Bus.respLayer1.occupancy 808500
+system.cpu.toL2Bus.respLayer1.utilization 0.1
+system.membus.snoop_filter.tot_requests 1869
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 432134500
+system.membus.trans_dist::ReadResp 1641
+system.membus.trans_dist::ReadExReq 228
+system.membus.trans_dist::ReadExResp 228
+system.membus.trans_dist::ReadSharedReq 1641
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738
+system.membus.pkt_count::total 3738
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616
+system.membus.pkt_size::total 119616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1869
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1869 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1869
+system.membus.reqLayer0.occupancy 2203500
+system.membus.reqLayer0.utilization 0.5
+system.membus.respLayer1.occupancy 9944750
+system.membus.respLayer1.utilization 2.3
---------- End Simulation Statistics ----------
--- /dev/null
+[root]
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+full_system=false
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+
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+symbolfile=
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+thermal_model=Null
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+
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+
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+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
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+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
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+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
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+socket_id=0
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+switched_out=false
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+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
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+indirectWays=2
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+localCtrBits=2
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+localPredictorSize=2048
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+useIndirect=true
+
+[system.cpu.dcache]
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+power_model=Null
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+sequential_access=false
+size=262144
+system=system
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+tags=system.cpu.dcache.tags
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+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
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+tag_latency=2
+
+[system.cpu.dtb]
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+
+[system.cpu.fuPool]
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+
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+
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+power_model=Null
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+response_latency=2
+sequential_access=false
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+system=system
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+tags=system.cpu.icache.tags
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+write_buffers=8
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+
+[system.cpu.icache.tags]
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+
+[system.cpu.interrupts]
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+
+[system.cpu.isa]
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+
+[system.cpu.itb]
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+
+[system.cpu.l2cache]
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+response_latency=20
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+size=2097152
+system=system
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+tags=system.cpu.l2cache.tags
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+
+[system.cpu.l2cache.tags]
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+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
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+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
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+IDD3N2=0.000000
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+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
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+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
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+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
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+dll=true
+eventq_index=0
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+kvm_map=true
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+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
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+tREFI=7800000
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+tRP=13750
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+tRTP=7500
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+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
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+ "tRFC": 260000,
+ "activation_limit": 4,
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+ "tWTR": 7500,
+ "IDD52": "0.0",
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+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
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+ "null": false,
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+ "eventq_index": 0,
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+ "IDD4R": "0.157",
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+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
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+ "IDD6": "0.02",
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+ "type": "DRAMCtrl",
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+ "page_policy": "open_adaptive",
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+ "tCK": 1250,
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+ "tBURST": 5000,
+ "path": "system.physmem",
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+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
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+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
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+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
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+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
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+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
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+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
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+ "mem_mode": "timing",
+ "name": "system",
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+ "load_addr_mask": 1099511627775,
+ "cpu": [
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+ "fetchTrapLatency": 1,
+ "iewToRenameDelay": 1,
+ "l2cache": {
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+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
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+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
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+ "assoc": 8,
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+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
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+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
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+ "tag_latency": 20,
+ "name": "l2cache",
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+ "sequential_access": false,
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+ },
+ "itb": {
+ "name": "itb",
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+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
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+ "max_loads_all_threads": 0,
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+ "smtIQThreshold": 100,
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+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
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+ "system": "system",
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+ "maxStackSize": 67108864,
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+ "type": "Process",
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+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "SSITSize": 1024,
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+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
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+ "renameWidth": 8,
+ "numThreads": 1,
+ "syscallRetryLatency": 10000,
+ "squashWidth": 8,
+ "function_trace": false,
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+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
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+ "system": "system",
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+ "cxx_class": "CoherentXBar",
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+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "p_state_clk_gate_min": 1000,
+ "fuPool": {
+ "name": "fuPool",
+ "FUList": [
+ {
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+ "opList": [
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+ "path": "system.cpu.fuPool.FUList0.opList",
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+ }
+ ],
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+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList0",
+ "type": "FUDesc"
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+ "type": "OpDesc"
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+ "name": "opList1",
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+ "cxx_class": "OpDesc",
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+ }
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+ "path": "system.cpu.fuPool.FUList1",
+ "type": "FUDesc"
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+ "name": "opList0",
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+ {
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList1",
+ "type": "OpDesc"
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList2",
+ "type": "OpDesc"
+ }
+ ],
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+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList2",
+ "type": "FUDesc"
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+ {
+ "count": 2,
+ "opList": [
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+ "name": "opList0",
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList0",
+ "type": "OpDesc"
+ },
+ {
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+ "name": "opList1",
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+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMisc",
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+ "name": "opList2",
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList2",
+ "type": "OpDesc"
+ },
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+ "opClass": "FloatDiv",
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+ "pipelined": false,
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+ "path": "system.cpu.fuPool.FUList3.opList3",
+ "type": "OpDesc"
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+ "opClass": "FloatSqrt",
+ "opLat": 24,
+ "name": "opList4",
+ "pipelined": false,
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+ "type": "OpDesc"
+ }
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+ "path": "system.cpu.fuPool.FUList3",
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+ },
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+ "path": "system.cpu.fuPool.FUList4.opList0",
+ "type": "OpDesc"
+ },
+ {
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+ "peer": "system.cpu.icache_port",
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+ "role": "MASTER"
+ },
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+ "name": "tags",
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+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
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+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "path": "system.cpu",
+ "numRobs": 1,
+ "switched_out": false,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "smtROBThreshold": 100,
+ "numIQEntries": 64,
+ "branchPred": {
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+ "BTBEntries": 4096,
+ "cxx_class": "TournamentBP",
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+ "globalCtrBits": 2,
+ "choicePredictorSize": 8192,
+ "indirectHashGHR": true,
+ "eventq_index": 0,
+ "localHistoryTableSize": 2048,
+ "type": "TournamentBP",
+ "indirectSets": 256,
+ "indirectWays": 2,
+ "choiceCtrBits": 2,
+ "useIndirect": true,
+ "localCtrBits": 2,
+ "path": "system.cpu.branchPred",
+ "localPredictorSize": 2048,
+ "RASSize": 16,
+ "globalPredictorSize": 8192,
+ "name": "branchPred",
+ "indirectHashTargets": true,
+ "instShiftAmt": 2,
+ "indirectTagSize": 16,
+ "BTBTagSize": 16
+ },
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "smtROBPolicy": "Partitioned",
+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
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+ "tag_latency": 2,
+ "name": "tags",
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+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "numPhysVecRegs": 256,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "smtCommitPolicy": "RoundRobin",
+ "issueToExecuteDelay": 1,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "numROBEntries": 192,
+ "fetchQueueSize": 32,
+ "iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 0,
+ "renameToIEWDelay": 2,
+ "p_state_clk_gate_bins": 20,
+ "progress_interval": 0,
+ "LQEntries": 32
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6006
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/o3-timing
+
+Global frequency set at 1000000000000 ticks per second
+fld: PASS
+fsd: PASS
+fmadd.d: PASS
+fmadd.d, quiet NaN: PASS
+fmadd.d, signaling NaN: PASS
+fmadd.d, infinity: PASS
+fmadd.d, -infinity: PASS
+fmsub.d: PASS
+fmsub.d, quiet NaN: PASS
+fmsub.d, signaling NaN: PASS
+fmsub.d, infinity: PASS
+fmsub.d, -infinity: PASS
+fmsub.d, subtract infinity: PASS
+fnmsub.d: PASS
+fnmsub.d, quiet NaN: PASS
+fnmsub.d, signaling NaN: PASS
+fnmsub.d, infinity: PASS
+fnmsub.d, -infinity: PASS
+fnmsub.d, subtract infinity: PASS
+fnmadd.d: PASS
+fnmadd.d, quiet NaN: PASS
+fnmadd.d, signaling NaN: PASS
+fnmadd.d, infinity: PASS
+fnmadd.d, -infinity: PASS
+fadd.d: PASS
+fadd.d, quiet NaN: PASS
+fadd.d, signaling NaN: PASS
+fadd.d, infinity: PASS
+fadd.d, -infinity: PASS
+fsub.d: PASS
+fsub.d, quiet NaN: PASS
+fsub.d, signaling NaN: PASS
+fsub.d, infinity: PASS
+fsub.d, -infinity: PASS
+fsub.d, subtract infinity: PASS
+fmul.d: PASS
+fmul.d, quiet NaN: PASS
+fmul.d, signaling NaN: PASS
+fmul.d, infinity: PASS
+fmul.d, -infinity: PASS
+fmul.d, 0*infinity: PASS
+fmul.d, overflow: PASS
+fmul.d, underflow: PASS
+fdiv.d: PASS
+fdiv.d, quiet NaN: PASS
+fdiv.d, signaling NaN: PASS
+fdiv.d/0: PASS
+fdiv.d/infinity: PASS
+fdiv.d, infinity/infinity: PASS
+fdiv.d, 0/0: PASS
+fdiv.d, infinity/0: PASS
+fdiv.d, 0/infinity: PASS
+fdiv.d, underflow: PASS
+fdiv.d, overflow: PASS
+fsqrt.d: PASS
+fsqrt.d, NaN: PASS
+fsqrt.d, quiet NaN: PASS
+fsqrt.d, signaling NaN: PASS
+fsqrt.d, infinity: PASS
+fsgnj.d, ++: PASS
+fsgnj.d, +-: PASS
+fsgnj.d, -+: PASS
+fsgnj.d, --: PASS
+fsgnj.d, quiet NaN: PASS
+fsgnj.d, signaling NaN: PASS
+fsgnj.d, inject NaN: PASS
+fsgnj.d, inject -NaN: PASS
+fsgnjn.d, ++: PASS
+fsgnjn.d, +-: PASS
+fsgnjn.d, -+: PASS
+fsgnjn.d, --: PASS
+fsgnjn.d, quiet NaN: PASS
+fsgnjn.d, signaling NaN: PASS
+fsgnjn.d, inject NaN: PASS
+fsgnjn.d, inject NaN: PASS
+fsgnjx.d, ++: PASS
+fsgnjx.d, +-: PASS
+fsgnjx.d, -+: PASS
+fsgnjx.d, --: PASS
+fsgnjx.d, quiet NaN: PASS
+fsgnjx.d, signaling NaN: PASS
+fsgnjx.d, inject NaN: PASS
+fsgnjx.d, inject NaN: PASS
+fmin.d: PASS
+fmin.d, -infinity: PASS
+fmin.d, infinity: PASS
+fmin.d, quiet NaN first: PASS
+fmin.d, quiet NaN second: PASS
+fmin.d, quiet NaN both: PASS
+fmin.d, signaling NaN first: PASS
+fmin.d, signaling NaN second: PASS
+fmin.d, signaling NaN both: PASS
+fmax.d: PASS
+fmax.d, -infinity: PASS
+fmax.d, infinity: PASS
+fmax.d, quiet NaN first: PASS
+fmax.d, quiet NaN second: PASS
+fmax.d, quiet NaN both: PASS
+fmax.d, signaling NaN first: PASS
+fmax.d, signaling NaN second: PASS
+fmax.d, signaling NaN both: PASS
+fcvt.s.d: PASS
+fcvt.s.d, quiet NaN: PASS
+fcvt.s.d, signaling NaN: PASS
+fcvt.s.d, infinity: PASS
+fcvt.s.d, overflow: PASS
+fcvt.s.d, underflow: PASS
+fcvt.d.s: PASS
+fcvt.d.s, quiet NaN: PASS
+fcvt.d.s, signaling NaN: PASS
+fcvt.d.s, infinity: PASS
+feq.d, equal: PASS
+feq.d, not equal: PASS
+feq.d, 0 == -0: PASS
+feq.d, quiet NaN first: PASS
+feq.d, quiet NaN second: PASS
+feq.d, quiet NaN both: PASS
+feq.d, signaling NaN first: PASS
+feq.d, signaling NaN second: PASS
+feq.d, signaling NaN both: PASS
+flt.d, equal: PASS
+flt.d, less: PASS
+flt.d, greater: PASS
+flt.d, quiet NaN first: PASS
+flt.d, quiet NaN second: PASS
+flt.d, quiet NaN both: PASS
+flt.d, signaling NaN first: PASS
+flt.d, signaling NaN second: PASS
+flt.d, signaling NaN both: PASS
+fle.d, equal: PASS
+fle.d, less: PASS
+fle.d, greater: PASS
+fle.d, 0 == -0: PASS
+fle.d, quiet NaN first: PASS
+fle.d, quiet NaN second: PASS
+fle.d, quiet NaN both: PASS
+fle.d, signaling NaN first: PASS
+fle.d, signaling NaN second: PASS
+fle.d, signaling NaN both: PASS
+fclass.d, -infinity: PASS
+fclass.d, -normal: PASS
+fclass.d, -subnormal: PASS
+fclass.d, -0.0: PASS
+fclass.d, 0.0: PASS
+fclass.d, subnormal: PASS
+fclass.d, normal: PASS
+fclass.d, infinity: PASS
+fclass.d, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.w.d, truncate positive: PASS
+fcvt.w.d, truncate negative: PASS
+fcvt.w.d, 0.0: PASS
+fcvt.w.d, -0.0: PASS
+fcvt.w.d, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, underflow: PASS
+fcvt.w.d, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, -infinity: PASS
+fcvt.w.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.wu.d, truncate positive: PASS
+fcvt.wu.d, truncate negative: PASS
+fcvt.wu.d, 0.0: PASS
+fcvt.wu.d, -0.0: PASS
+fcvt.wu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, underflow: PASS
+fcvt.wu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, -infinity: PASS
+fcvt.wu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, signaling NaN: PASS
+fcvt.d.w, 0: PASS
+fcvt.d.w, negative: PASS
+fcvt.d.w, truncate: PASS
+fcvt.d.wu, 0: PASS
+fcvt.d.wu: PASS
+fcvt.d.wu, truncate: PASS
+fcvt.l.d, truncate positive: PASS
+fcvt.l.d, truncate negative: PASS
+fcvt.l.d, 0.0: PASS
+fcvt.l.d, -0.0: PASS
+fcvt.l.d, 32-bit overflow: PASS
+fcvt.l.d, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, underflow: PASS
+fcvt.l.d, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, -infinity: PASS
+fcvt.l.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.lu.d, truncate positive: PASS
+fcvt.lu.d, truncate negative: PASS
+fcvt.lu.d, 0.0: PASS
+fcvt.lu.d, -0.0: PASS
+fcvt.lu.d, 32-bit overflow: PASS
+fcvt.lu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, underflow: PASS
+fcvt.lu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, -infinity: PASS
+fcvt.lu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, signaling NaN: PASS
+fmv.x.d, positive: PASS
+fmv.x.d, negative: PASS
+fmv.x.d, 0.0: PASS
+fmv.x.d, -0.0: PASS
+fcvt.d.l, 0: PASS
+fcvt.d.l, negative: PASS
+fcvt.d.l, 32-bit truncate: PASS
+fcvt.d.lu, 0: PASS
+fcvt.d.lu: PASS
+fcvt.d.lu, 32-bit truncate: PASS
+fmv.d.x: PASS
+Exiting @ tick 357345500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000357
+sim_ticks 357345500
+final_tick 357345500
+sim_freq 1000000000000
+host_inst_rate 5089
+host_op_rate 5104
+host_tick_rate 4183343
+host_mem_usage 272348
+host_seconds 85.42
+sim_insts 434729
+sim_ops 436032
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 357345500
+system.physmem.bytes_read::cpu.inst 79680
+system.physmem.bytes_read::cpu.data 34816
+system.physmem.bytes_read::total 114496
+system.physmem.bytes_inst_read::cpu.inst 79680
+system.physmem.bytes_inst_read::total 79680
+system.physmem.num_reads::cpu.inst 1245
+system.physmem.num_reads::cpu.data 544
+system.physmem.num_reads::total 1789
+system.physmem.bw_read::cpu.inst 222977482
+system.physmem.bw_read::cpu.data 97429518
+system.physmem.bw_read::total 320407001
+system.physmem.bw_inst_read::cpu.inst 222977482
+system.physmem.bw_inst_read::total 222977482
+system.physmem.bw_total::cpu.inst 222977482
+system.physmem.bw_total::cpu.data 97429518
+system.physmem.bw_total::total 320407001
+system.physmem.readReqs 1789
+system.physmem.writeReqs 0
+system.physmem.readBursts 1789
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 114496
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 114496
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 257
+system.physmem.perBankRdBursts::1 275
+system.physmem.perBankRdBursts::2 173
+system.physmem.perBankRdBursts::3 193
+system.physmem.perBankRdBursts::4 150
+system.physmem.perBankRdBursts::5 95
+system.physmem.perBankRdBursts::6 117
+system.physmem.perBankRdBursts::7 59
+system.physmem.perBankRdBursts::8 47
+system.physmem.perBankRdBursts::9 59
+system.physmem.perBankRdBursts::10 19
+system.physmem.perBankRdBursts::11 34
+system.physmem.perBankRdBursts::12 85
+system.physmem.perBankRdBursts::13 69
+system.physmem.perBankRdBursts::14 57
+system.physmem.perBankRdBursts::15 100
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 357180500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1789
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1144
+system.physmem.rdQLenPdf::1 452
+system.physmem.rdQLenPdf::2 140
+system.physmem.rdQLenPdf::3 40
+system.physmem.rdQLenPdf::4 12
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 0
+system.physmem.rdQLenPdf::7 0
+system.physmem.rdQLenPdf::8 0
+system.physmem.rdQLenPdf::9 0
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 0
+system.physmem.wrQLenPdf::1 0
+system.physmem.wrQLenPdf::2 0
+system.physmem.wrQLenPdf::3 0
+system.physmem.wrQLenPdf::4 0
+system.physmem.wrQLenPdf::5 0
+system.physmem.wrQLenPdf::6 0
+system.physmem.wrQLenPdf::7 0
+system.physmem.wrQLenPdf::8 0
+system.physmem.wrQLenPdf::9 0
+system.physmem.wrQLenPdf::10 0
+system.physmem.wrQLenPdf::11 0
+system.physmem.wrQLenPdf::12 0
+system.physmem.wrQLenPdf::13 0
+system.physmem.wrQLenPdf::14 0
+system.physmem.wrQLenPdf::15 0
+system.physmem.wrQLenPdf::16 0
+system.physmem.wrQLenPdf::17 0
+system.physmem.wrQLenPdf::18 0
+system.physmem.wrQLenPdf::19 0
+system.physmem.wrQLenPdf::20 0
+system.physmem.wrQLenPdf::21 0
+system.physmem.wrQLenPdf::22 0
+system.physmem.wrQLenPdf::23 0
+system.physmem.wrQLenPdf::24 0
+system.physmem.wrQLenPdf::25 0
+system.physmem.wrQLenPdf::26 0
+system.physmem.wrQLenPdf::27 0
+system.physmem.wrQLenPdf::28 0
+system.physmem.wrQLenPdf::29 0
+system.physmem.wrQLenPdf::30 0
+system.physmem.wrQLenPdf::31 0
+system.physmem.wrQLenPdf::32 0
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 426
+system.physmem.bytesPerActivate::mean 261.258215
+system.physmem.bytesPerActivate::gmean 177.377467
+system.physmem.bytesPerActivate::stdev 241.871281
+system.physmem.bytesPerActivate::0-127 137 32.15% 32.15%
+system.physmem.bytesPerActivate::128-255 116 27.23% 59.38%
+system.physmem.bytesPerActivate::256-383 55 12.91% 72.30%
+system.physmem.bytesPerActivate::384-511 53 12.44% 84.74%
+system.physmem.bytesPerActivate::512-639 26 6.10% 90.84%
+system.physmem.bytesPerActivate::640-767 12 2.81% 93.66%
+system.physmem.bytesPerActivate::768-895 8 1.87% 95.53%
+system.physmem.bytesPerActivate::896-1023 6 1.40% 96.94%
+system.physmem.bytesPerActivate::1024-1151 13 3.05% 99.99%
+system.physmem.bytesPerActivate::total 426
+system.physmem.totQLat 29198750
+system.physmem.totMemAccLat 62742500
+system.physmem.totBusLat 8945000
+system.physmem.avgQLat 16321.26
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 35071.26
+system.physmem.avgRdBW 320.40
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 320.40
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 2.50
+system.physmem.busUtilRead 2.50
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.36
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1349
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 75.40
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 199653.71
+system.physmem.pageHitRate 75.40
+system.physmem_0.actEnergy 2156280
+system.physmem_0.preEnergy 1119525
+system.physmem_0.readEnergy 9417660
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 27658800
+system.physmem_0.actBackEnergy 19175370
+system.physmem_0.preBackEnergy 595200
+system.physmem_0.actPowerDownEnergy 135115080
+system.physmem_0.prePowerDownEnergy 6696960
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 201934875
+system.physmem_0.averagePower 565.095827
+system.physmem_0.totalIdleTime 313626500
+system.physmem_0.memoryStateTime::IDLE 257500
+system.physmem_0.memoryStateTime::REF 11700000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 17432500
+system.physmem_0.memoryStateTime::ACT 31632750
+system.physmem_0.memoryStateTime::ACT_PDN 296322750
+system.physmem_1.actEnergy 985320
+system.physmem_1.preEnergy 497145
+system.physmem_1.readEnergy 3355800
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 13522080
+system.physmem_1.actBackEnergy 8332260
+system.physmem_1.preBackEnergy 718560
+system.physmem_1.actPowerDownEnergy 39862380
+system.physmem_1.prePowerDownEnergy 14924160
+system.physmem_1.selfRefreshEnergy 52829760
+system.physmem_1.totalEnergy 135027465
+system.physmem_1.averagePower 377.861709
+system.physmem_1.totalIdleTime 336590000
+system.physmem_1.memoryStateTime::IDLE 1334500
+system.physmem_1.memoryStateTime::REF 5744000
+system.physmem_1.memoryStateTime::SREF 210920500
+system.physmem_1.memoryStateTime::PRE_PDN 38865500
+system.physmem_1.memoryStateTime::ACT 13057250
+system.physmem_1.memoryStateTime::ACT_PDN 87423750
+system.pwrStateResidencyTicks::UNDEFINED 357345500
+system.cpu.branchPred.lookups 137963
+system.cpu.branchPred.condPredicted 96949
+system.cpu.branchPred.condIncorrect 28208
+system.cpu.branchPred.BTBLookups 88594
+system.cpu.branchPred.BTBHits 49630
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 56.019595
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 28658
+system.cpu.branchPred.indirectHits 15467
+system.cpu.branchPred.indirectMisses 13191
+system.cpu.branchPredindirectMispredicted 5179
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 220
+system.cpu.pwrStateResidencyTicks::ON 357345500
+system.cpu.numCycles 714692
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 135613
+system.cpu.fetch.Insts 614596
+system.cpu.fetch.Branches 137963
+system.cpu.fetch.predictedBranches 65097
+system.cpu.fetch.Cycles 444701
+system.cpu.fetch.SquashCycles 57212
+system.cpu.fetch.MiscStallCycles 165
+system.cpu.fetch.PendingTrapStallCycles 1046
+system.cpu.fetch.IcacheWaitRetryStallCycles 11
+system.cpu.fetch.CacheLines 93453
+system.cpu.fetch.IcacheSquashes 2267
+system.cpu.fetch.rateDist::samples 610142
+system.cpu.fetch.rateDist::mean 1.009502
+system.cpu.fetch.rateDist::stdev 0.972916
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 177437 29.08% 29.08%
+system.cpu.fetch.rateDist::1 317234 51.99% 81.07%
+system.cpu.fetch.rateDist::2 74911 12.27% 93.35%
+system.cpu.fetch.rateDist::3 21754 3.56% 96.91%
+system.cpu.fetch.rateDist::4 13865 2.27% 99.19%
+system.cpu.fetch.rateDist::5 2714 0.44% 99.63%
+system.cpu.fetch.rateDist::6 1405 0.23% 99.86%
+system.cpu.fetch.rateDist::7 414 0.06% 99.93%
+system.cpu.fetch.rateDist::8 408 0.06% 99.99%
+system.cpu.fetch.rateDist::overflows 0 0.00% 99.99%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::total 610142
+system.cpu.fetch.branchRate 0.193038
+system.cpu.fetch.rate 0.859945
+system.cpu.decode.IdleCycles 160289
+system.cpu.decode.BlockedCycles 52081
+system.cpu.decode.RunCycles 377160
+system.cpu.decode.UnblockCycles 2852
+system.cpu.decode.SquashCycles 17760
+system.cpu.decode.BranchResolved 47857
+system.cpu.decode.BranchMispred 11488
+system.cpu.decode.DecodedInsts 555576
+system.cpu.decode.SquashedInsts 15205
+system.cpu.rename.SquashCycles 17760
+system.cpu.rename.IdleCycles 181774
+system.cpu.rename.BlockCycles 4611
+system.cpu.rename.serializeStallCycles 40232
+system.cpu.rename.RunCycles 358471
+system.cpu.rename.UnblockCycles 7294
+system.cpu.rename.RenamedInsts 534785
+system.cpu.rename.ROBFullEvents 5
+system.cpu.rename.IQFullEvents 67
+system.cpu.rename.LQFullEvents 2993
+system.cpu.rename.SQFullEvents 2264
+system.cpu.rename.RenamedOperands 359758
+system.cpu.rename.RenameLookups 658701
+system.cpu.rename.int_rename_lookups 656814
+system.cpu.rename.fp_rename_lookups 1887
+system.cpu.rename.CommittedMaps 288923
+system.cpu.rename.UndoneMaps 70835
+system.cpu.rename.serializingInsts 2027
+system.cpu.rename.tempSerializingInsts 2027
+system.cpu.rename.skidInsts 4057
+system.cpu.memDep0.insertedLoads 127704
+system.cpu.memDep0.insertedStores 71313
+system.cpu.memDep0.conflictingLoads 549
+system.cpu.memDep0.conflictingStores 161
+system.cpu.iq.iqInstsAdded 493023
+system.cpu.iq.iqNonSpecInstsAdded 3683
+system.cpu.iq.iqInstsIssued 486946
+system.cpu.iq.iqSquashedInstsIssued 177
+system.cpu.iq.iqSquashedInstsExamined 60668
+system.cpu.iq.iqSquashedOperandsExamined 25216
+system.cpu.iq.iqSquashedNonSpecRemoved 392
+system.cpu.iq.issued_per_cycle::samples 610142
+system.cpu.iq.issued_per_cycle::mean 0.798086
+system.cpu.iq.issued_per_cycle::stdev 0.911334
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 265362 43.49% 43.49%
+system.cpu.iq.issued_per_cycle::1 243763 39.95% 83.44%
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+
+---------- End Simulation Statistics ----------
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:31
-gem5 executing on zizzer, pid 34072
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:12:11
+gem5 executing on boldrock, pid 2055
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 149676500 because target called exit()
+fcvt.w.d, underflow: PASS
+fcvt.w.d, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, -infinity: PASS
+fcvt.w.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.wu.d, truncate positive: PASS
+fcvt.wu.d, truncate negative: PASS
+fcvt.wu.d, 0.0: PASS
+fcvt.wu.d, -0.0: PASS
+fcvt.wu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, underflow: PASS
+fcvt.wu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, -infinity: PASS
+fcvt.wu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, signaling NaN: PASS
+fcvt.d.w, 0: PASS
+fcvt.d.w, negative: PASS
+fcvt.d.w, truncate: PASS
+fcvt.d.wu, 0: PASS
+fcvt.d.wu: PASS
+fcvt.d.wu, truncate: PASS
+fcvt.l.d, truncate positive: PASS
+fcvt.l.d, truncate negative: PASS
+fcvt.l.d, 0.0: PASS
+fcvt.l.d, -0.0: PASS
+fcvt.l.d, 32-bit overflow: PASS
+fcvt.l.d, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, underflow: PASS
+fcvt.l.d, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, -infinity: PASS
+fcvt.l.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.lu.d, truncate positive: PASS
+fcvt.lu.d, truncate negative: PASS
+fcvt.lu.d, 0.0: PASS
+fcvt.lu.d, -0.0: PASS
+fcvt.lu.d, 32-bit overflow: PASS
+fcvt.lu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, underflow: PASS
+fcvt.lu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, -infinity: PASS
+fcvt.lu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, signaling NaN: PASS
+fmv.x.d, positive: PASS
+fmv.x.d, negative: PASS
+fmv.x.d, 0.0: PASS
+fmv.x.d, -0.0: PASS
+fcvt.d.l, 0: PASS
+fcvt.d.l, negative: PASS
+fcvt.d.l, 32-bit truncate: PASS
+fcvt.d.lu, 0: PASS
+fcvt.d.lu: PASS
+fcvt.d.lu, 32-bit truncate: PASS
+fmv.d.x: PASS
+Exiting @ tick 255853000 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000150 # Number of seconds simulated
-sim_ticks 149676500 # Number of ticks simulated
-final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28553 # Simulator instruction rate (inst/s)
-host_op_rate 28553 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14284274 # Simulator tick rate (ticks/s)
-host_mem_usage 234416 # Number of bytes of host memory used
-host_seconds 10.48 # Real time elapsed on the host
-sim_insts 299191 # Number of instructions simulated
-sim_ops 299191 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory
-system.physmem.bytes_written::total 301409 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 162 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 299354 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 299191 # Number of instructions committed
-system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
-system.cpu.num_func_calls 21816 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
-system.cpu.num_int_insts 299008 # number of integer instructions
-system.cpu.num_fp_insts 1025 # number of float instructions
-system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
-system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
-system.cpu.num_mem_refs 118390 # number of memory refs
-system.cpu.num_load_insts 69843 # Number of load instructions
-system.cpu.num_store_insts 48547 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 299354 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 66377 # Number of branches fetched
-system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
-system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
-system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
-system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
-system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
-system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
-system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 299354 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 369197 # Transaction distribution
-system.membus.trans_dist::ReadResp 369197 # Transaction distribution
-system.membus.trans_dist::WriteReq 48546 # Transaction distribution
-system.membus.trans_dist::WriteResp 48546 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 417743 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 417743 # Request fanout histogram
+sim_seconds 0.000255
+sim_ticks 255853000
+final_tick 255853000
+sim_freq 1000000000000
+host_inst_rate 4946
+host_op_rate 4960
+host_tick_rate 2910956
+host_mem_usage 259288
+host_seconds 87.89
+sim_insts 434729
+sim_ops 436032
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 255853000
+system.physmem.bytes_read::cpu.inst 2041616
+system.physmem.bytes_read::cpu.data 725609
+system.physmem.bytes_read::total 2767225
+system.physmem.bytes_inst_read::cpu.inst 2041616
+system.physmem.bytes_inst_read::total 2041616
+system.physmem.bytes_written::cpu.data 458503
+system.physmem.bytes_written::total 458503
+system.physmem.num_reads::cpu.inst 510404
+system.physmem.num_reads::cpu.data 110145
+system.physmem.num_reads::total 620549
+system.physmem.num_writes::cpu.data 67023
+system.physmem.num_writes::total 67023
+system.physmem.bw_read::cpu.inst 7979644561
+system.physmem.bw_read::cpu.data 2836038662
+system.physmem.bw_read::total 10815683224
+system.physmem.bw_inst_read::cpu.inst 7979644561
+system.physmem.bw_inst_read::total 7979644561
+system.physmem.bw_write::cpu.data 1792056376
+system.physmem.bw_write::total 1792056376
+system.physmem.bw_total::cpu.inst 7979644561
+system.physmem.bw_total::cpu.data 4628095038
+system.physmem.bw_total::total 12607739600
+system.pwrStateResidencyTicks::UNDEFINED 255853000
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 220
+system.cpu.pwrStateResidencyTicks::ON 255853000
+system.cpu.numCycles 511707
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 434729
+system.cpu.committedOps 436032
+system.cpu.num_int_alu_accesses 433908
+system.cpu.num_fp_alu_accesses 1229
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 23870
+system.cpu.num_conditional_control_insts 71049
+system.cpu.num_int_insts 433908
+system.cpu.num_fp_insts 1229
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 549660
+system.cpu.num_int_register_writes 288600
+system.cpu.num_fp_register_reads 988
+system.cpu.num_fp_register_writes 800
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 177168
+system.cpu.num_load_insts 110145
+system.cpu.num_store_insts 67023
+system.cpu.num_idle_cycles -0
+system.cpu.num_busy_cycles 511707
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction -0
+system.cpu.Branches 94919
+system.cpu.op_class::No_OpClass 224 0.05% 0.05%
+system.cpu.op_class::IntAlu 256681 58.83% 58.88%
+system.cpu.op_class::IntMult 710 0.16% 59.05%
+system.cpu.op_class::IntDiv 992 0.22% 59.27%
+system.cpu.op_class::FloatAdd 133 0.03% 59.30%
+system.cpu.op_class::FloatCmp 170 0.03% 59.34%
+system.cpu.op_class::FloatCvt 128 0.02% 59.37%
+system.cpu.op_class::FloatMult 30 0.00% 59.38%
+system.cpu.op_class::FloatMultAcc 0 0.00% 59.38%
+system.cpu.op_class::FloatDiv 11 0.00% 59.38%
+system.cpu.op_class::FloatMisc 0 0.00% 59.38%
+system.cpu.op_class::FloatSqrt 5 0.00% 59.38%
+system.cpu.op_class::SimdAdd 0 0.00% 59.38%
+system.cpu.op_class::SimdAddAcc 0 0.00% 59.38%
+system.cpu.op_class::SimdAlu 0 0.00% 59.38%
+system.cpu.op_class::SimdCmp 0 0.00% 59.38%
+system.cpu.op_class::SimdCvt 0 0.00% 59.38%
+system.cpu.op_class::SimdMisc 0 0.00% 59.38%
+system.cpu.op_class::SimdMult 0 0.00% 59.38%
+system.cpu.op_class::SimdMultAcc 0 0.00% 59.38%
+system.cpu.op_class::SimdShift 0 0.00% 59.38%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 59.38%
+system.cpu.op_class::SimdSqrt 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatMult 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.38%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.38%
+system.cpu.op_class::MemRead 109574 25.11% 84.50%
+system.cpu.op_class::MemWrite 66842 15.32% 99.82%
+system.cpu.op_class::FloatMemRead 571 0.13% 99.95%
+system.cpu.op_class::FloatMemWrite 181 0.04% 99.99%
+system.cpu.op_class::IprAccess 0 0.00% 99.99%
+system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
+system.cpu.op_class::total 436252
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 255853000
+system.membus.trans_dist::ReadReq 618790
+system.membus.trans_dist::ReadResp 620549
+system.membus.trans_dist::WriteReq 65264
+system.membus.trans_dist::WriteResp 65264
+system.membus.trans_dist::LoadLockedReq 1759
+system.membus.trans_dist::StoreCondReq 1759
+system.membus.trans_dist::StoreCondResp 1759
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1020808
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 354336
+system.membus.pkt_count::total 1375144
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2041616
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1184112
+system.membus.pkt_size::total 3225728
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 687572
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 687572 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 687572
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
+addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
-transitions_per_cycle=4
+transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+addr_ranges=0:268435455:5:0:0:0
eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
+addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
- "cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
"support_data_reqs": true,
"is_cpu_sequencer": true
},
- "type": "L1Cache_Controller",
+ "cxx_class": "L1Cache_Controller",
"issue_latency": 2,
+ "type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
- "transitions_per_cycle": 4,
+ "transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
- "version": 0,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
- "type": "RubyDirectoryMemory",
- "numa_high_bit": 5,
- "size": 268435456
+ "type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:32
-gem5 executing on zizzer, pid 34074
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1344
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 6393532 because target called exit()
+fcvt.w.d, underflow: PASS
+fcvt.w.d, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, -infinity: PASS
+fcvt.w.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.wu.d, truncate positive: PASS
+fcvt.wu.d, truncate negative: PASS
+fcvt.wu.d, 0.0: PASS
+fcvt.wu.d, -0.0: PASS
+fcvt.wu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, underflow: PASS
+fcvt.wu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, -infinity: PASS
+fcvt.wu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, signaling NaN: PASS
+fcvt.d.w, 0: PASS
+fcvt.d.w, negative: PASS
+fcvt.d.w, truncate: PASS
+fcvt.d.wu, 0: PASS
+fcvt.d.wu: PASS
+fcvt.d.wu, truncate: PASS
+fcvt.l.d, truncate positive: PASS
+fcvt.l.d, truncate negative: PASS
+fcvt.l.d, 0.0: PASS
+fcvt.l.d, -0.0: PASS
+fcvt.l.d, 32-bit overflow: PASS
+fcvt.l.d, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, underflow: PASS
+fcvt.l.d, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, -infinity: PASS
+fcvt.l.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.lu.d, truncate positive: PASS
+fcvt.lu.d, truncate negative: PASS
+fcvt.lu.d, 0.0: PASS
+fcvt.lu.d, -0.0: PASS
+fcvt.lu.d, 32-bit overflow: PASS
+fcvt.lu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, underflow: PASS
+fcvt.lu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, -infinity: PASS
+fcvt.lu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, signaling NaN: PASS
+fmv.x.d, positive: PASS
+fmv.x.d, negative: PASS
+fmv.x.d, 0.0: PASS
+fmv.x.d, -0.0: PASS
+fcvt.d.l, 0: PASS
+fcvt.d.l, negative: PASS
+fcvt.d.l, 32-bit truncate: PASS
+fcvt.d.lu, 0: PASS
+fcvt.d.lu: PASS
+fcvt.d.lu, 32-bit truncate: PASS
+fmv.d.x: PASS
+Exiting @ tick 8234747 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.006394 # Number of seconds simulated
-sim_ticks 6393532 # Number of ticks simulated
-final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 80438 # Simulator instruction rate (inst/s)
-host_op_rate 80438 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1718903 # Simulator tick rate (ticks/s)
-host_mem_usage 429644 # Number of bytes of host memory used
-host_seconds 3.72 # Real time elapsed on the host
-sim_insts 299191 # Number of instructions simulated
-sim_ops 299191 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 97760 # Number of read requests accepted
-system.mem_ctrls.writeReqs 97756 # Number of write requests accepted
-system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 6393460 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 32.70 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states
-system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.cpu.clk_domain.clock 1 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 162 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 6393532 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 299191 # Number of instructions committed
-system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
-system.cpu.num_func_calls 21816 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
-system.cpu.num_int_insts 299008 # number of integer instructions
-system.cpu.num_fp_insts 1025 # number of float instructions
-system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
-system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
-system.cpu.num_mem_refs 118390 # number of memory refs
-system.cpu.num_load_insts 69843 # Number of load instructions
-system.cpu.num_store_insts 48547 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 6393532 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 66377 # Number of branches fetched
-system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
-system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
-system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
-system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
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-system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
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-system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
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-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
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-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
-system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 299354 # Class of executed instruction
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 1 # delay histogram for all message
-system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 195516 # delay histogram for all message
-system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 195516 # delay histogram for all message
+sim_seconds 0.008234
+sim_ticks 8234747
+final_tick 8234747
+sim_freq 1000000000
+host_inst_rate 3359
+host_op_rate 3369
+host_tick_rate 63636
+host_mem_usage 439776
+host_seconds 129.40
+sim_insts 434729
+sim_ops 436032
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 8234747
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 7528256
+system.mem_ctrls.bytes_read::total 7528256
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 7528000
+system.mem_ctrls.bytes_written::total 7528000
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 117629
+system.mem_ctrls.num_reads::total 117629
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 117625
+system.mem_ctrls.num_writes::total 117625
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 914206107
+system.mem_ctrls.bw_read::total 914206107
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 914175019
+system.mem_ctrls.bw_write::total 914175019
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1828381126
+system.mem_ctrls.bw_total::total 1828381126
+system.mem_ctrls.readReqs 117629
+system.mem_ctrls.writeReqs 117625
+system.mem_ctrls.readBursts 117629
+system.mem_ctrls.writeBursts 117625
+system.mem_ctrls.bytesReadDRAM 4130304
+system.mem_ctrls.bytesReadWrQ 3397952
+system.mem_ctrls.bytesWritten 4366848
+system.mem_ctrls.bytesReadSys 7528256
+system.mem_ctrls.bytesWrittenSys 7528000
+system.mem_ctrls.servicedByWrQ 53093
+system.mem_ctrls.mergedWrBursts 49364
+system.mem_ctrls.neitherReadNorWriteReqs 0
+system.mem_ctrls.perBankRdBursts::0 10167
+system.mem_ctrls.perBankRdBursts::1 8186
+system.mem_ctrls.perBankRdBursts::2 6889
+system.mem_ctrls.perBankRdBursts::3 10537
+system.mem_ctrls.perBankRdBursts::4 4633
+system.mem_ctrls.perBankRdBursts::5 1895
+system.mem_ctrls.perBankRdBursts::6 3152
+system.mem_ctrls.perBankRdBursts::7 8737
+system.mem_ctrls.perBankRdBursts::8 56
+system.mem_ctrls.perBankRdBursts::9 166
+system.mem_ctrls.perBankRdBursts::10 14
+system.mem_ctrls.perBankRdBursts::11 251
+system.mem_ctrls.perBankRdBursts::12 1768
+system.mem_ctrls.perBankRdBursts::13 891
+system.mem_ctrls.perBankRdBursts::14 2177
+system.mem_ctrls.perBankRdBursts::15 5017
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system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
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system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
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system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
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-system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00%
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system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
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system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
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-system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00%
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-system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.030580 # Average number of messages in buffer
-system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses
-system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.999599 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.065339 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061161 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999918 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999657 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999931 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.091740 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers07.avg_stall_time 6.755068 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 7.645070
-system.ruby.network.routers0.msg_count.Control::2 97760
-system.ruby.network.routers0.msg_count.Data::2 97756
-system.ruby.network.routers0.msg_count.Response_Data::4 97760
-system.ruby.network.routers0.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers0.msg_bytes.Control::2 782080
-system.ruby.network.routers0.msg_bytes.Data::2 7038432
-system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time 10.755059 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999887 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999978 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 7.645070
-system.ruby.network.routers1.msg_count.Control::2 97760
-system.ruby.network.routers1.msg_count.Data::2 97756
-system.ruby.network.routers1.msg_count.Response_Data::4 97760
-system.ruby.network.routers1.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers1.msg_bytes.Control::2 782080
-system.ruby.network.routers1.msg_bytes.Data::2 7038432
-system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030580 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 7.755066 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.int_link_buffers08.avg_stall_time 2.999830 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.int_link_buffers09.avg_stall_time 2.999967 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.int_link_buffers13.avg_stall_time 4.999715 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.int_link_buffers14.avg_stall_time 4.999943 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030580 # Average number of messages in buffer
-system.ruby.network.int_link_buffers17.avg_stall_time 9.755062 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999773 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015290 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999955 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030580 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers07.avg_stall_time 8.755064 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 7.645070
-system.ruby.network.routers2.msg_count.Control::2 97760
-system.ruby.network.routers2.msg_count.Data::2 97756
-system.ruby.network.routers2.msg_count.Response_Data::4 97760
-system.ruby.network.routers2.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers2.msg_bytes.Control::2 782080
-system.ruby.network.routers2.msg_bytes.Data::2 7038432
-system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 293280
-system.ruby.network.msg_count.Data 293268
-system.ruby.network.msg_count.Response_Data 293280
-system.ruby.network.msg_count.Writeback_Control 293268
-system.ruby.network.msg_byte.Control 2346240
-system.ruby.network.msg_byte.Data 21115296
-system.ruby.network.msg_byte.Response_Data 21116160
-system.ruby.network.msg_byte.Writeback_Control 2346144
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 7.645195
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048
-system.ruby.network.routers0.throttle1.link_utilization 7.644945
-system.ruby.network.routers0.throttle1.msg_count.Control::2 97760
-system.ruby.network.routers0.throttle1.msg_count.Data::2 97756
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432
-system.ruby.network.routers1.throttle0.link_utilization 7.644945
-system.ruby.network.routers1.throttle0.msg_count.Control::2 97760
-system.ruby.network.routers1.throttle0.msg_count.Data::2 97756
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432
-system.ruby.network.routers1.throttle1.link_utilization 7.645195
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048
-system.ruby.network.routers2.throttle0.link_utilization 7.645195
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048
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-system.ruby.network.routers2.throttle1.msg_count.Control::2 97760
-system.ruby.network.routers2.throttle1.msg_count.Data::2 97756
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432
-system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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+system.ruby.miss_latency_hist_seqr::stdev 37.111044
+system.ruby.miss_latency_hist_seqr | 54824 46.60% 46.60% | 58473 49.70% 96.31% | 3023 2.56% 98.88% | 487 0.41% 99.30% | 421 0.35% 99.65% | 338 0.28% 99.94% | 32 0.02% 99.97% | 14 0.01% 99.98% | 4 0.00% 99.98% | 13 0.01% 99.99%
+system.ruby.miss_latency_hist_seqr::total 117629
+system.ruby.Directory.incomplete_times_seqr 117628
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+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 8234747
+system.ruby.memctrl_clk_domain.clock 3
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+system.ruby.delayVCHist.vnet_1 | 117629 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.delayVCHist.vnet_2::max_bucket 9
+system.ruby.delayVCHist.vnet_2::samples 117625
+system.ruby.delayVCHist.vnet_2 | 117625 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
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-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450
-system.ruby.Directory_Controller.GETX 97760 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46242
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 68.355758
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.220522
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.646033
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 12541 27.12% 27.12% | 31422 67.95% 95.07% | 1588 3.43% 98.50% | 243 0.52% 99.03% | 220 0.47% 99.50% | 198 0.42% 99.93% | 19 0.04% 99.97% | 8 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46242
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 39
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 42.128205
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 35.627366
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 48.398118
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 36 92.30% 92.30% | 2 5.12% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 0 0.00% 97.43% | 1 2.56% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 39
+system.ruby.Directory_Controller.GETX 117629 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 117625 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 117629 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 117625 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 117629 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 117625 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 117629 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 117625 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 108386 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 510404 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 68782 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 117629 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 117625 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 117625 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 53690 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 46242 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 17697 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 54696 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 464162 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 51085 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 117625 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 117625 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 99932 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 17697 0.00% 0.00%
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:31
-gem5 executing on zizzer, pid 34073
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:34
+gem5 executing on boldrock, pid 1863
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
fld: PASS
fsd: PASS
fmadd.d: PASS
fcvt.w.d, 0.0: PASS
fcvt.w.d, -0.0: PASS
fcvt.w.d, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 497165500 because target called exit()
+fcvt.w.d, underflow: PASS
+fcvt.w.d, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, -infinity: PASS
+fcvt.w.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.wu.d, truncate positive: PASS
+fcvt.wu.d, truncate negative: PASS
+fcvt.wu.d, 0.0: PASS
+fcvt.wu.d, -0.0: PASS
+fcvt.wu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, underflow: PASS
+fcvt.wu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, -infinity: PASS
+fcvt.wu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.d, signaling NaN: PASS
+fcvt.d.w, 0: PASS
+fcvt.d.w, negative: PASS
+fcvt.d.w, truncate: PASS
+fcvt.d.wu, 0: PASS
+fcvt.d.wu: PASS
+fcvt.d.wu, truncate: PASS
+fcvt.l.d, truncate positive: PASS
+fcvt.l.d, truncate negative: PASS
+fcvt.l.d, 0.0: PASS
+fcvt.l.d, -0.0: PASS
+fcvt.l.d, 32-bit overflow: PASS
+fcvt.l.d, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, underflow: PASS
+fcvt.l.d, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, -infinity: PASS
+fcvt.l.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.d, signaling NaN: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.lu.d, truncate positive: PASS
+fcvt.lu.d, truncate negative: PASS
+fcvt.lu.d, 0.0: PASS
+fcvt.lu.d, -0.0: PASS
+fcvt.lu.d, 32-bit overflow: PASS
+fcvt.lu.d, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, underflow: PASS
+fcvt.lu.d, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.d, -infinity: PASS
+fcvt.lu.d, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.d, signaling NaN: PASS
+fmv.x.d, positive: PASS
+fmv.x.d, negative: PASS
+fmv.x.d, 0.0: PASS
+fmv.x.d, -0.0: PASS
+fcvt.d.l, 0: PASS
+fcvt.d.l, negative: PASS
+fcvt.d.l, 32-bit truncate: PASS
+fcvt.d.lu, 0: PASS
+fcvt.d.lu: PASS
+fcvt.d.lu, 32-bit truncate: PASS
+fmv.d.x: PASS
+Exiting @ tick 787032500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000497 # Number of seconds simulated
-sim_ticks 497165500 # Number of ticks simulated
-final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27513 # Simulator instruction rate (inst/s)
-host_op_rate 27513 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45717681 # Simulator tick rate (ticks/s)
-host_mem_usage 243824 # Number of bytes of host memory used
-host_seconds 10.87 # Real time elapsed on the host
-sim_insts 299191 # Number of instructions simulated
-sim_ops 299191 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81984 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 162 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 994331 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 299191 # Number of instructions committed
-system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
-system.cpu.num_func_calls 21816 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
-system.cpu.num_int_insts 299008 # number of integer instructions
-system.cpu.num_fp_insts 1025 # number of float instructions
-system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
-system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
-system.cpu.num_mem_refs 118390 # number of memory refs
-system.cpu.num_load_insts 69843 # Number of load instructions
-system.cpu.num_store_insts 48547 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 994331 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 66377 # Number of branches fetched
-system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
-system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
-system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
-system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
-system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
-system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
-system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
-system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 299354 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 258.453748 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 118073 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 316 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 373.648734 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 258.453748 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.063099 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.063099 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id
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-system.cpu.l2cache.overall_mshr_miss_latency::total 64691000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.518135 # average ReadCleanReq mshr miss latency
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-system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution
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---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:32
-gem5 executing on zizzer, pid 34076
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:58
+gem5 executing on boldrock, pid 1989
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 270200000 because target called exit()
+fcvt.w.s, underflow: PASS
+fcvt.w.s, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.s, -infinity: PASS
+fcvt.w.s, quiet NaN: PASS
+fcvt.w.s, quiet -NaN: PASS
+fcvt.w.s, signaling NaN: PASS
+fcvt.wu.s, truncate positive: PASS
+fcvt.wu.s, truncate negative: PASS
+fcvt.wu.s, 0.0: PASS
+fcvt.wu.s, -0.0: PASS
+fcvt.wu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, underflow: PASS
+fcvt.wu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, -infinity: PASS
+fcvt.wu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, signaling NaN: PASS
+fmv.x.s, positive: PASS
+fmv.x.s, negative: PASS
+fmv.x.s, 0.0: PASS
+fmv.x.s, -0.0: PASS
+feq.s, equal: PASS
+feq.s, not equal: PASS
+feq.s, 0 == -0: PASS
+feq.s, quiet NaN first: PASS
+feq.s, quiet NaN second: PASS
+feq.s, quiet NaN both: PASS
+feq.s, signaling NaN first: PASS
+feq.s, signaling NaN second: PASS
+feq.s, signaling NaN both: PASS
+flt.s, equal: PASS
+flt.s, less: PASS
+flt.s, greater: PASS
+flt.s, quiet NaN first: PASS
+flt.s, quiet NaN second: PASS
+flt.s, quiet NaN both: PASS
+flt.s, signaling NaN first: PASS
+flt.s, signaling NaN second: PASS
+flt.s, signaling NaN both: PASS
+fle.s, equal: PASS
+fle.s, less: PASS
+fle.s, greater: PASS
+fle.s, 0 == -0: PASS
+fle.s, quiet NaN first: PASS
+fle.s, quiet NaN second: PASS
+fle.s, quiet NaN both: PASS
+fle.s, signaling NaN first: PASS
+fle.s, signaling NaN second: PASS
+fle.s, signaling NaN both: PASS
+fclass.s, -infinity: PASS
+fclass.s, -normal: PASS
+fclass.s, -subnormal: PASS
+fclass.s, -0.0: PASS
+fclass.s, 0.0: PASS
+fclass.s, subnormal: PASS
+fclass.s, normal: PASS
+fclass.s, infinity: PASS
+fclass.s, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.s.w, 0: PASS
+fcvt.s.w, negative: PASS
+fcvt.s.w, truncate: PASS
+fcvt.s.wu, 0: PASS
+fcvt.s.wu: PASS
+fcvt.s.wu, truncate: PASS
+fmv.s.x: PASS
+fmv.s.x, truncate: PASS
+fsrm: PASS
+fsflags: PASS
+fscsr: PASS
+restore initial round mode: PASS
+fcvt.l.s, truncate positive: PASS
+fcvt.l.s, truncate negative: PASS
+fcvt.l.s, 0.0: PASS
+fcvt.l.s, -0.0: PASS
+fcvt.l.s, 32-bit overflow: PASS
+fcvt.l.s, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, underflow: PASS
+fcvt.l.s, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, -infinity: PASS
+fcvt.l.s, quiet NaN: PASS
+fcvt.l.s, quiet -NaN: PASS
+fcvt.l.s, signaling NaN: PASS
+fcvt.lu.s, truncate positive: PASS
+fcvt.lu.s, truncate negative: PASS
+fcvt.lu.s, 0.0: PASS
+fcvt.lu.s, -0.0: PASS
+fcvt.lu.s, 32-bit overflow: PASS
+fcvt.lu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, underflow: PASS
+fcvt.lu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, -infinity: PASS
+fcvt.lu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, signaling NaN: PASS
+fcvt.s.l, 0: PASS
+fcvt.s.l, negative: PASS
+fcvt.s.l, 32-bit truncate: PASS
+fcvt.s.lu, 0: PASS
+fcvt.s.lu: PASS
+fcvt.s.lu, 32-bit truncate: PASS
+Exiting @ tick 414261500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000270 # Number of seconds simulated
-sim_ticks 269998000 # Number of ticks simulated
-final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 216821 # Simulator instruction rate (inst/s)
-host_op_rate 216819 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 258712153 # Simulator tick rate (ticks/s)
-host_mem_usage 263004 # Number of bytes of host memory used
-host_seconds 1.04 # Real time elapsed on the host
-sim_insts 226275 # Number of instructions simulated
-sim_ops 226275 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory
-system.physmem.bytes_read::total 86336 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1349 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 173 # Per bank write bursts
-system.physmem.perBankRdBursts::1 19 # Per bank write bursts
-system.physmem.perBankRdBursts::2 18 # Per bank write bursts
-system.physmem.perBankRdBursts::3 76 # Per bank write bursts
-system.physmem.perBankRdBursts::4 196 # Per bank write bursts
-system.physmem.perBankRdBursts::5 259 # Per bank write bursts
-system.physmem.perBankRdBursts::6 19 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4 # Per bank write bursts
-system.physmem.perBankRdBursts::8 26 # Per bank write bursts
-system.physmem.perBankRdBursts::9 99 # Per bank write bursts
-system.physmem.perBankRdBursts::10 157 # Per bank write bursts
-system.physmem.perBankRdBursts::11 158 # Per bank write bursts
-system.physmem.perBankRdBursts::12 48 # Per bank write bursts
-system.physmem.perBankRdBursts::13 47 # Per bank write bursts
-system.physmem.perBankRdBursts::14 17 # Per bank write bursts
-system.physmem.perBankRdBursts::15 33 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 269757000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1349 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation
-system.physmem.totQLat 15217250 # Total ticks spent queuing
-system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 2.50 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 1101 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 199968.12 # Average gap between requests
-system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ)
-system.physmem_0.averagePower 549.494877 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states
-system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ)
-system.physmem_1.averagePower 541.901675 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 61459 # Number of BP lookups
-system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 29463 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 115 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 539996 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 226275 # Number of instructions committed
-system.cpu.committedOps 226275 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 2.386459 # CPI: cycles per instruction
-system.cpu.ipc 0.419031 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction
-system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction
-system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 226275 # Class of committed instruction
-system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits
-system.cpu.dcache.overall_hits::total 90016 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
-system.cpu.dcache.overall_misses::total 499 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 197 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 197 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 197 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 197 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 69 # number of replacements
-system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 206433 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits
-system.cpu.icache.overall_hits::total 101640 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses
-system.cpu.icache.overall_misses::total 1051 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency
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-system.cpu.icache.writebacks::total 69 # number of writebacks
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-system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
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-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses
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-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits
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-system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
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-system.cpu.l2cache.demand_hits::total 4 # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses
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-system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1349 # number of overall misses
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles
-system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency
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-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1144 # Transaction distribution
-system.membus.trans_dist::ReadExReq 205 # Transaction distribution
-system.membus.trans_dist::ReadExResp 205 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1349 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1349 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.6 # Layer utilization (%)
+sim_seconds 0.000414
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+system.physmem.bytesPerActivate::stdev 254.300651
+system.physmem.bytesPerActivate::0-127 93 23.36% 23.36%
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+system.physmem.bytesPerActivate::256-383 64 16.08% 69.09%
+system.physmem.bytesPerActivate::384-511 48 12.06% 81.15%
+system.physmem.bytesPerActivate::512-639 28 7.03% 88.19%
+system.physmem.bytesPerActivate::640-767 16 4.02% 92.21%
+system.physmem.bytesPerActivate::768-895 8 2.01% 94.22%
+system.physmem.bytesPerActivate::896-1023 7 1.75% 95.97%
+system.physmem.bytesPerActivate::1024-1151 16 4.02% 99.99%
+system.physmem.bytesPerActivate::total 398
+system.physmem.totQLat 24652500
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+system.physmem.totBusLat 9345000
+system.physmem.avgQLat 13190.20
+system.physmem.avgBusLat 5000.00
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+system.physmem.avgRdBW 288.74
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 288.74
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
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+system.physmem.busUtilRead 2.25
+system.physmem.busUtilWrite 0.00
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+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1463
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 78.27
+system.physmem.writeRowHitRate nan
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+system.physmem.pageHitRate 78.27
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+system.physmem_0.prePowerDownEnergy 4636320
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+system.physmem_1.prePowerDownEnergy 13950720
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+system.cpu.op_class_0::IprAccess 0 0.00% 99.99%
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+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 414261500
+system.membus.trans_dist::ReadResp 1643
+system.membus.trans_dist::ReadExReq 226
+system.membus.trans_dist::ReadExResp 226
+system.membus.trans_dist::ReadSharedReq 1643
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738
+system.membus.pkt_count::total 3738
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616
+system.membus.pkt_size::total 119616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1869
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1869 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1869
+system.membus.reqLayer0.occupancy 2188500
+system.membus.reqLayer0.utilization 0.5
+system.membus.respLayer1.occupancy 9936000
+system.membus.respLayer1.utilization 2.3
---------- End Simulation Statistics ----------
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
+numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
+wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
"decodeToFetchDelay": 1,
"renameWidth": 8,
"numThreads": 1,
+ "syscallRetryLatency": 10000,
"squashWidth": 8,
"function_trace": false,
"backComSize": 5,
"switched_out": false,
"smtLSQPolicy": "Partitioned",
"fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"smtROBThreshold": 100,
"issueWidth": 8,
"LSQCheckLoads": true,
"commitToRenameDelay": 1,
- "cachePorts": 200,
"system": "system",
"checker": null,
"numPhysFloatRegs": 256,
"default_p_state": "UNDEFINED",
"type": "DerivO3CPU",
"wbWidth": 8,
+ "numPhysVecRegs": 256,
"interrupts": [
{
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:32
-gem5 executing on zizzer, pid 34077
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1347
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 113397000 because target called exit()
+fcvt.w.s, underflow: PASS
+fcvt.w.s, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.s, -infinity: PASS
+fcvt.w.s, quiet NaN: PASS
+fcvt.w.s, quiet -NaN: PASS
+fcvt.w.s, signaling NaN: PASS
+fcvt.wu.s, truncate positive: PASS
+fcvt.wu.s, truncate negative: PASS
+fcvt.wu.s, 0.0: PASS
+fcvt.wu.s, -0.0: PASS
+fcvt.wu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, underflow: PASS
+fcvt.wu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, -infinity: PASS
+fcvt.wu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, signaling NaN: PASS
+fmv.x.s, positive: PASS
+fmv.x.s, negative: PASS
+fmv.x.s, 0.0: PASS
+fmv.x.s, -0.0: PASS
+feq.s, equal: PASS
+feq.s, not equal: PASS
+feq.s, 0 == -0: PASS
+feq.s, quiet NaN first: PASS
+feq.s, quiet NaN second: PASS
+feq.s, quiet NaN both: PASS
+feq.s, signaling NaN first: PASS
+feq.s, signaling NaN second: PASS
+feq.s, signaling NaN both: PASS
+flt.s, equal: PASS
+flt.s, less: PASS
+flt.s, greater: PASS
+flt.s, quiet NaN first: PASS
+flt.s, quiet NaN second: PASS
+flt.s, quiet NaN both: PASS
+flt.s, signaling NaN first: PASS
+flt.s, signaling NaN second: PASS
+flt.s, signaling NaN both: PASS
+fle.s, equal: PASS
+fle.s, less: PASS
+fle.s, greater: PASS
+fle.s, 0 == -0: PASS
+fle.s, quiet NaN first: PASS
+fle.s, quiet NaN second: PASS
+fle.s, quiet NaN both: PASS
+fle.s, signaling NaN first: PASS
+fle.s, signaling NaN second: PASS
+fle.s, signaling NaN both: PASS
+fclass.s, -infinity: PASS
+fclass.s, -normal: PASS
+fclass.s, -subnormal: PASS
+fclass.s, -0.0: PASS
+fclass.s, 0.0: PASS
+fclass.s, subnormal: PASS
+fclass.s, normal: PASS
+fclass.s, infinity: PASS
+fclass.s, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.s.w, 0: PASS
+fcvt.s.w, negative: PASS
+fcvt.s.w, truncate: PASS
+fcvt.s.wu, 0: PASS
+fcvt.s.wu: PASS
+fcvt.s.wu, truncate: PASS
+fmv.s.x: PASS
+fmv.s.x, truncate: PASS
+fsrm: PASS
+fsflags: PASS
+fscsr: PASS
+restore initial round mode: PASS
+fcvt.l.s, truncate positive: PASS
+fcvt.l.s, truncate negative: PASS
+fcvt.l.s, 0.0: PASS
+fcvt.l.s, -0.0: PASS
+fcvt.l.s, 32-bit overflow: PASS
+fcvt.l.s, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, underflow: PASS
+fcvt.l.s, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, -infinity: PASS
+fcvt.l.s, quiet NaN: PASS
+fcvt.l.s, quiet -NaN: PASS
+fcvt.l.s, signaling NaN: PASS
+fcvt.lu.s, truncate positive: PASS
+fcvt.lu.s, truncate negative: PASS
+fcvt.lu.s, 0.0: PASS
+fcvt.lu.s, -0.0: PASS
+fcvt.lu.s, 32-bit overflow: PASS
+fcvt.lu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, underflow: PASS
+fcvt.lu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, -infinity: PASS
+fcvt.lu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, signaling NaN: PASS
+fcvt.s.l, 0: PASS
+fcvt.s.l, negative: PASS
+fcvt.s.l, 32-bit truncate: PASS
+fcvt.s.lu, 0: PASS
+fcvt.s.lu: PASS
+fcvt.s.lu, 32-bit truncate: PASS
+Exiting @ tick 334241000 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000113 # Number of seconds simulated
-sim_ticks 113383000 # Number of ticks simulated
-final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 167766 # Simulator instruction rate (inst/s)
-host_op_rate 167765 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 84106882 # Simulator tick rate (ticks/s)
-host_mem_usage 263760 # Number of bytes of host memory used
-host_seconds 1.35 # Real time elapsed on the host
-sim_insts 226159 # Number of instructions simulated
-sim_ops 226159 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory
-system.physmem.bytes_read::total 85184 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1331 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 174 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18 # Per bank write bursts
-system.physmem.perBankRdBursts::2 15 # Per bank write bursts
-system.physmem.perBankRdBursts::3 82 # Per bank write bursts
-system.physmem.perBankRdBursts::4 194 # Per bank write bursts
-system.physmem.perBankRdBursts::5 254 # Per bank write bursts
-system.physmem.perBankRdBursts::6 22 # Per bank write bursts
-system.physmem.perBankRdBursts::7 4 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25 # Per bank write bursts
-system.physmem.perBankRdBursts::9 103 # Per bank write bursts
-system.physmem.perBankRdBursts::10 150 # Per bank write bursts
-system.physmem.perBankRdBursts::11 145 # Per bank write bursts
-system.physmem.perBankRdBursts::12 50 # Per bank write bursts
-system.physmem.perBankRdBursts::13 52 # Per bank write bursts
-system.physmem.perBankRdBursts::14 14 # Per bank write bursts
-system.physmem.perBankRdBursts::15 29 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 113277000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1331 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation
-system.physmem.totQLat 17606250 # Total ticks spent queuing
-system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 5.87 # Data bus utilization in percentage
-system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 1107 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 85106.69 # Average gap between requests
-system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ)
-system.physmem_0.averagePower 587.773777 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states
-system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ)
-system.physmem_1.averagePower 574.889920 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 78097 # Number of BP lookups
-system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 36130 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 115 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 226767 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 70228 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 68810 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 133 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 261550 # Type of FU issued
-system.cpu.iq.rate 1.153387 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 98069 # number of memory reference insts executed
-system.cpu.iew.exec_branches 57083 # Number of branches executed
-system.cpu.iew.exec_stores 39720 # Number of stores executed
-system.cpu.iew.exec_rate 1.120286 # Inst execution rate
-system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 250950 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 95653 # num instructions producing a value
-system.cpu.iew.wb_consumers 131997 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 226159 # Number of instructions committed
-system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 88940 # Number of memory references committed
-system.cpu.commit.loads 51711 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 50405 # Number of branches committed
-system.cpu.commit.fp_insts 862 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 225991 # Number of committed integer instructions.
-system.cpu.commit.function_calls 16616 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 226159 # Class of committed instruction
-system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 423217 # The number of ROB reads
-system.cpu.rob.rob_writes 556357 # The number of ROB writes
-system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 226159 # Number of Instructions Simulated
-system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 329254 # number of integer regfile reads
-system.cpu.int_regfile_writes 174794 # number of integer regfile writes
-system.cpu.fp_regfile_reads 878 # number of floating regfile reads
-system.cpu.fp_regfile_writes 754 # number of floating regfile writes
-system.cpu.misc_regfile_reads 446 # number of misc regfile reads
-system.cpu.misc_regfile_writes 313 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits
-system.cpu.dcache.overall_hits::total 87565 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses
-system.cpu.dcache.overall_misses::total 1935 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003363 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003363 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88108.247423 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88108.247423 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84345.588235 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84345.588235 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 70 # number of replacements
-system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 122053 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 122053 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 59155 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 59155 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 59155 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 59155 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 59155 # number of overall hits
-system.cpu.icache.overall_hits::total 59155 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1354 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1354 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses
-system.cpu.icache.overall_misses::total 1354 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 70 # number of writebacks
-system.cpu.icache.writebacks::total 70 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1035 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1035 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1035 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1035 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86827498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 86827498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86827498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 86827498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1030 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 1030 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 1331 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1030 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1331 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 16900000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85245000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 85245000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8401000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 8401000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 85245000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 25301000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 110546000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 85245000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 25301000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 110546000 # number of overall miss cycles
-system.cpu.l2cache.WritebackClean_accesses::writebacks 70 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 70 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1333 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1333 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998062 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998062 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998062 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.998500 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998062 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.998500 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82843.137255 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82843.137255 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82762.135922 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82762.135922 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86608.247423 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86608.247423 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83054.845980 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83054.845980 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1030 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1030 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1331 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 3 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1127 # Transaction distribution
-system.membus.trans_dist::ReadExReq 204 # Transaction distribution
-system.membus.trans_dist::ReadExResp 204 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1331 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1331 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
+sim_seconds 0.000334
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+final_tick 334241000
+sim_freq 1000000000000
+host_inst_rate 3258
+host_op_rate 3268
+host_tick_rate 2618086
+host_mem_usage 272352
+host_seconds 127.66
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+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 334241000
+system.physmem.bytes_read::cpu.inst 79616
+system.physmem.bytes_read::cpu.data 34432
+system.physmem.bytes_read::total 114048
+system.physmem.bytes_inst_read::cpu.inst 79616
+system.physmem.bytes_inst_read::total 79616
+system.physmem.num_reads::cpu.inst 1244
+system.physmem.num_reads::cpu.data 538
+system.physmem.num_reads::total 1782
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+system.physmem.bw_inst_read::cpu.inst 238199383
+system.physmem.bw_inst_read::total 238199383
+system.physmem.bw_total::cpu.inst 238199383
+system.physmem.bw_total::cpu.data 103015488
+system.physmem.bw_total::total 341214871
+system.physmem.readReqs 1782
+system.physmem.writeReqs 0
+system.physmem.readBursts 1782
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 114048
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 114048
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 238
+system.physmem.perBankRdBursts::1 261
+system.physmem.perBankRdBursts::2 164
+system.physmem.perBankRdBursts::3 171
+system.physmem.perBankRdBursts::4 146
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+system.physmem.perBankRdBursts::7 59
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+system.physmem.perBankRdBursts::10 21
+system.physmem.perBankRdBursts::11 42
+system.physmem.perBankRdBursts::12 76
+system.physmem.perBankRdBursts::13 78
+system.physmem.perBankRdBursts::14 92
+system.physmem.perBankRdBursts::15 118
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
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+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 334109500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1782
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+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1136
+system.physmem.rdQLenPdf::1 450
+system.physmem.rdQLenPdf::2 141
+system.physmem.rdQLenPdf::3 42
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+system.physmem.rdQLenPdf::24 0
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+system.physmem.rdQLenPdf::31 0
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+system.physmem.wrQLenPdf::3 0
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+system.physmem.wrQLenPdf::6 0
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+system.physmem.wrQLenPdf::8 0
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+system.physmem.wrQLenPdf::38 0
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+system.physmem.wrQLenPdf::43 0
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+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
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+system.physmem.wrQLenPdf::52 0
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+system.physmem.wrQLenPdf::54 0
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+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 400
+system.physmem.bytesPerActivate::mean 278.239999
+system.physmem.bytesPerActivate::gmean 189.218763
+system.physmem.bytesPerActivate::stdev 254.162780
+system.physmem.bytesPerActivate::0-127 113 28.24% 28.24%
+system.physmem.bytesPerActivate::128-255 118 29.49% 57.74%
+system.physmem.bytesPerActivate::256-383 52 12.99% 70.74%
+system.physmem.bytesPerActivate::384-511 42 10.49% 81.24%
+system.physmem.bytesPerActivate::512-639 33 8.24% 89.49%
+system.physmem.bytesPerActivate::640-767 10 2.49% 91.99%
+system.physmem.bytesPerActivate::768-895 7 1.74% 93.74%
+system.physmem.bytesPerActivate::896-1023 11 2.74% 96.49%
+system.physmem.bytesPerActivate::1024-1151 14 3.49% 99.99%
+system.physmem.bytesPerActivate::total 400
+system.physmem.totQLat 28596250
+system.physmem.totMemAccLat 62008750
+system.physmem.totBusLat 8910000
+system.physmem.avgQLat 16047.27
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 34797.27
+system.physmem.avgRdBW 341.21
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 341.21
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 2.66
+system.physmem.busUtilRead 2.66
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.38
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1368
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 76.76
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 187491.30
+system.physmem.pageHitRate 76.76
+system.physmem_0.actEnergy 1927800
+system.physmem_0.preEnergy 998085
+system.physmem_0.readEnergy 8882160
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 25814880
+system.physmem_0.actBackEnergy 18293580
+system.physmem_0.preBackEnergy 540000
+system.physmem_0.actPowerDownEnergy 129050280
+system.physmem_0.prePowerDownEnergy 3729600
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 189236385
+system.physmem_0.averagePower 566.167057
+system.physmem_0.totalIdleTime 292641750
+system.physmem_0.memoryStateTime::IDLE 245500
+system.physmem_0.memoryStateTime::REF 10920000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 9705500
+system.physmem_0.memoryStateTime::ACT 30338500
+system.physmem_0.memoryStateTime::ACT_PDN 283031500
+system.physmem_1.actEnergy 1028160
+system.physmem_1.preEnergy 519915
+system.physmem_1.readEnergy 3841320
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 11678160
+system.physmem_1.actBackEnergy 8555700
+system.physmem_1.preBackEnergy 555360
+system.physmem_1.actPowerDownEnergy 38406030
+system.physmem_1.prePowerDownEnergy 10018560
+system.physmem_1.selfRefreshEnergy 50549220
+system.physmem_1.totalEnergy 125152425
+system.physmem_1.averagePower 374.437401
+system.physmem_1.totalIdleTime 313185500
+system.physmem_1.memoryStateTime::IDLE 973000
+system.physmem_1.memoryStateTime::REF 4958000
+system.physmem_1.memoryStateTime::SREF 203719000
+system.physmem_1.memoryStateTime::PRE_PDN 26090000
+system.physmem_1.memoryStateTime::ACT 14271500
+system.physmem_1.memoryStateTime::ACT_PDN 84229500
+system.pwrStateResidencyTicks::UNDEFINED 334241000
+system.cpu.branchPred.lookups 127435
+system.cpu.branchPred.condPredicted 89833
+system.cpu.branchPred.condIncorrect 23395
+system.cpu.branchPred.BTBLookups 81108
+system.cpu.branchPred.BTBHits 45160
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 55.678847
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 25902
+system.cpu.branchPred.indirectHits 14811
+system.cpu.branchPred.indirectMisses 11091
+system.cpu.branchPredindirectMispredicted 5072
+system.cpu_clk_domain.clock 500
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+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
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+system.cpu.numWorkItemsCompleted 0
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+system.cpu.fetch.rateDist::stdev 0.982669
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+system.cpu.fetch.rateDist::0 163182 28.94% 28.94%
+system.cpu.fetch.rateDist::1 291750 51.75% 80.69%
+system.cpu.fetch.rateDist::2 72803 12.91% 93.61%
+system.cpu.fetch.rateDist::3 20031 3.55% 97.16%
+system.cpu.fetch.rateDist::4 9935 1.76% 98.92%
+system.cpu.fetch.rateDist::5 3180 0.56% 99.49%
+system.cpu.fetch.rateDist::6 1981 0.35% 99.84%
+system.cpu.fetch.rateDist::7 355 0.06% 99.90%
+system.cpu.fetch.rateDist::8 526 0.09% 99.99%
+system.cpu.fetch.rateDist::overflows 0 0.00% 99.99%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::total 563743
+system.cpu.fetch.branchRate 0.190633
+system.cpu.fetch.rate 0.853239
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+system.cpu.decode.BlockedCycles 50036
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+system.cpu.decode.UnblockCycles 2505
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+system.cpu.rename.SQFullEvents 3460
+system.cpu.rename.RenamedOperands 337685
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+system.cpu.rename.tempSerializingInsts 1943
+system.cpu.rename.skidInsts 3831
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+system.cpu.memDep0.conflictingLoads 532
+system.cpu.memDep0.conflictingStores 153
+system.cpu.iq.iqInstsAdded 466229
+system.cpu.iq.iqNonSpecInstsAdded 3274
+system.cpu.iq.iqInstsIssued 459327
+system.cpu.iq.iqSquashedInstsIssued 175
+system.cpu.iq.iqSquashedInstsExamined 52219
+system.cpu.iq.iqSquashedOperandsExamined 23838
+system.cpu.iq.iqSquashedNonSpecRemoved 88
+system.cpu.iq.issued_per_cycle::samples 563743
+system.cpu.iq.issued_per_cycle::mean 0.814780
+system.cpu.iq.issued_per_cycle::stdev 0.900911
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 233488 41.41% 41.41%
+system.cpu.iq.issued_per_cycle::1 239164 42.42% 83.84%
+system.cpu.iq.issued_per_cycle::2 63723 11.30% 95.14%
+system.cpu.iq.issued_per_cycle::3 22016 3.90% 99.05%
+system.cpu.iq.issued_per_cycle::4 2579 0.45% 99.50%
+system.cpu.iq.issued_per_cycle::5 1083 0.19% 99.70%
+system.cpu.iq.issued_per_cycle::6 919 0.16% 99.86%
+system.cpu.iq.issued_per_cycle::7 744 0.13% 99.99%
+system.cpu.iq.issued_per_cycle::8 27 0.00% 99.99%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 99.99%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 8
+system.cpu.iq.issued_per_cycle::total 563743
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 39 2.95% 2.95%
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.95%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.95%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.95%
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+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.95%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.95%
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+system.membus.snoops 0
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+system.membus.snoop_fanout::stdev -0
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---------- End Simulation Statistics ----------
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:33
-gem5 executing on zizzer, pid 34079
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:10
+gem5 executing on boldrock, pid 1746
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 113137000 because target called exit()
+fcvt.w.s, underflow: PASS
+fcvt.w.s, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.s, -infinity: PASS
+fcvt.w.s, quiet NaN: PASS
+fcvt.w.s, quiet -NaN: PASS
+fcvt.w.s, signaling NaN: PASS
+fcvt.wu.s, truncate positive: PASS
+fcvt.wu.s, truncate negative: PASS
+fcvt.wu.s, 0.0: PASS
+fcvt.wu.s, -0.0: PASS
+fcvt.wu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, underflow: PASS
+fcvt.wu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, -infinity: PASS
+fcvt.wu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, signaling NaN: PASS
+fmv.x.s, positive: PASS
+fmv.x.s, negative: PASS
+fmv.x.s, 0.0: PASS
+fmv.x.s, -0.0: PASS
+feq.s, equal: PASS
+feq.s, not equal: PASS
+feq.s, 0 == -0: PASS
+feq.s, quiet NaN first: PASS
+feq.s, quiet NaN second: PASS
+feq.s, quiet NaN both: PASS
+feq.s, signaling NaN first: PASS
+feq.s, signaling NaN second: PASS
+feq.s, signaling NaN both: PASS
+flt.s, equal: PASS
+flt.s, less: PASS
+flt.s, greater: PASS
+flt.s, quiet NaN first: PASS
+flt.s, quiet NaN second: PASS
+flt.s, quiet NaN both: PASS
+flt.s, signaling NaN first: PASS
+flt.s, signaling NaN second: PASS
+flt.s, signaling NaN both: PASS
+fle.s, equal: PASS
+fle.s, less: PASS
+fle.s, greater: PASS
+fle.s, 0 == -0: PASS
+fle.s, quiet NaN first: PASS
+fle.s, quiet NaN second: PASS
+fle.s, quiet NaN both: PASS
+fle.s, signaling NaN first: PASS
+fle.s, signaling NaN second: PASS
+fle.s, signaling NaN both: PASS
+fclass.s, -infinity: PASS
+fclass.s, -normal: PASS
+fclass.s, -subnormal: PASS
+fclass.s, -0.0: PASS
+fclass.s, 0.0: PASS
+fclass.s, subnormal: PASS
+fclass.s, normal: PASS
+fclass.s, infinity: PASS
+fclass.s, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.s.w, 0: PASS
+fcvt.s.w, negative: PASS
+fcvt.s.w, truncate: PASS
+fcvt.s.wu, 0: PASS
+fcvt.s.wu: PASS
+fcvt.s.wu, truncate: PASS
+fmv.s.x: PASS
+fmv.s.x, truncate: PASS
+fsrm: PASS
+fsflags: PASS
+fscsr: PASS
+restore initial round mode: PASS
+fcvt.l.s, truncate positive: PASS
+fcvt.l.s, truncate negative: PASS
+fcvt.l.s, 0.0: PASS
+fcvt.l.s, -0.0: PASS
+fcvt.l.s, 32-bit overflow: PASS
+fcvt.l.s, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, underflow: PASS
+fcvt.l.s, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, -infinity: PASS
+fcvt.l.s, quiet NaN: PASS
+fcvt.l.s, quiet -NaN: PASS
+fcvt.l.s, signaling NaN: PASS
+fcvt.lu.s, truncate positive: PASS
+fcvt.lu.s, truncate negative: PASS
+fcvt.lu.s, 0.0: PASS
+fcvt.lu.s, -0.0: PASS
+fcvt.lu.s, 32-bit overflow: PASS
+fcvt.lu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, underflow: PASS
+fcvt.lu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, -infinity: PASS
+fcvt.lu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, signaling NaN: PASS
+fcvt.s.l, 0: PASS
+fcvt.s.l, negative: PASS
+fcvt.s.l, 32-bit truncate: PASS
+fcvt.s.lu, 0: PASS
+fcvt.s.lu: PASS
+fcvt.s.lu, 32-bit truncate: PASS
+Exiting @ tick 244411500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000113 # Number of seconds simulated
-sim_ticks 113137000 # Number of ticks simulated
-final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28615 # Simulator instruction rate (inst/s)
-host_op_rate 28615 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14314809 # Simulator tick rate (ticks/s)
-host_mem_usage 234404 # Number of bytes of host memory used
-host_seconds 7.90 # Real time elapsed on the host
-sim_insts 226159 # Number of instructions simulated
-sim_ops 226159 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 905100 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 339455 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1244555 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 905100 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 905100 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 226262 # Number of bytes written to this memory
-system.physmem.bytes_written::total 226262 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 226275 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 51711 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 277986 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 37229 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 37229 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8000035355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3000388909 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11000424264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8000035355 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8000035355 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1999893934 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1999893934 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8000035355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5000282843 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13000318198 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 115 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 226275 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 226159 # Number of instructions committed
-system.cpu.committedOps 226159 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses
-system.cpu.num_func_calls 16616 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls
-system.cpu.num_int_insts 225992 # number of integer instructions
-system.cpu.num_fp_insts 862 # number of float instructions
-system.cpu.num_int_register_reads 298589 # number of times the integer registers were read
-system.cpu.num_int_register_writes 154866 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 733 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 588 # number of times the floating registers were written
-system.cpu.num_mem_refs 88941 # number of memory refs
-system.cpu.num_load_insts 51711 # Number of load instructions
-system.cpu.num_store_insts 37230 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 226275 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 50405 # Number of branches fetched
-system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction
-system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction
-system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction
-system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction
-system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction
-system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction
-system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 226275 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 277986 # Transaction distribution
-system.membus.trans_dist::ReadResp 277986 # Transaction distribution
-system.membus.trans_dist::WriteReq 37229 # Transaction distribution
-system.membus.trans_dist::WriteResp 37229 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 452550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 177880 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630430 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 905100 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 565717 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1470817 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 315215 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 315215 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 315215 # Request fanout histogram
+sim_seconds 0.000244
+sim_ticks 244411500
+final_tick 244411500
+sim_freq 1000000000000
+host_inst_rate 4072
+host_op_rate 4084
+host_tick_rate 2392518
+host_mem_usage 259288
+host_seconds 102.15
+sim_insts 416024
+sim_ops 417277
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 244411500
+system.physmem.bytes_read::cpu.inst 1950284
+system.physmem.bytes_read::cpu.data 696743
+system.physmem.bytes_read::total 2647027
+system.physmem.bytes_inst_read::cpu.inst 1950284
+system.physmem.bytes_inst_read::total 1950284
+system.physmem.bytes_written::cpu.data 440589
+system.physmem.bytes_written::total 440589
+system.physmem.num_reads::cpu.inst 487571
+system.physmem.num_reads::cpu.data 105498
+system.physmem.num_reads::total 593069
+system.physmem.num_writes::cpu.data 64126
+system.physmem.num_writes::total 64126
+system.physmem.bw_read::cpu.inst 7979509965
+system.physmem.bw_read::cpu.data 2850696468
+system.physmem.bw_read::total 10830206434
+system.physmem.bw_inst_read::cpu.inst 7979509965
+system.physmem.bw_inst_read::total 7979509965
+system.physmem.bw_write::cpu.data 1802652493
+system.physmem.bw_write::total 1802652493
+system.physmem.bw_total::cpu.inst 7979509965
+system.physmem.bw_total::cpu.data 4653348962
+system.physmem.bw_total::total 12632858928
+system.pwrStateResidencyTicks::UNDEFINED 244411500
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 216
+system.cpu.pwrStateResidencyTicks::ON 244411500
+system.cpu.numCycles 488824
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 416024
+system.cpu.committedOps 417277
+system.cpu.num_int_alu_accesses 415220
+system.cpu.num_fp_alu_accesses 1163
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 23050
+system.cpu.num_conditional_control_insts 67806
+system.cpu.num_int_insts 415220
+system.cpu.num_fp_insts 1163
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 525251
+system.cpu.num_int_register_writes 276296
+system.cpu.num_fp_register_reads 936
+system.cpu.num_fp_register_writes 756
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 169624
+system.cpu.num_load_insts 105498
+system.cpu.num_store_insts 64126
+system.cpu.num_idle_cycles -0
+system.cpu.num_busy_cycles 488824
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction -0
+system.cpu.Branches 90856
+system.cpu.op_class::No_OpClass 236 0.05% 0.05%
+system.cpu.op_class::IntAlu 245871 58.89% 58.94%
+system.cpu.op_class::IntMult 674 0.16% 59.11%
+system.cpu.op_class::IntDiv 644 0.15% 59.26%
+system.cpu.op_class::FloatAdd 128 0.03% 59.29%
+system.cpu.op_class::FloatCmp 161 0.03% 59.33%
+system.cpu.op_class::FloatCvt 109 0.02% 59.35%
+system.cpu.op_class::FloatMult 30 0.00% 59.36%
+system.cpu.op_class::FloatMultAcc 0 0.00% 59.36%
+system.cpu.op_class::FloatDiv 11 0.00% 59.36%
+system.cpu.op_class::FloatMisc 0 0.00% 59.36%
+system.cpu.op_class::FloatSqrt 5 0.00% 59.37%
+system.cpu.op_class::SimdAdd 0 0.00% 59.37%
+system.cpu.op_class::SimdAddAcc 0 0.00% 59.37%
+system.cpu.op_class::SimdAlu 0 0.00% 59.37%
+system.cpu.op_class::SimdCmp 0 0.00% 59.37%
+system.cpu.op_class::SimdCvt 0 0.00% 59.37%
+system.cpu.op_class::SimdMisc 0 0.00% 59.37%
+system.cpu.op_class::SimdMult 0 0.00% 59.37%
+system.cpu.op_class::SimdMultAcc 0 0.00% 59.37%
+system.cpu.op_class::SimdShift 0 0.00% 59.37%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 59.37%
+system.cpu.op_class::SimdSqrt 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatMult 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.37%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.37%
+system.cpu.op_class::MemRead 104951 25.13% 84.50%
+system.cpu.op_class::MemWrite 63954 15.31% 99.82%
+system.cpu.op_class::FloatMemRead 547 0.13% 99.95%
+system.cpu.op_class::FloatMemWrite 172 0.04% 99.99%
+system.cpu.op_class::IprAccess 0 0.00% 99.99%
+system.cpu.op_class::InstPrefetch 0 0.00% 99.99%
+system.cpu.op_class::total 417493
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 244411500
+system.membus.trans_dist::ReadReq 591378
+system.membus.trans_dist::ReadResp 593069
+system.membus.trans_dist::WriteReq 62435
+system.membus.trans_dist::WriteResp 62435
+system.membus.trans_dist::LoadLockedReq 1691
+system.membus.trans_dist::StoreCondReq 1691
+system.membus.trans_dist::StoreCondResp 1691
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 975142
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 339248
+system.membus.pkt_count::total 1314390
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1950284
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1137332
+system.membus.pkt_size::total 3087616
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 657195
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev -0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 657195 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 657195
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
+addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
-transitions_per_cycle=4
+transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+addr_ranges=0:268435455:5:0:0:0
eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
+addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
- "cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
"support_data_reqs": true,
"is_cpu_sequencer": true
},
- "type": "L1Cache_Controller",
+ "cxx_class": "L1Cache_Controller",
"issue_latency": 2,
+ "type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
- "transitions_per_cycle": 4,
+ "transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
- "version": 0,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
- "type": "RubyDirectoryMemory",
- "numa_high_bit": 5,
- "size": 268435456
+ "type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:42
-gem5 executing on zizzer, pid 34083
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:34
+gem5 executing on boldrock, pid 1867
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 4665394 because target called exit()
+fcvt.w.s, underflow: PASS
+fcvt.w.s, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.s, -infinity: PASS
+fcvt.w.s, quiet NaN: PASS
+fcvt.w.s, quiet -NaN: PASS
+fcvt.w.s, signaling NaN: PASS
+fcvt.wu.s, truncate positive: PASS
+fcvt.wu.s, truncate negative: PASS
+fcvt.wu.s, 0.0: PASS
+fcvt.wu.s, -0.0: PASS
+fcvt.wu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, underflow: PASS
+fcvt.wu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, -infinity: PASS
+fcvt.wu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, signaling NaN: PASS
+fmv.x.s, positive: PASS
+fmv.x.s, negative: PASS
+fmv.x.s, 0.0: PASS
+fmv.x.s, -0.0: PASS
+feq.s, equal: PASS
+feq.s, not equal: PASS
+feq.s, 0 == -0: PASS
+feq.s, quiet NaN first: PASS
+feq.s, quiet NaN second: PASS
+feq.s, quiet NaN both: PASS
+feq.s, signaling NaN first: PASS
+feq.s, signaling NaN second: PASS
+feq.s, signaling NaN both: PASS
+flt.s, equal: PASS
+flt.s, less: PASS
+flt.s, greater: PASS
+flt.s, quiet NaN first: PASS
+flt.s, quiet NaN second: PASS
+flt.s, quiet NaN both: PASS
+flt.s, signaling NaN first: PASS
+flt.s, signaling NaN second: PASS
+flt.s, signaling NaN both: PASS
+fle.s, equal: PASS
+fle.s, less: PASS
+fle.s, greater: PASS
+fle.s, 0 == -0: PASS
+fle.s, quiet NaN first: PASS
+fle.s, quiet NaN second: PASS
+fle.s, quiet NaN both: PASS
+fle.s, signaling NaN first: PASS
+fle.s, signaling NaN second: PASS
+fle.s, signaling NaN both: PASS
+fclass.s, -infinity: PASS
+fclass.s, -normal: PASS
+fclass.s, -subnormal: PASS
+fclass.s, -0.0: PASS
+fclass.s, 0.0: PASS
+fclass.s, subnormal: PASS
+fclass.s, normal: PASS
+fclass.s, infinity: PASS
+fclass.s, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.s.w, 0: PASS
+fcvt.s.w, negative: PASS
+fcvt.s.w, truncate: PASS
+fcvt.s.wu, 0: PASS
+fcvt.s.wu: PASS
+fcvt.s.wu, truncate: PASS
+fmv.s.x: PASS
+fmv.s.x, truncate: PASS
+fsrm: PASS
+fsflags: PASS
+fscsr: PASS
+restore initial round mode: PASS
+fcvt.l.s, truncate positive: PASS
+fcvt.l.s, truncate negative: PASS
+fcvt.l.s, 0.0: PASS
+fcvt.l.s, -0.0: PASS
+fcvt.l.s, 32-bit overflow: PASS
+fcvt.l.s, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, underflow: PASS
+fcvt.l.s, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, -infinity: PASS
+fcvt.l.s, quiet NaN: PASS
+fcvt.l.s, quiet -NaN: PASS
+fcvt.l.s, signaling NaN: PASS
+fcvt.lu.s, truncate positive: PASS
+fcvt.lu.s, truncate negative: PASS
+fcvt.lu.s, 0.0: PASS
+fcvt.lu.s, -0.0: PASS
+fcvt.lu.s, 32-bit overflow: PASS
+fcvt.lu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, underflow: PASS
+fcvt.lu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, -infinity: PASS
+fcvt.lu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, signaling NaN: PASS
+fcvt.s.l, 0: PASS
+fcvt.s.l, negative: PASS
+fcvt.s.l, 32-bit truncate: PASS
+fcvt.s.lu, 0: PASS
+fcvt.s.lu: PASS
+fcvt.s.lu, 32-bit truncate: PASS
+Exiting @ tick 7772689 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.004665 # Number of seconds simulated
-sim_ticks 4665394 # Number of ticks simulated
-final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 87650 # Simulator instruction rate (inst/s)
-host_op_rate 87650 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1808106 # Simulator tick rate (ticks/s)
-host_mem_usage 429644 # Number of bytes of host memory used
-host_seconds 2.58 # Real time elapsed on the host
-sim_insts 226159 # Number of instructions simulated
-sim_ops 226159 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4623808 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 4623808 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4623552 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 4623552 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 72247 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 72247 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 72243 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 72243 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 991086283 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 991086283 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 991031411 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 991031411 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1982117695 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1982117695 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 72247 # Number of read requests accepted
-system.mem_ctrls.writeReqs 72243 # Number of write requests accepted
-system.mem_ctrls.readBursts 72247 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 72243 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 2375168 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 2248640 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 2474112 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 4623808 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 4623552 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 35135 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 33568 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 360 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 641 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 33 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 2702 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 5567 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 5413 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 5211 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 1018 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 201 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 679 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 1777 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 10251 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 1439 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 1161 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 39 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 620 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 374 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 689 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 35 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 2847 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 5733 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 5572 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 5809 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 1085 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 201 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 742 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 1831 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 10392 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 1454 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 1229 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 626 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 4665243 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 72247 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 72243 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 37112 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 208 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 255 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 2030 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 2392 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 2414 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 2512 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 2548 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 2499 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 2385 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 2380 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 2383 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 2380 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 2379 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 13232 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 366.340992 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 230.810737 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 342.245951 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 3082 23.29% 23.29% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 3681 27.82% 51.11% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 1764 13.33% 64.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 976 7.38% 71.82% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 696 5.26% 77.08% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 455 3.44% 80.52% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 307 2.32% 82.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 275 2.08% 84.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 1996 15.08% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 13232 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 2379 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.599412 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.547106 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 1.309736 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 94 3.95% 3.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 1021 42.92% 46.87% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 1131 47.54% 94.41% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 122 5.13% 99.54% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 10 0.42% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 2379 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 2379 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.249685 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.232515 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.782399 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 2139 89.91% 89.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 18 0.76% 90.67% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 109 4.58% 95.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 94 3.95% 99.20% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 19 0.80% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 2379 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 719075 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 1424203 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 185560 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 509.10 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 530.31 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 991.09 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 991.03 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 3.98 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.14 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 27462 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 35070 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 74.00 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 90.68 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 32.29 # Average gap between requests
-system.mem_ctrls.pageHitRate 82.51 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 60632880 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 32801496 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 239275680 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 184946688 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 366325440.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 608748144 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 8669568 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 1381360344 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 69824640 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 28732560 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 2981317440 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 639.028009 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 3307806 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 5774 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 155020 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 96709 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 181835 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 1196757 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 3029299 # Time in different power states
-system.mem_ctrls_1.actEnergy 33886440 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 18326952 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 184691808 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 137924928 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 348500880.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 590211744 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 11048832 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 1320078504 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 60484992 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 72883440 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 2778038520 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 595.456358 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 3342297 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 12341 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 147456 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 289875 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 157513 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 1163300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 2894909 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.cpu.clk_domain.clock 1 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 115 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 4665394 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 4665394 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 226159 # Number of instructions committed
-system.cpu.committedOps 226159 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses
-system.cpu.num_func_calls 16616 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls
-system.cpu.num_int_insts 225992 # number of integer instructions
-system.cpu.num_fp_insts 862 # number of float instructions
-system.cpu.num_int_register_reads 298589 # number of times the integer registers were read
-system.cpu.num_int_register_writes 154866 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 733 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 588 # number of times the floating registers were written
-system.cpu.num_mem_refs 88941 # number of memory refs
-system.cpu.num_load_insts 51711 # Number of load instructions
-system.cpu.num_store_insts 37230 # Number of store instructions
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-system.cpu.num_busy_cycles 4665394 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 50405 # Number of branches fetched
-system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction
-system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction
-system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction
-system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction
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-system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction
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-system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction
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-system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction
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-system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction
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-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction
-system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 226275 # Class of executed instruction
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 1 # delay histogram for all message
-system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 144490 # delay histogram for all message
-system.ruby.delayHist | 144490 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 144490 # delay histogram for all message
+sim_seconds 0.007772
+sim_ticks 7772689
+final_tick 7772689
+sim_freq 1000000000
+host_inst_rate 4127
+host_op_rate 4139
+host_tick_rate 77114
+host_mem_usage 439776
+host_seconds 100.79
+sim_insts 416024
+sim_ops 417277
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7772689
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 7083968
+system.mem_ctrls.bytes_read::total 7083968
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 7083712
+system.mem_ctrls.bytes_written::total 7083712
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 110687
+system.mem_ctrls.num_reads::total 110687
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 110683
+system.mem_ctrls.num_writes::total 110683
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 911392183
+system.mem_ctrls.bw_read::total 911392183
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 911359247
+system.mem_ctrls.bw_write::total 911359247
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1822751431
+system.mem_ctrls.bw_total::total 1822751431
+system.mem_ctrls.readReqs 110687
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+system.mem_ctrls.writeBursts 110683
+system.mem_ctrls.bytesReadDRAM 3722624
+system.mem_ctrls.bytesReadWrQ 3361344
+system.mem_ctrls.bytesWritten 3934464
+system.mem_ctrls.bytesReadSys 7083968
+system.mem_ctrls.bytesWrittenSys 7083712
+system.mem_ctrls.servicedByWrQ 52521
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+system.mem_ctrls.neitherReadNorWriteReqs 0
+system.mem_ctrls.perBankRdBursts::0 10729
+system.mem_ctrls.perBankRdBursts::1 4116
+system.mem_ctrls.perBankRdBursts::2 13533
+system.mem_ctrls.perBankRdBursts::3 1653
+system.mem_ctrls.perBankRdBursts::4 4321
+system.mem_ctrls.perBankRdBursts::5 1347
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+system.mem_ctrls.perBankRdBursts::7 6835
+system.mem_ctrls.perBankRdBursts::8 81
+system.mem_ctrls.perBankRdBursts::9 120
+system.mem_ctrls.perBankRdBursts::10 223
+system.mem_ctrls.perBankRdBursts::11 51
+system.mem_ctrls.perBankRdBursts::12 1584
+system.mem_ctrls.perBankRdBursts::13 1923
+system.mem_ctrls.perBankRdBursts::14 5368
+system.mem_ctrls.perBankRdBursts::15 2493
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+system.mem_ctrls.perBankWrBursts::1 4210
+system.mem_ctrls.perBankWrBursts::2 15017
+system.mem_ctrls.perBankWrBursts::3 1660
+system.mem_ctrls.perBankWrBursts::4 4443
+system.mem_ctrls.perBankWrBursts::5 1372
+system.mem_ctrls.perBankWrBursts::6 3914
+system.mem_ctrls.perBankWrBursts::7 7213
+system.mem_ctrls.perBankWrBursts::8 83
+system.mem_ctrls.perBankWrBursts::9 126
+system.mem_ctrls.perBankWrBursts::10 222
+system.mem_ctrls.perBankWrBursts::11 53
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system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
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system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
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system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
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system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
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system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
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system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
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-system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00%
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-system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.067565 # Average number of messages in buffer
-system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 1.000000 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.061941 # Average number of messages in buffer
-system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999999 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015486 # Average number of messages in buffer
-system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.999887 # Average number of cycles messages are stalled in this MB
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers03.avg_stall_time 5.999420 # Average number of cycles messages are stalled in this MB
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-system.ruby.network.routers0.port_buffers04.avg_stall_time 5.999905 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.092910 # Average number of messages in buffer
-system.ruby.network.routers0.port_buffers07.avg_stall_time 6.751873 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 7.742647
-system.ruby.network.routers0.msg_count.Control::2 72247
-system.ruby.network.routers0.msg_count.Data::2 72243
-system.ruby.network.routers0.msg_count.Response_Data::4 72247
-system.ruby.network.routers0.msg_count.Writeback_Control::3 72243
-system.ruby.network.routers0.msg_bytes.Control::2 577976
-system.ruby.network.routers0.msg_bytes.Data::2 5201496
-system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944
-system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers02.avg_stall_time 10.751860 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015485 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers06.avg_stall_time 1.999808 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015486 # Average number of messages in buffer
-system.ruby.network.routers1.port_buffers07.avg_stall_time 1.999970 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 7.742647
-system.ruby.network.routers1.msg_count.Control::2 72247
-system.ruby.network.routers1.msg_count.Data::2 72243
-system.ruby.network.routers1.msg_count.Response_Data::4 72247
-system.ruby.network.routers1.msg_count.Writeback_Control::3 72243
-system.ruby.network.routers1.msg_bytes.Control::2 577976
-system.ruby.network.routers1.msg_bytes.Data::2 5201496
-system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.030971 # Average number of messages in buffer
-system.ruby.network.int_link_buffers02.avg_stall_time 7.751870 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015485 # Average number of messages in buffer
-system.ruby.network.int_link_buffers08.avg_stall_time 2.999712 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015486 # Average number of messages in buffer
-system.ruby.network.int_link_buffers09.avg_stall_time 2.999954 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015485 # Average number of messages in buffer
-system.ruby.network.int_link_buffers13.avg_stall_time 4.999518 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015486 # Average number of messages in buffer
-system.ruby.network.int_link_buffers14.avg_stall_time 4.999922 # Average number of cycles messages are stalled in this MB
-system.ruby.network.int_link_buffers17.avg_buf_msgs 0.030971 # Average number of messages in buffer
-system.ruby.network.int_link_buffers17.avg_stall_time 9.751864 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015485 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers03.avg_stall_time 3.999615 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015486 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers04.avg_stall_time 3.999938 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.030971 # Average number of messages in buffer
-system.ruby.network.routers2.port_buffers07.avg_stall_time 8.751867 # Average number of cycles messages are stalled in this MB
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 7.742647
-system.ruby.network.routers2.msg_count.Control::2 72247
-system.ruby.network.routers2.msg_count.Data::2 72243
-system.ruby.network.routers2.msg_count.Response_Data::4 72247
-system.ruby.network.routers2.msg_count.Writeback_Control::3 72243
-system.ruby.network.routers2.msg_bytes.Control::2 577976
-system.ruby.network.routers2.msg_bytes.Data::2 5201496
-system.ruby.network.routers2.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 577944
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 216741
-system.ruby.network.msg_count.Data 216729
-system.ruby.network.msg_count.Response_Data 216741
-system.ruby.network.msg_count.Writeback_Control 216729
-system.ruby.network.msg_byte.Control 1733928
-system.ruby.network.msg_byte.Data 15604488
-system.ruby.network.msg_byte.Response_Data 15605352
-system.ruby.network.msg_byte.Writeback_Control 1733832
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 7.742819
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 72247
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72243
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 577944
-system.ruby.network.routers0.throttle1.link_utilization 7.742476
-system.ruby.network.routers0.throttle1.msg_count.Control::2 72247
-system.ruby.network.routers0.throttle1.msg_count.Data::2 72243
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 577976
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-system.ruby.network.routers1.throttle0.msg_count.Control::2 72247
-system.ruby.network.routers1.throttle0.msg_count.Data::2 72243
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 577976
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5201496
-system.ruby.network.routers1.throttle1.link_utilization 7.742819
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 72247
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-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 577944
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-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5201784
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 577944
-system.ruby.network.routers2.throttle1.link_utilization 7.742476
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-system.ruby.network.routers2.throttle1.msg_count.Data::2 72243
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 577976
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5201496
-system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 72247 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 72247 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
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-system.ruby.delayVCHist.vnet_2::samples 72243 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 72243 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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+system.ruby.miss_latency_hist_seqr | 53835 48.63% 48.63% | 52822 47.72% 96.35% | 2558 2.31% 98.67% | 638 0.57% 99.24% | 440 0.39% 99.64% | 345 0.31% 99.95% | 31 0.02% 99.98% | 8 0.00% 99.99% | 0 0.00% 99.99% | 10 0.00% 99.99%
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+system.ruby.memctrl_clk_domain.clock 3
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+system.ruby.delayVCHist.vnet_1 | 110687 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
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-system.ruby.LD.latency_hist_seqr | 41177 79.63% 79.63% | 9735 18.83% 98.45% | 541 1.05% 99.50% | 99 0.19% 99.69% | 79 0.15% 99.85% | 70 0.14% 99.98% | 7 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00%
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-system.ruby.Directory_Controller.IM.Memory_Data 72247 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 72243 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 51711 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 226275 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 37229 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 72247 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 72243 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 72243 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 27454 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 33263 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 11530 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 24257 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 193012 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 25699 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 72243 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 72243 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 60717 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 11530 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 41494
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 69.862389
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 62.422428
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 39.479620
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11034 26.59% 26.59% | 28480 68.63% 95.22% | 1233 2.97% 98.19% | 318 0.76% 98.96% | 224 0.53% 99.50% | 185 0.44% 99.95% | 11 0.02% 99.97% | 6 0.01% 99.99% | 0 0.00% 99.99% | 3 0.00% 99.99%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 41494
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 79
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 34.569620
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 33.693646
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 10.099103
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 93.67% 93.67% | 0 0.00% 93.67% | 3 3.79% 97.46% | 2 2.53% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 79
+system.ruby.Directory_Controller.GETX 110687 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 110683 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 110687 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 110683 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 110687 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 110683 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 110687 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 110683 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 103807 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 487571 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 65817 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 110687 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 110683 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 110683 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 51601 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 41494 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 17592 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 52206 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 446077 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 48225 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 110683 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 110683 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 93095 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 17592 0.00% 0.00%
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:33
-gem5 executing on zizzer, pid 34081
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:10:19
+gem5 executing on boldrock, pid 1506
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
clear fsflags: PASS
flw: PASS
fsw: PASS
fcvt.w.s, 0.0: PASS
fcvt.w.s, -0.0: PASS
fcvt.w.s, overflow: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
-Exiting @ tick 385535500 because target called exit()
+fcvt.w.s, underflow: PASS
+fcvt.w.s, infinity: \e[1;31mFAIL\e[0m (expected 2147483647; found -2147483648)
+fcvt.w.s, -infinity: PASS
+fcvt.w.s, quiet NaN: PASS
+fcvt.w.s, quiet -NaN: PASS
+fcvt.w.s, signaling NaN: PASS
+fcvt.wu.s, truncate positive: PASS
+fcvt.wu.s, truncate negative: PASS
+fcvt.wu.s, 0.0: PASS
+fcvt.wu.s, -0.0: PASS
+fcvt.wu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, underflow: PASS
+fcvt.wu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, -infinity: PASS
+fcvt.wu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.wu.s, signaling NaN: PASS
+fmv.x.s, positive: PASS
+fmv.x.s, negative: PASS
+fmv.x.s, 0.0: PASS
+fmv.x.s, -0.0: PASS
+feq.s, equal: PASS
+feq.s, not equal: PASS
+feq.s, 0 == -0: PASS
+feq.s, quiet NaN first: PASS
+feq.s, quiet NaN second: PASS
+feq.s, quiet NaN both: PASS
+feq.s, signaling NaN first: PASS
+feq.s, signaling NaN second: PASS
+feq.s, signaling NaN both: PASS
+flt.s, equal: PASS
+flt.s, less: PASS
+flt.s, greater: PASS
+flt.s, quiet NaN first: PASS
+flt.s, quiet NaN second: PASS
+flt.s, quiet NaN both: PASS
+flt.s, signaling NaN first: PASS
+flt.s, signaling NaN second: PASS
+flt.s, signaling NaN both: PASS
+fle.s, equal: PASS
+fle.s, less: PASS
+fle.s, greater: PASS
+fle.s, 0 == -0: PASS
+fle.s, quiet NaN first: PASS
+fle.s, quiet NaN second: PASS
+fle.s, quiet NaN both: PASS
+fle.s, signaling NaN first: PASS
+fle.s, signaling NaN second: PASS
+fle.s, signaling NaN both: PASS
+fclass.s, -infinity: PASS
+fclass.s, -normal: PASS
+fclass.s, -subnormal: PASS
+fclass.s, -0.0: PASS
+fclass.s, 0.0: PASS
+fclass.s, subnormal: PASS
+fclass.s, normal: PASS
+fclass.s, infinity: PASS
+fclass.s, signaling NaN: PASS
+fclass.s, quiet NaN: PASS
+fcvt.s.w, 0: PASS
+fcvt.s.w, negative: PASS
+fcvt.s.w, truncate: PASS
+fcvt.s.wu, 0: PASS
+fcvt.s.wu: PASS
+fcvt.s.wu, truncate: PASS
+fmv.s.x: PASS
+fmv.s.x, truncate: PASS
+fsrm: PASS
+fsflags: PASS
+fscsr: PASS
+restore initial round mode: PASS
+fcvt.l.s, truncate positive: PASS
+fcvt.l.s, truncate negative: PASS
+fcvt.l.s, 0.0: PASS
+fcvt.l.s, -0.0: PASS
+fcvt.l.s, 32-bit overflow: PASS
+fcvt.l.s, overflow: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, underflow: PASS
+fcvt.l.s, infinity: \e[1;31mFAIL\e[0m (expected 9223372036854775807; found -9223372036854775808)
+fcvt.l.s, -infinity: PASS
+fcvt.l.s, quiet NaN: PASS
+fcvt.l.s, quiet -NaN: PASS
+fcvt.l.s, signaling NaN: PASS
+fcvt.lu.s, truncate positive: PASS
+fcvt.lu.s, truncate negative: PASS
+fcvt.lu.s, 0.0: PASS
+fcvt.lu.s, -0.0: PASS
+fcvt.lu.s, 32-bit overflow: PASS
+fcvt.lu.s, overflow: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, underflow: PASS
+fcvt.lu.s, infinity: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 0)
+fcvt.lu.s, -infinity: PASS
+fcvt.lu.s, quiet NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, quiet -NaN: \e[1;31mFAIL\e[0m (expected 18446744073709551615; found 9223372036854775808)
+fcvt.lu.s, signaling NaN: PASS
+fcvt.s.l, 0: PASS
+fcvt.s.l, negative: PASS
+fcvt.s.l, 32-bit truncate: PASS
+fcvt.s.lu, 0: PASS
+fcvt.s.lu: PASS
+fcvt.s.lu, 32-bit truncate: PASS
+Exiting @ tick 755664500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000386 # Number of seconds simulated
-sim_ticks 385535500 # Number of ticks simulated
-final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27855 # Simulator instruction rate (inst/s)
-host_op_rate 27855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47485128 # Simulator tick rate (ticks/s)
-host_mem_usage 243704 # Number of bytes of host memory used
-host_seconds 8.12 # Real time elapsed on the host
-sim_insts 226159 # Number of instructions simulated
-sim_ops 226159 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory
-system.physmem.bytes_read::total 72576 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 115 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 771071 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 226159 # Number of instructions committed
-system.cpu.committedOps 226159 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses
-system.cpu.num_func_calls 16616 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls
-system.cpu.num_int_insts 225992 # number of integer instructions
-system.cpu.num_fp_insts 862 # number of float instructions
-system.cpu.num_int_register_reads 298589 # number of times the integer registers were read
-system.cpu.num_int_register_writes 154866 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 733 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 588 # number of times the floating registers were written
-system.cpu.num_mem_refs 88941 # number of memory refs
-system.cpu.num_load_insts 51711 # Number of load instructions
-system.cpu.num_store_insts 37230 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 771071 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 50405 # Number of branches fetched
-system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction
-system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction
-system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction
-system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction
-system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction
-system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction
-system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction
-system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction
-system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 226275 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id
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---------- End Simulation Statistics ----------
--- /dev/null
+[root]
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+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.038000
+IDD3P12=0.000000
+IDD4R=0.157000
+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+device_bus_width=8
+device_rowbuffer_size=1024
+device_size=536870912
+devices_per_rank=8
+dll=true
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+max_accesses_per_row=16
+mem_sched_policy=frfcfs
+min_writes_per_switch=16
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
+tRRD_L=0
+tRTP=7500
+tRTW=2500
+tWR=15000
+tWTR=7500
+tXAW=30000
+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1000,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.157",
+ "burst_length": 8,
+ "tRTP": 7500,
+ "IDD4W": "0.125",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "power_model": null,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 6000,
+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "max_insts_any_thread": 0,
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "fetch1LineSnapWidth": 0,
+ "fetch1ToFetch2BackwardDelay": 1,
+ "fetch1FetchLimit": 1,
+ "executeIssueLimit": 2,
+ "system": "system",
+ "executeLSQMaxStoreBufferStoresPerCycle": 2,
+ "icache": {
+ "cpu_side": {
+ "peer": "system.cpu.icache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 131072,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": true,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 131072,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "decodeInputWidth": 2,
+ "cxx_class": "MinorCPU",
+ "max_loads_all_threads": 0,
+ "executeMemoryIssueLimit": 1,
+ "decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
+ "max_loads_any_thread": 0,
+ "executeLSQTransfersQueueSize": 2,
+ "p_state_clk_gate_max": 1000000000000,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "executeMemoryWidth": 0,
+ "default_p_state": "UNDEFINED",
+ "executeBranchDelay": 1,
+ "executeMemoryCommitLimit": 1,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 2097152,
+ "tag_latency": 20,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "do_quiesce": true,
+ "type": "MinorCPU",
+ "executeCycleInput": true,
+ "executeAllowEarlyMemoryIssue": true,
+ "executeInputBufferSize": 7,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "socket_id": 0,
+ "progress_interval": 0,
+ "p_state_clk_gate_min": 1000,
+ "toL2Bus": {
+ "point_of_coherency": false,
+ "system": "system",
+ "response_latency": 1,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "executeFuncUnits": {
+ "name": "executeFuncUnits",
+ "eventq_index": 0,
+ "cxx_class": "MinorFUPool",
+ "path": "system.cpu.executeFuncUnits",
+ "funcUnits": [
+ {
+ "issueLat": 1,
+ "opLat": 3,
+ "name": "funcUnits0",
+ "cantForwardFromFUIndices": [],
+ "opClasses": {
+ "name": "opClasses",
+ "opClasses": [
+ {
+ "opClass": "IntAlu",
+ "name": "opClasses",
+ "eventq_index": 0,
+ "cxx_class": "MinorOpClass",
+ "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses",
+ "type": "MinorOpClass"
+ }
+ ],
+ "eventq_index": 0,
+ "cxx_class": "MinorOpClassSet",
+ "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses",
+ "type": "MinorOpClassSet"
+ },
+ "eventq_index": 0,
+ "timings": [
+ {
+ "extraAssumedLat": 0,
+ "description": "Int",
+ "srcRegsRelativeLats": [
+ 2
+ ],
+ "suppress": false,
+ "mask": 0,
+ "extraCommitLat": 0,
+ "eventq_index": 0,
+ "opClasses": {
+ "name": "opClasses",
+ "opClasses": [],
+ "eventq_index": 0,
+ "cxx_class": "MinorOpClassSet",
+ "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses",
+ "type": "MinorOpClassSet"
+ },
+ "cxx_class": "MinorFUTiming",
+ "path": "system.cpu.executeFuncUnits.funcUnits0.timings",
+ "extraCommitLatExpr": null,
+ "type": "MinorFUTiming",
+ "match": 0,
+ "name": "timings"
+ }
+ ],
+ "cxx_class": "MinorFU",
+ "path": "system.cpu.executeFuncUnits.funcUnits0",
+ "type": "MinorFU"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 3,
+ "name": "funcUnits1",
+ "cantForwardFromFUIndices": [],
+ "opClasses": {
+ "name": "opClasses",
+ "opClasses": [
+ {
+ "opClass": "IntAlu",
+ "name": "opClasses",
+ "eventq_index": 0,
+ "cxx_class": "MinorOpClass",
+ "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses",
+ "type": "MinorOpClass"
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+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1345
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing
+
+Global frequency set at 1000000000000 ticks per second
+lui: PASS
+lui, negative: PASS
+auipc: 0x184D6
+auipc: PASS
+jal: PASS
+jalr: PASS
+beq, equal: PASS
+beq, not equal: PASS
+bne, equal: PASS
+bne, not equal: PASS
+blt, less: PASS
+blt, equal: PASS
+blt, greater: PASS
+bge, less: PASS
+bge, equal: PASS
+bge, greater: PASS
+bltu, greater: PASS
+bltu, equal: PASS
+bltu, less: PASS
+bgeu, greater: PASS
+bgeu, equal: PASS
+bgeu, less: PASS
+lb, positive: PASS
+lb, negative: PASS
+lh, positive: PASS
+lh, negative: PASS
+lw, positive: PASS
+lw, negative: PASS
+lbu: PASS
+lhu: PASS
+sb: PASS
+sh: PASS
+sw: PASS
+addi: PASS
+addi, overflow: PASS
+slti, true: PASS
+slti, false: PASS
+sltiu, false: PASS
+sltiu, true: PASS
+xori (1): PASS
+xori (0): PASS
+ori (1): PASS
+ori (A): PASS
+andi (0): PASS
+andi (1): PASS
+slli, general: PASS
+slli, erase: PASS
+srli, general: PASS
+srli, erase: PASS
+srli, negative: PASS
+srai, general: PASS
+srai, erase: PASS
+srai, negative: PASS
+add: PASS
+add, overflow: PASS
+sub: PASS
+sub, "overflow": PASS
+sll, general: PASS
+sll, erase: PASS
+slt, true: PASS
+slt, false: PASS
+sltu, false: PASS
+sltu, true: PASS
+xor (1): PASS
+xor (0): PASS
+srl, general: PASS
+srl, erase: PASS
+srl, negative: PASS
+sra, general: PASS
+sra, erase: PASS
+sra, negative: PASS
+or (1): PASS
+or (A): PASS
+and (0): PASS
+and (-1): PASS
+Bytes written: 15
+open, write: PASS
+access F_OK: PASS
+access R_OK: PASS
+access W_OK: PASS
+access X_OK: PASS
+stat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+fstat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+open, stat: PASS
+Bytes read: 15
+String read: this is a test
+open, read, unlink: PASS
+times:
+ tms_utime = 0
+ tms_stime = 0
+ tms_cutime = 0
+ tms_cstime = 0
+times: \e[1;31mFAIL\e[0m (expected 1; found 0)
+timeval:
+ tv_sec = 1000000000
+ tv_usec = 259
+gettimeofday: PASS
+Cycles: 527819
+rdcycle: PASS
+Time: 1499980275
+rdtime: PASS
+Instructions Retired: 214592
+rdinstret: PASS
+lwu: PASS
+ld: PASS
+sd: PASS
+addiw: PASS
+addiw, overflow: PASS
+addiw, truncate: PASS
+slliw, general: PASS
+slliw, erase: PASS
+slliw, truncate: PASS
+srliw, general: PASS
+srliw, erase: PASS
+srliw, negative: PASS
+srliw, truncate: PASS
+sraiw, general: PASS
+sraiw, erase: PASS
+sraiw, negative: PASS
+sraiw, truncate: PASS
+addw: PASS
+addw, overflow: PASS
+addw, truncate: PASS
+subw: PASS
+subw, "overflow": PASS
+subw, truncate: PASS
+sllw, general: PASS
+sllw, erase: PASS
+sllw, truncate: PASS
+srlw, general: PASS
+srlw, erase: PASS
+srlw, negative: PASS
+srlw, truncate: PASS
+sraw, general: PASS
+sraw, erase: PASS
+sraw, negative: PASS
+sraw, truncate: PASS
+Exiting @ tick 313251500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000313
+sim_ticks 313251500
+final_tick 313251500
+sim_freq 1000000000000
+host_inst_rate 2591
+host_op_rate 2598
+host_tick_rate 3037898
+host_mem_usage 272308
+host_seconds 103.11
+sim_insts 267165
+sim_ops 267935
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 313251500
+system.physmem.bytes_read::cpu.inst 79360
+system.physmem.bytes_read::cpu.data 31360
+system.physmem.bytes_read::total 110720
+system.physmem.bytes_inst_read::cpu.inst 79360
+system.physmem.bytes_inst_read::total 79360
+system.physmem.num_reads::cpu.inst 1240
+system.physmem.num_reads::cpu.data 490
+system.physmem.num_reads::total 1730
+system.physmem.bw_read::cpu.inst 253342761
+system.physmem.bw_read::cpu.data 100111252
+system.physmem.bw_read::total 353454014
+system.physmem.bw_inst_read::cpu.inst 253342761
+system.physmem.bw_inst_read::total 253342761
+system.physmem.bw_total::cpu.inst 253342761
+system.physmem.bw_total::cpu.data 100111252
+system.physmem.bw_total::total 353454014
+system.physmem.readReqs 1730
+system.physmem.writeReqs 0
+system.physmem.readBursts 1730
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 110720
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 110720
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 226
+system.physmem.perBankRdBursts::1 132
+system.physmem.perBankRdBursts::2 158
+system.physmem.perBankRdBursts::3 128
+system.physmem.perBankRdBursts::4 122
+system.physmem.perBankRdBursts::5 110
+system.physmem.perBankRdBursts::6 45
+system.physmem.perBankRdBursts::7 84
+system.physmem.perBankRdBursts::8 30
+system.physmem.perBankRdBursts::9 49
+system.physmem.perBankRdBursts::10 66
+system.physmem.perBankRdBursts::11 62
+system.physmem.perBankRdBursts::12 141
+system.physmem.perBankRdBursts::13 134
+system.physmem.perBankRdBursts::14 150
+system.physmem.perBankRdBursts::15 93
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 313129500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1730
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1515
+system.physmem.rdQLenPdf::1 197
+system.physmem.rdQLenPdf::2 18
+system.physmem.rdQLenPdf::3 0
+system.physmem.rdQLenPdf::4 0
+system.physmem.rdQLenPdf::5 0
+system.physmem.rdQLenPdf::6 0
+system.physmem.rdQLenPdf::7 0
+system.physmem.rdQLenPdf::8 0
+system.physmem.rdQLenPdf::9 0
+system.physmem.rdQLenPdf::10 0
+system.physmem.rdQLenPdf::11 0
+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
+system.physmem.rdQLenPdf::14 0
+system.physmem.rdQLenPdf::15 0
+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
+system.physmem.rdQLenPdf::27 0
+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 0
+system.physmem.wrQLenPdf::1 0
+system.physmem.wrQLenPdf::2 0
+system.physmem.wrQLenPdf::3 0
+system.physmem.wrQLenPdf::4 0
+system.physmem.wrQLenPdf::5 0
+system.physmem.wrQLenPdf::6 0
+system.physmem.wrQLenPdf::7 0
+system.physmem.wrQLenPdf::8 0
+system.physmem.wrQLenPdf::9 0
+system.physmem.wrQLenPdf::10 0
+system.physmem.wrQLenPdf::11 0
+system.physmem.wrQLenPdf::12 0
+system.physmem.wrQLenPdf::13 0
+system.physmem.wrQLenPdf::14 0
+system.physmem.wrQLenPdf::15 0
+system.physmem.wrQLenPdf::16 0
+system.physmem.wrQLenPdf::17 0
+system.physmem.wrQLenPdf::18 0
+system.physmem.wrQLenPdf::19 0
+system.physmem.wrQLenPdf::20 0
+system.physmem.wrQLenPdf::21 0
+system.physmem.wrQLenPdf::22 0
+system.physmem.wrQLenPdf::23 0
+system.physmem.wrQLenPdf::24 0
+system.physmem.wrQLenPdf::25 0
+system.physmem.wrQLenPdf::26 0
+system.physmem.wrQLenPdf::27 0
+system.physmem.wrQLenPdf::28 0
+system.physmem.wrQLenPdf::29 0
+system.physmem.wrQLenPdf::30 0
+system.physmem.wrQLenPdf::31 0
+system.physmem.wrQLenPdf::32 0
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 384
+system.physmem.bytesPerActivate::mean 284.166667
+system.physmem.bytesPerActivate::gmean 191.143330
+system.physmem.bytesPerActivate::stdev 258.838001
+system.physmem.bytesPerActivate::0-127 121 31.51% 31.51%
+system.physmem.bytesPerActivate::128-255 78 20.31% 51.82%
+system.physmem.bytesPerActivate::256-383 78 20.31% 72.14%
+system.physmem.bytesPerActivate::384-511 41 10.68% 82.81%
+system.physmem.bytesPerActivate::512-639 16 4.17% 86.98%
+system.physmem.bytesPerActivate::640-767 17 4.43% 91.41%
+system.physmem.bytesPerActivate::768-895 7 1.82% 93.23%
+system.physmem.bytesPerActivate::896-1023 13 3.39% 96.61%
+system.physmem.bytesPerActivate::1024-1151 13 3.39% 100.00%
+system.physmem.bytesPerActivate::total 384
+system.physmem.totQLat 26594000
+system.physmem.totMemAccLat 59031500
+system.physmem.totBusLat 8650000
+system.physmem.avgQLat 15372.25
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 34122.25
+system.physmem.avgRdBW 353.45
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 353.45
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 2.76
+system.physmem.busUtilRead 2.76
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.08
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1341
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 77.51
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 180999.71
+system.physmem.pageHitRate 77.51
+system.physmem_0.actEnergy 1727880
+system.physmem_0.preEnergy 910800
+system.physmem_0.readEnergy 7175700
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 24585600.000000
+system.physmem_0.actBackEnergy 18117450
+system.physmem_0.preBackEnergy 554880
+system.physmem_0.actPowerDownEnergy 118740120
+system.physmem_0.prePowerDownEnergy 4485600
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 176298030
+system.physmem_0.averagePower 562.798477
+system.physmem_0.totalIdleTime 271894500
+system.physmem_0.memoryStateTime::IDLE 246000
+system.physmem_0.memoryStateTime::REF 10400000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 11677750
+system.physmem_0.memoryStateTime::ACT 30512750
+system.physmem_0.memoryStateTime::ACT_PDN 260415000
+system.physmem_1.actEnergy 1049580
+system.physmem_1.preEnergy 546480
+system.physmem_1.readEnergy 5176500
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 19053840.000000
+system.physmem_1.actBackEnergy 13439460
+system.physmem_1.preBackEnergy 996000
+system.physmem_1.actPowerDownEnergy 66734460
+system.physmem_1.prePowerDownEnergy 15381120
+system.physmem_1.selfRefreshEnergy 24957060
+system.physmem_1.totalEnergy 147334500
+system.physmem_1.averagePower 470.337827
+system.physmem_1.totalIdleTime 281112750
+system.physmem_1.memoryStateTime::IDLE 1783500
+system.physmem_1.memoryStateTime::REF 8084000
+system.physmem_1.memoryStateTime::SREF 94783750
+system.physmem_1.memoryStateTime::PRE_PDN 40053750
+system.physmem_1.memoryStateTime::ACT 22186000
+system.physmem_1.memoryStateTime::ACT_PDN 146360500
+system.pwrStateResidencyTicks::UNDEFINED 313251500
+system.cpu.branchPred.lookups 74064
+system.cpu.branchPred.condPredicted 50422
+system.cpu.branchPred.condIncorrect 6373
+system.cpu.branchPred.BTBLookups 52846
+system.cpu.branchPred.BTBHits 24168
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 45.732884
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 16397
+system.cpu.branchPred.indirectHits 9369
+system.cpu.branchPred.indirectMisses 7028
+system.cpu.branchPredindirectMispredicted 3663
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 182
+system.cpu.pwrStateResidencyTicks::ON 313251500
+system.cpu.numCycles 626503
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 267165
+system.cpu.committedOps 267935
+system.cpu.discardedOps 16687
+system.cpu.numFetchSuspends 0
+system.cpu.cpi 2.345004
+system.cpu.ipc 0.426439
+system.cpu.op_class_0::No_OpClass 191 0.07% 0.07%
+system.cpu.op_class_0::IntAlu 157741 58.87% 58.94%
+system.cpu.op_class_0::IntMult 436 0.16% 59.11%
+system.cpu.op_class_0::IntDiv 230 0.09% 59.19%
+system.cpu.op_class_0::FloatAdd 0 0.00% 59.19%
+system.cpu.op_class_0::FloatCmp 0 0.00% 59.19%
+system.cpu.op_class_0::FloatCvt 0 0.00% 59.19%
+system.cpu.op_class_0::FloatMult 0 0.00% 59.19%
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.19%
+system.cpu.op_class_0::FloatDiv 0 0.00% 59.19%
+system.cpu.op_class_0::FloatMisc 0 0.00% 59.19%
+system.cpu.op_class_0::FloatSqrt 0 0.00% 59.19%
+system.cpu.op_class_0::SimdAdd 0 0.00% 59.19%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdAlu 0 0.00% 59.19%
+system.cpu.op_class_0::SimdCmp 0 0.00% 59.19%
+system.cpu.op_class_0::SimdCvt 0 0.00% 59.19%
+system.cpu.op_class_0::SimdMisc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdMult 0 0.00% 59.19%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdShift 0 0.00% 59.19%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.19%
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.19%
+system.cpu.op_class_0::MemRead 67806 25.31% 84.50%
+system.cpu.op_class_0::MemWrite 41519 15.50% 100.00%
+system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00%
+system.cpu.op_class_0::FloatMemWrite 12 0.00% 100.00%
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00%
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class_0::total 267935
+system.cpu.tickCycles 372506
+system.cpu.idleCycles 253997
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 313251500
+system.cpu.dcache.tags.replacements 0
+system.cpu.dcache.tags.tagsinuse 375.293791
+system.cpu.dcache.tags.total_refs 111829
+system.cpu.dcache.tags.sampled_refs 492
+system.cpu.dcache.tags.avg_refs 227.294715
+system.cpu.dcache.tags.warmup_cycle 0
+system.cpu.dcache.tags.occ_blocks::cpu.data 375.293791
+system.cpu.dcache.tags.occ_percent::cpu.data 0.091624
+system.cpu.dcache.tags.occ_percent::total 0.091624
+system.cpu.dcache.tags.occ_task_id_blocks::1024 492
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 14
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 19
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 459
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.120117
+system.cpu.dcache.tags.tag_accesses 225460
+system.cpu.dcache.tags.data_accesses 225460
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 313251500
+system.cpu.dcache.ReadReq_hits::cpu.data 69905
+system.cpu.dcache.ReadReq_hits::total 69905
+system.cpu.dcache.WriteReq_hits::cpu.data 40366
+system.cpu.dcache.WriteReq_hits::total 40366
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 779
+system.cpu.dcache.LoadLockedReq_hits::total 779
+system.cpu.dcache.StoreCondReq_hits::cpu.data 779
+system.cpu.dcache.StoreCondReq_hits::total 779
+system.cpu.dcache.demand_hits::cpu.data 110271
+system.cpu.dcache.demand_hits::total 110271
+system.cpu.dcache.overall_hits::cpu.data 110271
+system.cpu.dcache.overall_hits::total 110271
+system.cpu.dcache.ReadReq_misses::cpu.data 269
+system.cpu.dcache.ReadReq_misses::total 269
+system.cpu.dcache.WriteReq_misses::cpu.data 386
+system.cpu.dcache.WriteReq_misses::total 386
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+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1741
+system.cpu.toL2Bus.snoop_fanout::mean 0.001149
+system.cpu.toL2Bus.snoop_fanout::stdev 0.033884
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1739 99.89% 99.89%
+system.cpu.toL2Bus.snoop_fanout::1 2 0.11% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 1741
+system.cpu.toL2Bus.reqLayer0.occupancy 1017500
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 1872000
+system.cpu.toL2Bus.respLayer0.utilization 0.6
+system.cpu.toL2Bus.respLayer1.occupancy 738000
+system.cpu.toL2Bus.respLayer1.utilization 0.2
+system.membus.snoop_filter.tot_requests 1730
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 313251500
+system.membus.trans_dist::ReadResp 1506
+system.membus.trans_dist::ReadExReq 224
+system.membus.trans_dist::ReadExResp 224
+system.membus.trans_dist::ReadSharedReq 1506
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3460
+system.membus.pkt_count::total 3460
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 110720
+system.membus.pkt_size::total 110720
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1730
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1730 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1730
+system.membus.reqLayer0.occupancy 2027000
+system.membus.reqLayer0.utilization 0.6
+system.membus.respLayer1.occupancy 9218000
+system.membus.respLayer1.utilization 2.9
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=DerivO3CPU
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+LFSTSize=1024
+LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+branchPred=system.cpu.branchPred
+cacheStorePorts=200
+checker=Null
+clk_domain=system.cpu_clk_domain
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+default_p_state=UNDEFINED
+dispatchWidth=8
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
+fetchQueueSize=32
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+needsTSO=false
+numIQEntries=64
+numPhysCCRegs=0
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numPhysVecRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+simpoint_start_insts=
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+socket_id=0
+squashWidth=8
+store_set_clear_period=250000
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wait_for_remote_gdb=false
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.branchPred]
+type=TournamentBP
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+eventq_index=0
+globalCtrBits=2
+globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
+instShiftAmt=2
+localCtrBits=2
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+useIndirect=true
+
+[system.cpu.dcache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=262144
+tag_latency=2
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+eventq_index=0
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+eventq_index=0
+opClass=IntAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+eventq_index=0
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+eventq_index=0
+opClass=IntMult
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+eventq_index=0
+opClass=IntDiv
+opLat=20
+pipelined=false
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+eventq_index=0
+opClass=FloatAdd
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatCmp
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatCvt
+opLat=2
+pipelined=true
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2 opList3 opList4
+count=2
+eventq_index=0
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+eventq_index=0
+opClass=FloatMult
+opLat=4
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatDiv
+opLat=12
+pipelined=false
+
+[system.cpu.fuPool.FUList3.opList4]
+type=OpDesc
+eventq_index=0
+opClass=FloatSqrt
+opLat=24
+pipelined=false
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0 opList1
+count=0
+eventq_index=0
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+eventq_index=0
+opClass=SimdAdd
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+eventq_index=0
+opClass=SimdAddAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+eventq_index=0
+opClass=SimdAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+eventq_index=0
+opClass=SimdCmp
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+eventq_index=0
+opClass=SimdCvt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+eventq_index=0
+opClass=SimdMisc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+eventq_index=0
+opClass=SimdMult
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+eventq_index=0
+opClass=SimdMultAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+eventq_index=0
+opClass=SimdShift
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+eventq_index=0
+opClass=SimdShiftAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+eventq_index=0
+opClass=SimdSqrt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatAdd
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatAlu
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatCmp
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatCvt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatDiv
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMisc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMult
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatMultAcc
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+eventq_index=0
+opClass=SimdFloatSqrt
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=0
+eventq_index=0
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1 opList2 opList3
+count=4
+eventq_index=0
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+eventq_index=0
+opClass=MemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+eventq_index=0
+opClass=MemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+eventq_index=0
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+eventq_index=0
+opClass=IprAccess
+opLat=3
+pipelined=false
+
+[system.cpu.icache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=20
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=DRAMCtrl
+IDD0=0.055000
+IDD02=0.000000
+IDD2N=0.032000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.032000
+IDD2P12=0.000000
+IDD3N=0.038000
+IDD3N2=0.000000
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+IDD3P02=0.000000
+IDD3P1=0.038000
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+IDD4R2=0.000000
+IDD4W=0.125000
+IDD4W2=0.000000
+IDD5=0.235000
+IDD52=0.000000
+IDD6=0.020000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
+activation_limit=4
+addr_mapping=RoRaBaCoCh
+bank_groups_per_rank=0
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
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+device_rowbuffer_size=1024
+device_size=536870912
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+dll=true
+eventq_index=0
+in_addr_map=true
+kvm_map=true
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+p_state_clk_gate_bins=20
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+p_state_clk_gate_min=1000
+page_policy=open_adaptive
+power_model=Null
+range=0:134217727:0:0:0:0
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCCD_L=0
+tCK=1250
+tCL=13750
+tCS=2500
+tRAS=35000
+tRCD=13750
+tREFI=7800000
+tRFC=260000
+tRP=13750
+tRRD=6000
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+tRTP=7500
+tRTW=2500
+tWR=15000
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+tXP=6000
+tXPDLL=0
+tXS=270000
+tXSDLL=0
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
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+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1000,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
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+ "IDD4R": "0.157",
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+ "tRTP": 7500,
+ "IDD4W": "0.125",
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+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
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+ "IDD6": "0.02",
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+ "type": "DRAMCtrl",
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+ "IDD0": "0.055",
+ "IDD62": "0.0",
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+ "mem_sched_policy": "frfcfs",
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+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
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+ "conf_table_reported": true,
+ "tCK": 1250,
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+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 6000,
+ "tXS": 270000,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30000,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727:0:0:0:0",
+ "VDD2": "0.0",
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+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
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+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ },
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+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
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+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
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+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
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+ "mem_mode": "timing",
+ "name": "system",
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+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
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+ "smtLSQThreshold": 100,
+ "fetchTrapLatency": 1,
+ "iewToRenameDelay": 1,
+ "l2cache": {
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+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
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+ "cxx_class": "Cache",
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+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
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+ "p_state_clk_gate_min": 1000,
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+ "eventq_index": 0,
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+ "assoc": 8,
+ "cxx_class": "LRU",
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+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
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+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
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+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "itb": {
+ "name": "itb",
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+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "fetchWidth": 8,
+ "max_loads_all_threads": 0,
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+ "commitToFetchDelay": 1,
+ "needsTSO": false,
+ "smtIQThreshold": 100,
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+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
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+ "maxStackSize": 67108864,
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+ "type": "Process",
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+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "SSITSize": 1024,
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+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
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+ "renameWidth": 8,
+ "numThreads": 1,
+ "syscallRetryLatency": 10000,
+ "squashWidth": 8,
+ "function_trace": false,
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+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
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+ "system": "system",
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+ "cxx_class": "CoherentXBar",
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+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "p_state_clk_gate_min": 1000,
+ "fuPool": {
+ "name": "fuPool",
+ "FUList": [
+ {
+ "count": 6,
+ "opList": [
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+ "name": "opList",
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+ "path": "system.cpu.fuPool.FUList0.opList",
+ "type": "OpDesc"
+ }
+ ],
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+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList0",
+ "type": "FUDesc"
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+ "type": "OpDesc"
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+ {
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+ "name": "opList1",
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+ "cxx_class": "OpDesc",
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+ }
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+ "path": "system.cpu.fuPool.FUList1",
+ "type": "FUDesc"
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+ "name": "opList0",
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+ {
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList1",
+ "type": "OpDesc"
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+ "opClass": "FloatCvt",
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+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList2.opList2",
+ "type": "OpDesc"
+ }
+ ],
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+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList2",
+ "type": "FUDesc"
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+ {
+ "count": 2,
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+ "name": "opList0",
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList0",
+ "type": "OpDesc"
+ },
+ {
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+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMisc",
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+ "name": "opList2",
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+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList3.opList2",
+ "type": "OpDesc"
+ },
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+ "opClass": "FloatDiv",
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+ "pipelined": false,
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+ "path": "system.cpu.fuPool.FUList3.opList3",
+ "type": "OpDesc"
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+ "opClass": "FloatSqrt",
+ "opLat": 24,
+ "name": "opList4",
+ "pipelined": false,
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+ "type": "OpDesc"
+ }
+ ],
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+ },
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+ "path": "system.cpu.fuPool.FUList4.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMemRead",
+ "opLat": 1,
+ "name": "opList1",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList4.opList1",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList4",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList4",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "opClass": "SimdAdd",
+ "opLat": 1,
+ "name": "opList00",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList00",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdAddAcc",
+ "opLat": 1,
+ "name": "opList01",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList01",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdAlu",
+ "opLat": 1,
+ "name": "opList02",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList02",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdCmp",
+ "opLat": 1,
+ "name": "opList03",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList03",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdCvt",
+ "opLat": 1,
+ "name": "opList04",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList04",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdMisc",
+ "opLat": 1,
+ "name": "opList05",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList05",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdMult",
+ "opLat": 1,
+ "name": "opList06",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList06",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdMultAcc",
+ "opLat": 1,
+ "name": "opList07",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList07",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdShift",
+ "opLat": 1,
+ "name": "opList08",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList08",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdShiftAcc",
+ "opLat": 1,
+ "name": "opList09",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList09",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdSqrt",
+ "opLat": 1,
+ "name": "opList10",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList10",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatAdd",
+ "opLat": 1,
+ "name": "opList11",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList11",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatAlu",
+ "opLat": 1,
+ "name": "opList12",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList12",
+ "type": "OpDesc"
+ },
+ {
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+ "opLat": 1,
+ "name": "opList13",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList13",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatCvt",
+ "opLat": 1,
+ "name": "opList14",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList14",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatDiv",
+ "opLat": 1,
+ "name": "opList15",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList15",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatMisc",
+ "opLat": 1,
+ "name": "opList16",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList16",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatMult",
+ "opLat": 1,
+ "name": "opList17",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList17",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatMultAcc",
+ "opLat": 1,
+ "name": "opList18",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList18",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "SimdFloatSqrt",
+ "opLat": 1,
+ "name": "opList19",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList5.opList19",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList5",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList5",
+ "type": "FUDesc"
+ },
+ {
+ "count": 0,
+ "opList": [
+ {
+ "opClass": "MemWrite",
+ "opLat": 1,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList6.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMemWrite",
+ "opLat": 1,
+ "name": "opList1",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList6.opList1",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList6",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList6",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "opClass": "MemRead",
+ "opLat": 1,
+ "name": "opList0",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList7.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "MemWrite",
+ "opLat": 1,
+ "name": "opList1",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList7.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMemRead",
+ "opLat": 1,
+ "name": "opList2",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList7.opList2",
+ "type": "OpDesc"
+ },
+ {
+ "opClass": "FloatMemWrite",
+ "opLat": 1,
+ "name": "opList3",
+ "pipelined": true,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList7.opList3",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList7",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList7",
+ "type": "FUDesc"
+ },
+ {
+ "count": 1,
+ "opList": [
+ {
+ "opClass": "IprAccess",
+ "opLat": 3,
+ "name": "opList",
+ "pipelined": false,
+ "eventq_index": 0,
+ "cxx_class": "OpDesc",
+ "path": "system.cpu.fuPool.FUList8.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList8",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu.fuPool.FUList8",
+ "type": "FUDesc"
+ }
+ ],
+ "eventq_index": 0,
+ "cxx_class": "FUPool",
+ "path": "system.cpu.fuPool",
+ "type": "FUPool"
+ },
+ "socket_id": 0,
+ "renameToFetchDelay": 1,
+ "icache": {
+ "cpu_side": {
+ "peer": "system.cpu.icache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 131072,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": true,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 131072,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "path": "system.cpu",
+ "numRobs": 1,
+ "switched_out": false,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "smtROBThreshold": 100,
+ "numIQEntries": 64,
+ "branchPred": {
+ "numThreads": 1,
+ "BTBEntries": 4096,
+ "cxx_class": "TournamentBP",
+ "indirectPathLength": 3,
+ "globalCtrBits": 2,
+ "choicePredictorSize": 8192,
+ "indirectHashGHR": true,
+ "eventq_index": 0,
+ "localHistoryTableSize": 2048,
+ "type": "TournamentBP",
+ "indirectSets": 256,
+ "indirectWays": 2,
+ "choiceCtrBits": 2,
+ "useIndirect": true,
+ "localCtrBits": 2,
+ "path": "system.cpu.branchPred",
+ "localPredictorSize": 2048,
+ "RASSize": 16,
+ "globalPredictorSize": 8192,
+ "name": "branchPred",
+ "indirectHashTargets": true,
+ "instShiftAmt": 2,
+ "indirectTagSize": 16,
+ "BTBTagSize": 16
+ },
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "smtROBPolicy": "Partitioned",
+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 262144,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "numPhysVecRegs": 256,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "smtCommitPolicy": "RoundRobin",
+ "issueToExecuteDelay": 1,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "numROBEntries": 192,
+ "fetchQueueSize": 32,
+ "iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 0,
+ "renameToIEWDelay": 2,
+ "p_state_clk_gate_bins": 20,
+ "progress_interval": 0,
+ "LQEntries": 32
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:25:07
+gem5 executing on boldrock, pid 6002
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/o3-timing
+
+Global frequency set at 1000000000000 ticks per second
+lui: PASS
+lui, negative: PASS
+auipc: 0x184D6
+auipc: PASS
+jal: PASS
+jalr: PASS
+beq, equal: PASS
+beq, not equal: PASS
+bne, equal: PASS
+bne, not equal: PASS
+blt, less: PASS
+blt, equal: PASS
+blt, greater: PASS
+bge, less: PASS
+bge, equal: PASS
+bge, greater: PASS
+bltu, greater: PASS
+bltu, equal: PASS
+bltu, less: PASS
+bgeu, greater: PASS
+bgeu, equal: PASS
+bgeu, less: PASS
+lb, positive: PASS
+lb, negative: PASS
+lh, positive: PASS
+lh, negative: PASS
+lw, positive: PASS
+lw, negative: PASS
+lbu: PASS
+lhu: PASS
+sb: PASS
+sh: PASS
+sw: PASS
+addi: PASS
+addi, overflow: PASS
+slti, true: PASS
+slti, false: PASS
+sltiu, false: PASS
+sltiu, true: PASS
+xori (1): PASS
+xori (0): PASS
+ori (1): PASS
+ori (A): PASS
+andi (0): PASS
+andi (1): PASS
+slli, general: PASS
+slli, erase: PASS
+srli, general: PASS
+srli, erase: PASS
+srli, negative: PASS
+srai, general: PASS
+srai, erase: PASS
+srai, negative: PASS
+add: PASS
+add, overflow: PASS
+sub: PASS
+sub, "overflow": PASS
+sll, general: PASS
+sll, erase: PASS
+slt, true: PASS
+slt, false: PASS
+sltu, false: PASS
+sltu, true: PASS
+xor (1): PASS
+xor (0): PASS
+srl, general: PASS
+srl, erase: PASS
+srl, negative: PASS
+sra, general: PASS
+sra, erase: PASS
+sra, negative: PASS
+or (1): PASS
+or (A): PASS
+and (0): PASS
+and (-1): PASS
+Bytes written: 15
+open, write: PASS
+access F_OK: PASS
+access R_OK: PASS
+access W_OK: PASS
+access X_OK: PASS
+stat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+fstat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+open, stat: PASS
+Bytes read: 15
+String read: this is a test
+open, read, unlink: PASS
+times:
+ tms_utime = 0
+ tms_stime = 0
+ tms_cutime = 0
+ tms_cstime = 0
+times: \e[1;31mFAIL\e[0m (expected 1; found 0)
+timeval:
+ tv_sec = 1000000000
+ tv_usec = 194
+gettimeofday: PASS
+Cycles: 397395
+rdcycle: PASS
+Time: 1499981167
+rdtime: PASS
+Instructions Retired: 214447
+rdinstret: PASS
+lwu: PASS
+ld: PASS
+sd: PASS
+addiw: PASS
+addiw, overflow: PASS
+addiw, truncate: PASS
+slliw, general: PASS
+slliw, erase: PASS
+slliw, truncate: PASS
+srliw, general: PASS
+srliw, erase: PASS
+srliw, negative: PASS
+srliw, truncate: PASS
+sraiw, general: PASS
+sraiw, erase: PASS
+sraiw, negative: PASS
+sraiw, truncate: PASS
+addw: PASS
+addw, overflow: PASS
+addw, truncate: PASS
+subw: PASS
+subw, "overflow": PASS
+subw, truncate: PASS
+sllw, general: PASS
+sllw, erase: PASS
+sllw, truncate: PASS
+srlw, general: PASS
+srlw, erase: PASS
+srlw, negative: PASS
+srlw, truncate: PASS
+sraw, general: PASS
+sraw, erase: PASS
+sraw, negative: PASS
+sraw, truncate: PASS
+Exiting @ tick 243602000 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000244
+sim_ticks 243602000
+final_tick 243602000
+sim_freq 1000000000000
+host_inst_rate 3536
+host_op_rate 3546
+host_tick_rate 3225943
+host_mem_usage 272312
+host_seconds 75.51
+sim_insts 266983
+sim_ops 267753
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 243602000
+system.physmem.bytes_read::cpu.inst 72896
+system.physmem.bytes_read::cpu.data 31488
+system.physmem.bytes_read::total 104384
+system.physmem.bytes_inst_read::cpu.inst 72896
+system.physmem.bytes_inst_read::total 72896
+system.physmem.num_reads::cpu.inst 1139
+system.physmem.num_reads::cpu.data 492
+system.physmem.num_reads::total 1631
+system.physmem.bw_read::cpu.inst 299242207
+system.physmem.bw_read::cpu.data 129260022
+system.physmem.bw_read::total 428502229
+system.physmem.bw_inst_read::cpu.inst 299242207
+system.physmem.bw_inst_read::total 299242207
+system.physmem.bw_total::cpu.inst 299242207
+system.physmem.bw_total::cpu.data 129260022
+system.physmem.bw_total::total 428502229
+system.physmem.readReqs 1631
+system.physmem.writeReqs 0
+system.physmem.readBursts 1631
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 104384
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 104384
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 222
+system.physmem.perBankRdBursts::1 131
+system.physmem.perBankRdBursts::2 152
+system.physmem.perBankRdBursts::3 119
+system.physmem.perBankRdBursts::4 123
+system.physmem.perBankRdBursts::5 94
+system.physmem.perBankRdBursts::6 45
+system.physmem.perBankRdBursts::7 71
+system.physmem.perBankRdBursts::8 25
+system.physmem.perBankRdBursts::9 46
+system.physmem.perBankRdBursts::10 59
+system.physmem.perBankRdBursts::11 61
+system.physmem.perBankRdBursts::12 118
+system.physmem.perBankRdBursts::13 123
+system.physmem.perBankRdBursts::14 145
+system.physmem.perBankRdBursts::15 97
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
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+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
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+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
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+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
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+system.physmem.numWrRetry 0
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+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1631
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1057
+system.physmem.rdQLenPdf::1 386
+system.physmem.rdQLenPdf::2 133
+system.physmem.rdQLenPdf::3 44
+system.physmem.rdQLenPdf::4 9
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+system.physmem.rdQLenPdf::9 0
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+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
+system.physmem.rdQLenPdf::19 0
+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
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+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 0
+system.physmem.wrQLenPdf::1 0
+system.physmem.wrQLenPdf::2 0
+system.physmem.wrQLenPdf::3 0
+system.physmem.wrQLenPdf::4 0
+system.physmem.wrQLenPdf::5 0
+system.physmem.wrQLenPdf::6 0
+system.physmem.wrQLenPdf::7 0
+system.physmem.wrQLenPdf::8 0
+system.physmem.wrQLenPdf::9 0
+system.physmem.wrQLenPdf::10 0
+system.physmem.wrQLenPdf::11 0
+system.physmem.wrQLenPdf::12 0
+system.physmem.wrQLenPdf::13 0
+system.physmem.wrQLenPdf::14 0
+system.physmem.wrQLenPdf::15 0
+system.physmem.wrQLenPdf::16 0
+system.physmem.wrQLenPdf::17 0
+system.physmem.wrQLenPdf::18 0
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+system.physmem.wrQLenPdf::20 0
+system.physmem.wrQLenPdf::21 0
+system.physmem.wrQLenPdf::22 0
+system.physmem.wrQLenPdf::23 0
+system.physmem.wrQLenPdf::24 0
+system.physmem.wrQLenPdf::25 0
+system.physmem.wrQLenPdf::26 0
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+system.physmem.wrQLenPdf::30 0
+system.physmem.wrQLenPdf::31 0
+system.physmem.wrQLenPdf::32 0
+system.physmem.wrQLenPdf::33 0
+system.physmem.wrQLenPdf::34 0
+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
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+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
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+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 400
+system.physmem.bytesPerActivate::mean 255.040000
+system.physmem.bytesPerActivate::gmean 165.833511
+system.physmem.bytesPerActivate::stdev 255.114458
+system.physmem.bytesPerActivate::0-127 153 38.25% 38.25%
+system.physmem.bytesPerActivate::128-255 90 22.50% 60.75%
+system.physmem.bytesPerActivate::256-383 68 17.00% 77.75%
+system.physmem.bytesPerActivate::384-511 24 6.00% 83.75%
+system.physmem.bytesPerActivate::512-639 18 4.50% 88.25%
+system.physmem.bytesPerActivate::640-767 18 4.50% 92.75%
+system.physmem.bytesPerActivate::768-895 6 1.50% 94.25%
+system.physmem.bytesPerActivate::896-1023 9 2.25% 96.50%
+system.physmem.bytesPerActivate::1024-1151 14 3.50% 100.00%
+system.physmem.bytesPerActivate::total 400
+system.physmem.totQLat 29262750
+system.physmem.totMemAccLat 59844000
+system.physmem.totBusLat 8155000
+system.physmem.avgQLat 17941.60
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 36691.60
+system.physmem.avgRdBW 428.50
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 428.50
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 3.35
+system.physmem.busUtilRead 3.35
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.35
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1223
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 74.98
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 149276.82
+system.physmem.pageHitRate 74.98
+system.physmem_0.actEnergy 1756440
+system.physmem_0.preEnergy 922185
+system.physmem_0.readEnergy 6832980
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 19053840.000000
+system.physmem_0.actBackEnergy 15603750
+system.physmem_0.preBackEnergy 420000
+system.physmem_0.actPowerDownEnergy 91000500
+system.physmem_0.prePowerDownEnergy 3351360
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 138941055
+system.physmem_0.averagePower 570.359725
+system.physmem_0.totalIdleTime 208219500
+system.physmem_0.memoryStateTime::IDLE 192250
+system.physmem_0.memoryStateTime::REF 8060000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 8725250
+system.physmem_0.memoryStateTime::ACT 27035000
+system.physmem_0.memoryStateTime::ACT_PDN 199589500
+system.physmem_1.actEnergy 1156680
+system.physmem_1.preEnergy 595815
+system.physmem_1.readEnergy 4812360
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 14751360.000000
+system.physmem_1.actBackEnergy 10992450
+system.physmem_1.preBackEnergy 722880
+system.physmem_1.actPowerDownEnergy 48652350
+system.physmem_1.prePowerDownEnergy 14106720
+system.physmem_1.selfRefreshEnergy 19460820
+system.physmem_1.totalEnergy 115251435
+system.physmem_1.averagePower 473.112694
+system.physmem_1.totalIdleTime 217047250
+system.physmem_1.memoryStateTime::IDLE 1273000
+system.physmem_1.memoryStateTime::REF 6258000
+system.physmem_1.memoryStateTime::SREF 74182750
+system.physmem_1.memoryStateTime::PRE_PDN 36736250
+system.physmem_1.memoryStateTime::ACT 18474250
+system.physmem_1.memoryStateTime::ACT_PDN 106677750
+system.pwrStateResidencyTicks::UNDEFINED 243602000
+system.cpu.branchPred.lookups 80739
+system.cpu.branchPred.condPredicted 55234
+system.cpu.branchPred.condIncorrect 16709
+system.cpu.branchPred.BTBLookups 66719
+system.cpu.branchPred.BTBHits 29812
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 44.682924
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 17634
+system.cpu.branchPred.indirectHits 9974
+system.cpu.branchPred.indirectMisses 7660
+system.cpu.branchPredindirectMispredicted 3727
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 182
+system.cpu.pwrStateResidencyTicks::ON 243602000
+system.cpu.numCycles 487205
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 92250
+system.cpu.fetch.Insts 369070
+system.cpu.fetch.Branches 80739
+system.cpu.fetch.predictedBranches 39786
+system.cpu.fetch.Cycles 270521
+system.cpu.fetch.SquashCycles 34268
+system.cpu.fetch.MiscStallCycles 231
+system.cpu.fetch.PendingTrapStallCycles 1420
+system.cpu.fetch.IcacheWaitRetryStallCycles 59
+system.cpu.fetch.CacheLines 61096
+system.cpu.fetch.IcacheSquashes 1928
+system.cpu.fetch.rateDist::samples 381615
+system.cpu.fetch.rateDist::mean 0.969383
+system.cpu.fetch.rateDist::stdev 0.966964
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 119805 31.39% 31.39%
+system.cpu.fetch.rateDist::1 192549 50.46% 81.85%
+system.cpu.fetch.rateDist::2 46684 12.23% 94.08%
+system.cpu.fetch.rateDist::3 12523 3.28% 97.37%
+system.cpu.fetch.rateDist::4 6183 1.62% 98.99%
+system.cpu.fetch.rateDist::5 2151 0.56% 99.55%
+system.cpu.fetch.rateDist::6 1338 0.35% 99.90%
+system.cpu.fetch.rateDist::7 126 0.03% 99.93%
+system.cpu.fetch.rateDist::8 256 0.07% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::total 381615
+system.cpu.fetch.branchRate 0.165719
+system.cpu.fetch.rate 0.757525
+system.cpu.decode.IdleCycles 106114
+system.cpu.decode.BlockedCycles 29186
+system.cpu.decode.RunCycles 234250
+system.cpu.decode.UnblockCycles 1120
+system.cpu.decode.SquashCycles 10945
+system.cpu.decode.BranchResolved 28858
+system.cpu.decode.BranchMispred 6374
+system.cpu.decode.DecodedInsts 334613
+system.cpu.decode.SquashedInsts 10033
+system.cpu.rename.SquashCycles 10945
+system.cpu.rename.IdleCycles 118199
+system.cpu.rename.BlockCycles 3392
+system.cpu.rename.serializeStallCycles 20508
+system.cpu.rename.RunCycles 223269
+system.cpu.rename.UnblockCycles 5302
+system.cpu.rename.RenamedInsts 321518
+system.cpu.rename.ROBFullEvents 5
+system.cpu.rename.IQFullEvents 6
+system.cpu.rename.LQFullEvents 2019
+system.cpu.rename.SQFullEvents 2488
+system.cpu.rename.RenamedOperands 216877
+system.cpu.rename.RenameLookups 393562
+system.cpu.rename.int_rename_lookups 393262
+system.cpu.rename.fp_rename_lookups 300
+system.cpu.rename.CommittedMaps 178355
+system.cpu.rename.UndoneMaps 38522
+system.cpu.rename.serializingInsts 1018
+system.cpu.rename.tempSerializingInsts 1018
+system.cpu.rename.skidInsts 1732
+system.cpu.memDep0.insertedLoads 76736
+system.cpu.memDep0.insertedStores 44216
+system.cpu.memDep0.conflictingLoads 477
+system.cpu.memDep0.conflictingStores 50
+system.cpu.iq.iqInstsAdded 297572
+system.cpu.iq.iqNonSpecInstsAdded 1822
+system.cpu.iq.iqInstsIssued 294276
+system.cpu.iq.iqSquashedInstsIssued 313
+system.cpu.iq.iqSquashedInstsExamined 31633
+system.cpu.iq.iqSquashedOperandsExamined 14101
+system.cpu.iq.iqSquashedNonSpecRemoved 75
+system.cpu.iq.issued_per_cycle::samples 381615
+system.cpu.iq.issued_per_cycle::mean 0.771133
+system.cpu.iq.issued_per_cycle::stdev 0.841803
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 163391 42.82% 42.82%
+system.cpu.iq.issued_per_cycle::1 161707 42.37% 85.19%
+system.cpu.iq.issued_per_cycle::2 41029 10.75% 95.94%
+system.cpu.iq.issued_per_cycle::3 12774 3.35% 99.29%
+system.cpu.iq.issued_per_cycle::4 1779 0.47% 99.75%
+system.cpu.iq.issued_per_cycle::5 668 0.18% 99.93%
+system.cpu.iq.issued_per_cycle::6 177 0.05% 99.98%
+system.cpu.iq.issued_per_cycle::7 49 0.01% 99.99%
+system.cpu.iq.issued_per_cycle::8 41 0.01% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 8
+system.cpu.iq.issued_per_cycle::total 381615
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 17 6.97% 6.97%
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.97%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.97%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.97%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.97%
+system.cpu.iq.fu_full::MemRead 38 15.57% 22.54%
+system.cpu.iq.fu_full::MemWrite 186 76.23% 98.77%
+system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.77%
+system.cpu.iq.fu_full::FloatMemWrite 3 1.23% 100.00%
+system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00%
+system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00%
+system.cpu.iq.FU_type_0::No_OpClass 191 0.06% 0.06%
+system.cpu.iq.FU_type_0::IntAlu 174238 59.21% 59.27%
+system.cpu.iq.FU_type_0::IntMult 438 0.15% 59.42%
+system.cpu.iq.FU_type_0::IntDiv 231 0.08% 59.50%
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 59.50%
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.50%
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.50%
+system.cpu.iq.FU_type_0::FloatMult 32 0.01% 59.51%
+system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.51%
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.51%
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+system.cpu.toL2Bus.snoop_fanout::mean 0
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+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
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+system.cpu.toL2Bus.reqLayer0.utilization 0.4
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+system.cpu.toL2Bus.respLayer0.utilization 0.7
+system.cpu.toL2Bus.respLayer1.occupancy 739500
+system.cpu.toL2Bus.respLayer1.utilization 0.3
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+system.membus.snoop_filter.hit_multi_requests 0
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+system.membus.trans_dist::ReadExReq 218
+system.membus.trans_dist::ReadExResp 218
+system.membus.trans_dist::ReadSharedReq 1413
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3262
+system.membus.pkt_count::total 3262
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 104384
+system.membus.pkt_size::total 104384
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1631
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1631 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1631
+system.membus.reqLayer0.occupancy 2012500
+system.membus.reqLayer0.utilization 0.8
+system.membus.respLayer1.occupancy 8687000
+system.membus.respLayer1.utilization 3.6
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=atomic
+mem_ranges=
+memories=system.physmem
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+fastmem=false
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+simulate_data_stalls=false
+simulate_inst_stalls=false
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:134217727:0:0:0:0
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.icache_port",
+ "system.cpu.dcache_port"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "range": "0:134217727:0:0:0:0",
+ "latency": 30000,
+ "name": "physmem",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "kvm_map": true,
+ "clk_domain": "system.clk_domain",
+ "power_model": null,
+ "latency_var": 0,
+ "bandwidth": "73.000000",
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.physmem",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "atomic",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simulate_data_stalls": false,
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "AtomicSimpleCPU",
+ "max_loads_all_threads": 0,
+ "system": "system",
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "width": 1,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "do_quiesce": true,
+ "type": "AtomicSimpleCPU",
+ "fastmem": false,
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "simulate_inst_stalls": false,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1348
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic
+
+Global frequency set at 1000000000000 ticks per second
+lui: PASS
+lui, negative: PASS
+auipc: 0x184D6
+auipc: PASS
+jal: PASS
+jalr: PASS
+beq, equal: PASS
+beq, not equal: PASS
+bne, equal: PASS
+bne, not equal: PASS
+blt, less: PASS
+blt, equal: PASS
+blt, greater: PASS
+bge, less: PASS
+bge, equal: PASS
+bge, greater: PASS
+bltu, greater: PASS
+bltu, equal: PASS
+bltu, less: PASS
+bgeu, greater: PASS
+bgeu, equal: PASS
+bgeu, less: PASS
+lb, positive: PASS
+lb, negative: PASS
+lh, positive: PASS
+lh, negative: PASS
+lw, positive: PASS
+lw, negative: PASS
+lbu: PASS
+lhu: PASS
+sb: PASS
+sh: PASS
+sw: PASS
+addi: PASS
+addi, overflow: PASS
+slti, true: PASS
+slti, false: PASS
+sltiu, false: PASS
+sltiu, true: PASS
+xori (1): PASS
+xori (0): PASS
+ori (1): PASS
+ori (A): PASS
+andi (0): PASS
+andi (1): PASS
+slli, general: PASS
+slli, erase: PASS
+srli, general: PASS
+srli, erase: PASS
+srli, negative: PASS
+srai, general: PASS
+srai, erase: PASS
+srai, negative: PASS
+add: PASS
+add, overflow: PASS
+sub: PASS
+sub, "overflow": PASS
+sll, general: PASS
+sll, erase: PASS
+slt, true: PASS
+slt, false: PASS
+sltu, false: PASS
+sltu, true: PASS
+xor (1): PASS
+xor (0): PASS
+srl, general: PASS
+srl, erase: PASS
+srl, negative: PASS
+sra, general: PASS
+sra, erase: PASS
+sra, negative: PASS
+or (1): PASS
+or (A): PASS
+and (0): PASS
+and (-1): PASS
+Bytes written: 15
+open, write: PASS
+access F_OK: PASS
+access R_OK: PASS
+access W_OK: PASS
+access X_OK: PASS
+stat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+fstat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+open, stat: PASS
+Bytes read: 15
+String read: this is a test
+open, read, unlink: PASS
+times:
+ tms_utime = 0
+ tms_stime = 0
+ tms_cutime = 0
+ tms_cstime = 0
+times: \e[1;31mFAIL\e[0m (expected 1; found 0)
+timeval:
+ tv_sec = 1000000000
+ tv_usec = 118
+gettimeofday: PASS
+Cycles: 243487
+rdcycle: PASS
+Time: 1499980274
+rdtime: PASS
+Instructions Retired: 214447
+rdinstret: PASS
+lwu: PASS
+ld: PASS
+sd: PASS
+addiw: PASS
+addiw, overflow: PASS
+addiw, truncate: PASS
+slliw, general: PASS
+slliw, erase: PASS
+slliw, truncate: PASS
+srliw, general: PASS
+srliw, erase: PASS
+srliw, negative: PASS
+srliw, truncate: PASS
+sraiw, general: PASS
+sraiw, erase: PASS
+sraiw, negative: PASS
+sraiw, truncate: PASS
+addw: PASS
+addw, overflow: PASS
+addw, truncate: PASS
+subw: PASS
+subw, "overflow": PASS
+subw, truncate: PASS
+sllw, general: PASS
+sllw, erase: PASS
+sllw, truncate: PASS
+srlw, general: PASS
+srlw, erase: PASS
+srlw, negative: PASS
+srlw, truncate: PASS
+sraw, general: PASS
+sraw, erase: PASS
+sraw, negative: PASS
+sraw, truncate: PASS
+Exiting @ tick 155449500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000155
+sim_ticks 155449500
+final_tick 155449500
+sim_freq 1000000000000
+host_inst_rate 2592
+host_op_rate 2599
+host_tick_rate 1508911
+host_mem_usage 259244
+host_seconds 103.02
+sim_insts 266983
+sim_ops 267753
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 155449500
+system.physmem.bytes_read::cpu.inst 1240520
+system.physmem.bytes_read::cpu.data 453141
+system.physmem.bytes_read::total 1693661
+system.physmem.bytes_inst_read::cpu.inst 1240520
+system.physmem.bytes_inst_read::total 1240520
+system.physmem.bytes_written::cpu.data 283069
+system.physmem.bytes_written::total 283069
+system.physmem.num_reads::cpu.inst 310130
+system.physmem.num_reads::cpu.data 67806
+system.physmem.num_reads::total 377936
+system.physmem.num_writes::cpu.data 41531
+system.physmem.num_writes::total 41531
+system.physmem.bw_read::cpu.inst 7980212223
+system.physmem.bw_read::cpu.data 2915036716
+system.physmem.bw_read::total 10895248939
+system.physmem.bw_inst_read::cpu.inst 7980212223
+system.physmem.bw_inst_read::total 7980212223
+system.physmem.bw_write::cpu.data 1820970798
+system.physmem.bw_write::total 1820970798
+system.physmem.bw_total::cpu.inst 7980212223
+system.physmem.bw_total::cpu.data 4736007514
+system.physmem.bw_total::total 12716219737
+system.pwrStateResidencyTicks::UNDEFINED 155449500
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 182
+system.cpu.pwrStateResidencyTicks::ON 155449500
+system.cpu.numCycles 310900
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 266983
+system.cpu.committedOps 267753
+system.cpu.num_int_alu_accesses 266336
+system.cpu.num_fp_alu_accesses 12
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 15688
+system.cpu.num_conditional_control_insts 41227
+system.cpu.num_int_insts 266336
+system.cpu.num_fp_insts 12
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 334534
+system.cpu.num_int_register_writes 178355
+system.cpu.num_fp_register_reads 12
+system.cpu.num_fp_register_writes 0
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 109337
+system.cpu.num_load_insts 67806
+system.cpu.num_store_insts 41531
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 310900
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 56915
+system.cpu.op_class::No_OpClass 191 0.07% 0.07%
+system.cpu.op_class::IntAlu 157741 58.87% 58.94%
+system.cpu.op_class::IntMult 436 0.16% 59.11%
+system.cpu.op_class::IntDiv 230 0.09% 59.19%
+system.cpu.op_class::FloatAdd 0 0.00% 59.19%
+system.cpu.op_class::FloatCmp 0 0.00% 59.19%
+system.cpu.op_class::FloatCvt 0 0.00% 59.19%
+system.cpu.op_class::FloatMult 0 0.00% 59.19%
+system.cpu.op_class::FloatMultAcc 0 0.00% 59.19%
+system.cpu.op_class::FloatDiv 0 0.00% 59.19%
+system.cpu.op_class::FloatMisc 0 0.00% 59.19%
+system.cpu.op_class::FloatSqrt 0 0.00% 59.19%
+system.cpu.op_class::SimdAdd 0 0.00% 59.19%
+system.cpu.op_class::SimdAddAcc 0 0.00% 59.19%
+system.cpu.op_class::SimdAlu 0 0.00% 59.19%
+system.cpu.op_class::SimdCmp 0 0.00% 59.19%
+system.cpu.op_class::SimdCvt 0 0.00% 59.19%
+system.cpu.op_class::SimdMisc 0 0.00% 59.19%
+system.cpu.op_class::SimdMult 0 0.00% 59.19%
+system.cpu.op_class::SimdMultAcc 0 0.00% 59.19%
+system.cpu.op_class::SimdShift 0 0.00% 59.19%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 59.19%
+system.cpu.op_class::SimdSqrt 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatMult 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.19%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.19%
+system.cpu.op_class::MemRead 67806 25.31% 84.50%
+system.cpu.op_class::MemWrite 41519 15.50% 100.00%
+system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 12 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 267935
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 155449500
+system.membus.trans_dist::ReadReq 377157
+system.membus.trans_dist::ReadResp 377936
+system.membus.trans_dist::WriteReq 40752
+system.membus.trans_dist::WriteResp 40752
+system.membus.trans_dist::LoadLockedReq 779
+system.membus.trans_dist::StoreCondReq 779
+system.membus.trans_dist::StoreCondResp 779
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 620260
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 218674
+system.membus.pkt_count::total 838934
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1240520
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 736210
+system.membus.pkt_size::total 1976730
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 419467
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 419467 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 419467
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=0:268435455:0:0:0:0
+memories=system.mem_ctrls
+mmap_using_noreserve=false
+multi_thread=false
+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=clk_domain dtb interrupts isa itb tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu.clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
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+
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--- /dev/null
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+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers1.port_buffers11",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers12",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers1.port_buffers12",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers13",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers1.port_buffers13",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers14",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers1.port_buffers14",
+ "type": "MessageBuffer"
+ }
+ ]
+ },
+ {
+ "router_id": 2,
+ "latency": 1,
+ "name": "routers2",
+ "p_state_clk_gate_min": 1,
+ "virt_nets": 5,
+ "p_state_clk_gate_bins": 20,
+ "cxx_class": "Switch",
+ "clk_domain": "system.ruby.clk_domain",
+ "power_model": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "path": "system.ruby.network.routers2",
+ "type": "Switch",
+ "port_buffers": [
+ {
+ "ordered": true,
+ "name": "port_buffers00",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers00",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers01",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers01",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers02",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers02",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers03",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers03",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers04",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers04",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers05",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers05",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers06",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers06",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers07",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers07",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers08",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers08",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers09",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers09",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers10",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers10",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers11",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers11",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers12",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers12",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers13",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers13",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers14",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers14",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers15",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers15",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers16",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers16",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers17",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers17",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers18",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers18",
+ "type": "MessageBuffer"
+ },
+ {
+ "ordered": true,
+ "name": "port_buffers19",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.network.routers2.port_buffers19",
+ "type": "MessageBuffer"
+ }
+ ]
+ }
+ ],
+ "power_model": null,
+ "netifs": [],
+ "control_msg_size": 8,
+ "buffer_size": 0,
+ "endpoint_bandwidth": 1000,
+ "ruby_system": "system.ruby",
+ "name": "network",
+ "p_state_clk_gate_bins": 20,
+ "ext_links": [
+ {
+ "latency": 1,
+ "name": "ext_links0",
+ "weight": 1,
+ "ext_node": "system.ruby.l1_cntrl0",
+ "link_id": 0,
+ "eventq_index": 0,
+ "cxx_class": "SimpleExtLink",
+ "path": "system.ruby.network.ext_links0",
+ "int_node": "system.ruby.network.routers0",
+ "type": "SimpleExtLink",
+ "bandwidth_factor": 16
+ },
+ {
+ "latency": 1,
+ "name": "ext_links1",
+ "weight": 1,
+ "ext_node": "system.ruby.dir_cntrl0",
+ "link_id": 1,
+ "eventq_index": 0,
+ "cxx_class": "SimpleExtLink",
+ "path": "system.ruby.network.ext_links1",
+ "int_node": "system.ruby.network.routers1",
+ "type": "SimpleExtLink",
+ "bandwidth_factor": 16
+ }
+ ],
+ "number_of_virtual_networks": 5,
+ "path": "system.ruby.network"
+ },
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.ruby.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "phys_mem": null,
+ "type": "RubySystem",
+ "p_state_clk_gate_min": 1,
+ "hot_lines": false,
+ "power_model": null,
+ "path": "system.ruby",
+ "memctrl_clk_domain": {
+ "name": "memctrl_clk_domain",
+ "clk_domain": "system.ruby.clk_domain",
+ "eventq_index": 0,
+ "cxx_class": "DerivedClockDomain",
+ "path": "system.ruby.memctrl_clk_domain",
+ "type": "DerivedClockDomain",
+ "clk_divider": 3
+ },
+ "name": "ruby",
+ "p_state_clk_gate_bins": 20,
+ "block_size_bytes": 64,
+ "access_backing_store": false,
+ "number_of_virtual_networks": 5,
+ "num_of_sequencers": 1,
+ "dir_cntrl0": {
+ "system": "system",
+ "cluster_id": 0,
+ "responseFromMemory": {
+ "ordered": false,
+ "name": "responseFromMemory",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.responseFromMemory",
+ "type": "MessageBuffer"
+ },
+ "cxx_class": "Directory_Controller",
+ "forwardFromDir": {
+ "ordered": false,
+ "name": "forwardFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[4]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.forwardFromDir",
+ "type": "MessageBuffer"
+ },
+ "dmaRequestToDir": {
+ "ordered": true,
+ "name": "dmaRequestToDir",
+ "cxx_class": "MessageBuffer",
+ "slave": {
+ "peer": "system.ruby.network.master[3]",
+ "role": "SLAVE"
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.dmaRequestToDir",
+ "type": "MessageBuffer"
+ },
+ "type": "Directory_Controller",
+ "recycle_latency": 10,
+ "clk_domain": "system.ruby.clk_domain",
+ "version": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "directory_latency": 12,
+ "number_of_TBEs": 256,
+ "to_memory_controller_latency": 1,
+ "p_state_clk_gate_min": 1,
+ "responseFromDir": {
+ "ordered": false,
+ "name": "responseFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[2]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.responseFromDir",
+ "type": "MessageBuffer"
+ },
+ "transitions_per_cycle": 32,
+ "memory": {
+ "peer": "system.mem_ctrls.port",
+ "role": "MASTER"
+ },
+ "power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
+ "buffer_size": 0,
+ "ruby_system": "system.ruby",
+ "requestToDir": {
+ "ordered": true,
+ "name": "requestToDir",
+ "cxx_class": "MessageBuffer",
+ "slave": {
+ "peer": "system.ruby.network.master[2]",
+ "role": "SLAVE"
+ },
+ "randomization": false,
+ "eventq_index": 0,
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.requestToDir",
+ "type": "MessageBuffer"
+ },
+ "dmaResponseFromDir": {
+ "ordered": true,
+ "name": "dmaResponseFromDir",
+ "cxx_class": "MessageBuffer",
+ "randomization": false,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.ruby.network.slave[3]",
+ "role": "MASTER"
+ },
+ "buffer_size": 0,
+ "path": "system.ruby.dir_cntrl0.dmaResponseFromDir",
+ "type": "MessageBuffer"
+ },
+ "name": "dir_cntrl0",
+ "p_state_clk_gate_bins": 20,
+ "directory": {
+ "name": "directory",
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
+ "eventq_index": 0,
+ "cxx_class": "DirectoryMemory",
+ "path": "system.ruby.dir_cntrl0.directory",
+ "type": "RubyDirectoryMemory"
+ },
+ "path": "system.ruby.dir_cntrl0"
+ }
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "system": "system",
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "TimingSimpleCPU",
+ "max_loads_all_threads": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "do_quiesce": true,
+ "type": "TimingSimpleCPU",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ },
+ "multi_thread": false,
+ "mem_ctrls": [
+ {
+ "static_frontend_latency": 10,
+ "tRFC": 260,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 8,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.ruby.dir_cntrl0.memory",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.032",
+ "p_state_clk_gate_min": 1,
+ "null": false,
+ "IDD2P1": "0.032",
+ "eventq_index": 0,
+ "tRRD": 6,
+ "tRTW": 3,
+ "IDD4R": "0.157",
+ "burst_length": 8,
+ "tRTP": 8,
+ "IDD4W": "0.125",
+ "tWR": 15,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000,
+ "IDD6": "0.02",
+ "IDD5": "0.235",
+ "tRCD": 14,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "tRRD_L": 0,
+ "IDD0": "0.055",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 3,
+ "power_model": null,
+ "tCL": 14,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1,
+ "tRAS": 35,
+ "tRP": 14,
+ "tBURST": 5,
+ "path": "system.mem_ctrls",
+ "tXP": 6,
+ "tXS": 270,
+ "addr_mapping": "RoRaBaCoCh",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.038",
+ "IDD3N": "0.038",
+ "name": "mem_ctrls",
+ "tXSDLL": 0,
+ "device_size": 536870912,
+ "kvm_map": true,
+ "dll": true,
+ "tXAW": 30,
+ "write_low_thresh_perc": 50,
+ "range": "0:268435455:5:19:0:0",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "p_state_clk_gate_bins": 20,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800
+ }
+ ],
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1349
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby
+
+Global frequency set at 1000000000 ticks per second
+lui: PASS
+lui, negative: PASS
+auipc: 0x184D6
+auipc: PASS
+jal: PASS
+jalr: PASS
+beq, equal: PASS
+beq, not equal: PASS
+bne, equal: PASS
+bne, not equal: PASS
+blt, less: PASS
+blt, equal: PASS
+blt, greater: PASS
+bge, less: PASS
+bge, equal: PASS
+bge, greater: PASS
+bltu, greater: PASS
+bltu, equal: PASS
+bltu, less: PASS
+bgeu, greater: PASS
+bgeu, equal: PASS
+bgeu, less: PASS
+lb, positive: PASS
+lb, negative: PASS
+lh, positive: PASS
+lh, negative: PASS
+lw, positive: PASS
+lw, negative: PASS
+lbu: PASS
+lhu: PASS
+sb: PASS
+sh: PASS
+sw: PASS
+addi: PASS
+addi, overflow: PASS
+slti, true: PASS
+slti, false: PASS
+sltiu, false: PASS
+sltiu, true: PASS
+xori (1): PASS
+xori (0): PASS
+ori (1): PASS
+ori (A): PASS
+andi (0): PASS
+andi (1): PASS
+slli, general: PASS
+slli, erase: PASS
+srli, general: PASS
+srli, erase: PASS
+srli, negative: PASS
+srai, general: PASS
+srai, erase: PASS
+srai, negative: PASS
+add: PASS
+add, overflow: PASS
+sub: PASS
+sub, "overflow": PASS
+sll, general: PASS
+sll, erase: PASS
+slt, true: PASS
+slt, false: PASS
+sltu, false: PASS
+sltu, true: PASS
+xor (1): PASS
+xor (0): PASS
+srl, general: PASS
+srl, erase: PASS
+srl, negative: PASS
+sra, general: PASS
+sra, erase: PASS
+sra, negative: PASS
+or (1): PASS
+or (A): PASS
+and (0): PASS
+and (-1): PASS
+Bytes written: 15
+open, write: PASS
+access F_OK: PASS
+access R_OK: PASS
+access W_OK: PASS
+access X_OK: PASS
+stat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+fstat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+open, stat: PASS
+Bytes read: 15
+String read: this is a test
+open, read, unlink: PASS
+times:
+ tms_utime = 0
+ tms_stime = 0
+ tms_cutime = 0
+ tms_cstime = 0
+times: \e[1;31mFAIL\e[0m (expected 1; found 0)
+timeval:
+ tv_sec = 1000000000
+ tv_usec = 3837
+gettimeofday: PASS
+Cycles: 3938511
+rdcycle: PASS
+Time: 1499980275
+rdtime: PASS
+Instructions Retired: 214479
+rdinstret: PASS
+lwu: PASS
+ld: PASS
+sd: PASS
+addiw: PASS
+addiw, overflow: PASS
+addiw, truncate: PASS
+slliw, general: PASS
+slliw, erase: PASS
+slliw, truncate: PASS
+srliw, general: PASS
+srliw, erase: PASS
+srliw, negative: PASS
+srliw, truncate: PASS
+sraiw, general: PASS
+sraiw, erase: PASS
+sraiw, negative: PASS
+sraiw, truncate: PASS
+addw: PASS
+addw, overflow: PASS
+addw, truncate: PASS
+subw: PASS
+subw, "overflow": PASS
+subw, truncate: PASS
+sllw, general: PASS
+sllw, erase: PASS
+sllw, truncate: PASS
+srlw, general: PASS
+srlw, erase: PASS
+srlw, negative: PASS
+srlw, truncate: PASS
+sraw, general: PASS
+sraw, erase: PASS
+sraw, negative: PASS
+sraw, truncate: PASS
+Exiting @ tick 5116735 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.005117
+sim_ticks 5116735
+final_tick 5116735
+sim_freq 1000000000
+host_inst_rate 2592
+host_op_rate 2600
+host_tick_rate 49673
+host_mem_usage 439732
+host_seconds 103.01
+sim_insts 267015
+sim_ops 267785
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5116735
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4826944
+system.mem_ctrls.bytes_read::total 4826944
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4826688
+system.mem_ctrls.bytes_written::total 4826688
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 75421
+system.mem_ctrls.num_reads::total 75421
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 75417
+system.mem_ctrls.num_writes::total 75417
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 943364079
+system.mem_ctrls.bw_read::total 943364079
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 943314047
+system.mem_ctrls.bw_write::total 943314047
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1886678126
+system.mem_ctrls.bw_total::total 1886678126
+system.mem_ctrls.readReqs 75421
+system.mem_ctrls.writeReqs 75417
+system.mem_ctrls.readBursts 75421
+system.mem_ctrls.writeBursts 75417
+system.mem_ctrls.bytesReadDRAM 2399616
+system.mem_ctrls.bytesReadWrQ 2427328
+system.mem_ctrls.bytesWritten 2507072
+system.mem_ctrls.bytesReadSys 4826944
+system.mem_ctrls.bytesWrittenSys 4826688
+system.mem_ctrls.servicedByWrQ 37927
+system.mem_ctrls.mergedWrBursts 36225
+system.mem_ctrls.neitherReadNorWriteReqs 0
+system.mem_ctrls.perBankRdBursts::0 9427
+system.mem_ctrls.perBankRdBursts::1 1709
+system.mem_ctrls.perBankRdBursts::2 836
+system.mem_ctrls.perBankRdBursts::3 1322
+system.mem_ctrls.perBankRdBursts::4 2448
+system.mem_ctrls.perBankRdBursts::5 5376
+system.mem_ctrls.perBankRdBursts::6 192
+system.mem_ctrls.perBankRdBursts::7 137
+system.mem_ctrls.perBankRdBursts::8 54
+system.mem_ctrls.perBankRdBursts::9 224
+system.mem_ctrls.perBankRdBursts::10 819
+system.mem_ctrls.perBankRdBursts::11 1647
+system.mem_ctrls.perBankRdBursts::12 4044
+system.mem_ctrls.perBankRdBursts::13 1798
+system.mem_ctrls.perBankRdBursts::14 6564
+system.mem_ctrls.perBankRdBursts::15 897
+system.mem_ctrls.perBankWrBursts::0 10076
+system.mem_ctrls.perBankWrBursts::1 1700
+system.mem_ctrls.perBankWrBursts::2 866
+system.mem_ctrls.perBankWrBursts::3 1330
+system.mem_ctrls.perBankWrBursts::4 2482
+system.mem_ctrls.perBankWrBursts::5 5586
+system.mem_ctrls.perBankWrBursts::6 200
+system.mem_ctrls.perBankWrBursts::7 142
+system.mem_ctrls.perBankWrBursts::8 57
+system.mem_ctrls.perBankWrBursts::9 224
+system.mem_ctrls.perBankWrBursts::10 821
+system.mem_ctrls.perBankWrBursts::11 1756
+system.mem_ctrls.perBankWrBursts::12 4248
+system.mem_ctrls.perBankWrBursts::13 1812
+system.mem_ctrls.perBankWrBursts::14 6954
+system.mem_ctrls.perBankWrBursts::15 919
+system.mem_ctrls.numRdRetry 0
+system.mem_ctrls.numWrRetry 0
+system.mem_ctrls.totGap 5116653
+system.mem_ctrls.readPktSize::0 0
+system.mem_ctrls.readPktSize::1 0
+system.mem_ctrls.readPktSize::2 0
+system.mem_ctrls.readPktSize::3 0
+system.mem_ctrls.readPktSize::4 0
+system.mem_ctrls.readPktSize::5 0
+system.mem_ctrls.readPktSize::6 75421
+system.mem_ctrls.writePktSize::0 0
+system.mem_ctrls.writePktSize::1 0
+system.mem_ctrls.writePktSize::2 0
+system.mem_ctrls.writePktSize::3 0
+system.mem_ctrls.writePktSize::4 0
+system.mem_ctrls.writePktSize::5 0
+system.mem_ctrls.writePktSize::6 75417
+system.mem_ctrls.rdQLenPdf::0 37494
+system.mem_ctrls.rdQLenPdf::1 0
+system.mem_ctrls.rdQLenPdf::2 0
+system.mem_ctrls.rdQLenPdf::3 0
+system.mem_ctrls.rdQLenPdf::4 0
+system.mem_ctrls.rdQLenPdf::5 0
+system.mem_ctrls.rdQLenPdf::6 0
+system.mem_ctrls.rdQLenPdf::7 0
+system.mem_ctrls.rdQLenPdf::8 0
+system.mem_ctrls.rdQLenPdf::9 0
+system.mem_ctrls.rdQLenPdf::10 0
+system.mem_ctrls.rdQLenPdf::11 0
+system.mem_ctrls.rdQLenPdf::12 0
+system.mem_ctrls.rdQLenPdf::13 0
+system.mem_ctrls.rdQLenPdf::14 0
+system.mem_ctrls.rdQLenPdf::15 0
+system.mem_ctrls.rdQLenPdf::16 0
+system.mem_ctrls.rdQLenPdf::17 0
+system.mem_ctrls.rdQLenPdf::18 0
+system.mem_ctrls.rdQLenPdf::19 0
+system.mem_ctrls.rdQLenPdf::20 0
+system.mem_ctrls.rdQLenPdf::21 0
+system.mem_ctrls.rdQLenPdf::22 0
+system.mem_ctrls.rdQLenPdf::23 0
+system.mem_ctrls.rdQLenPdf::24 0
+system.mem_ctrls.rdQLenPdf::25 0
+system.mem_ctrls.rdQLenPdf::26 0
+system.mem_ctrls.rdQLenPdf::27 0
+system.mem_ctrls.rdQLenPdf::28 0
+system.mem_ctrls.rdQLenPdf::29 0
+system.mem_ctrls.rdQLenPdf::30 0
+system.mem_ctrls.rdQLenPdf::31 0
+system.mem_ctrls.wrQLenPdf::0 1
+system.mem_ctrls.wrQLenPdf::1 1
+system.mem_ctrls.wrQLenPdf::2 1
+system.mem_ctrls.wrQLenPdf::3 1
+system.mem_ctrls.wrQLenPdf::4 1
+system.mem_ctrls.wrQLenPdf::5 1
+system.mem_ctrls.wrQLenPdf::6 1
+system.mem_ctrls.wrQLenPdf::7 1
+system.mem_ctrls.wrQLenPdf::8 1
+system.mem_ctrls.wrQLenPdf::9 1
+system.mem_ctrls.wrQLenPdf::10 1
+system.mem_ctrls.wrQLenPdf::11 1
+system.mem_ctrls.wrQLenPdf::12 1
+system.mem_ctrls.wrQLenPdf::13 1
+system.mem_ctrls.wrQLenPdf::14 1
+system.mem_ctrls.wrQLenPdf::15 278
+system.mem_ctrls.wrQLenPdf::16 320
+system.mem_ctrls.wrQLenPdf::17 2066
+system.mem_ctrls.wrQLenPdf::18 2441
+system.mem_ctrls.wrQLenPdf::19 2481
+system.mem_ctrls.wrQLenPdf::20 2497
+system.mem_ctrls.wrQLenPdf::21 2551
+system.mem_ctrls.wrQLenPdf::22 2509
+system.mem_ctrls.wrQLenPdf::23 2416
+system.mem_ctrls.wrQLenPdf::24 2402
+system.mem_ctrls.wrQLenPdf::25 2403
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+system.mem_ctrls.wrQLenPdf::29 2402
+system.mem_ctrls.wrQLenPdf::30 2401
+system.mem_ctrls.wrQLenPdf::31 2401
+system.mem_ctrls.wrQLenPdf::32 2401
+system.mem_ctrls.wrQLenPdf::33 2
+system.mem_ctrls.wrQLenPdf::34 1
+system.mem_ctrls.wrQLenPdf::35 0
+system.mem_ctrls.wrQLenPdf::36 0
+system.mem_ctrls.wrQLenPdf::37 0
+system.mem_ctrls.wrQLenPdf::38 0
+system.mem_ctrls.wrQLenPdf::39 0
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+system.mem_ctrls.wrQLenPdf::41 0
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+system.mem_ctrls.wrQLenPdf::48 0
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+system.mem_ctrls.wrQLenPdf::58 0
+system.mem_ctrls.wrQLenPdf::59 0
+system.mem_ctrls.wrQLenPdf::60 0
+system.mem_ctrls.wrQLenPdf::61 0
+system.mem_ctrls.wrQLenPdf::62 0
+system.mem_ctrls.wrQLenPdf::63 0
+system.mem_ctrls.bytesPerActivate::samples 19854
+system.mem_ctrls.bytesPerActivate::mean 247.067593
+system.mem_ctrls.bytesPerActivate::gmean 170.034775
+system.mem_ctrls.bytesPerActivate::stdev 232.007749
+system.mem_ctrls.bytesPerActivate::0-127 6244 31.45% 31.45%
+system.mem_ctrls.bytesPerActivate::128-255 5972 30.08% 61.53%
+system.mem_ctrls.bytesPerActivate::256-383 2912 14.67% 76.20%
+system.mem_ctrls.bytesPerActivate::384-511 1915 9.65% 85.84%
+system.mem_ctrls.bytesPerActivate::512-639 1197 6.03% 91.87%
+system.mem_ctrls.bytesPerActivate::640-767 490 2.47% 94.34%
+system.mem_ctrls.bytesPerActivate::768-895 315 1.59% 95.93%
+system.mem_ctrls.bytesPerActivate::896-1023 221 1.11% 97.04%
+system.mem_ctrls.bytesPerActivate::1024-1151 588 2.96% 100.00%
+system.mem_ctrls.bytesPerActivate::total 19854
+system.mem_ctrls.rdPerTurnAround::samples 2401
+system.mem_ctrls.rdPerTurnAround::mean 15.614327
+system.mem_ctrls.rdPerTurnAround::gmean 15.546038
+system.mem_ctrls.rdPerTurnAround::stdev 1.481394
+system.mem_ctrls.rdPerTurnAround::12-13 161 6.71% 6.71%
+system.mem_ctrls.rdPerTurnAround::14-15 983 40.94% 47.65%
+system.mem_ctrls.rdPerTurnAround::16-17 1037 43.19% 90.84%
+system.mem_ctrls.rdPerTurnAround::18-19 206 8.58% 99.42%
+system.mem_ctrls.rdPerTurnAround::20-21 13 0.54% 99.96%
+system.mem_ctrls.rdPerTurnAround::32-33 1 0.04% 100.00%
+system.mem_ctrls.rdPerTurnAround::total 2401
+system.mem_ctrls.wrPerTurnAround::samples 2401
+system.mem_ctrls.wrPerTurnAround::mean 16.315285
+system.mem_ctrls.wrPerTurnAround::gmean 16.295426
+system.mem_ctrls.wrPerTurnAround::stdev 0.838235
+system.mem_ctrls.wrPerTurnAround::16 2077 86.51% 86.51%
+system.mem_ctrls.wrPerTurnAround::17 33 1.37% 87.88%
+system.mem_ctrls.wrPerTurnAround::18 158 6.58% 94.46%
+system.mem_ctrls.wrPerTurnAround::19 124 5.16% 99.63%
+system.mem_ctrls.wrPerTurnAround::20 9 0.37% 100.00%
+system.mem_ctrls.wrPerTurnAround::total 2401
+system.mem_ctrls.totQLat 852328
+system.mem_ctrls.totMemAccLat 1564714
+system.mem_ctrls.totBusLat 187470
+system.mem_ctrls.avgQLat 22.73
+system.mem_ctrls.avgBusLat 5.00
+system.mem_ctrls.avgMemAccLat 41.73
+system.mem_ctrls.avgRdBW 468.97
+system.mem_ctrls.avgWrBW 489.97
+system.mem_ctrls.avgRdBWSys 943.36
+system.mem_ctrls.avgWrBWSys 943.31
+system.mem_ctrls.peakBW 12800.00
+system.mem_ctrls.busUtil 7.49
+system.mem_ctrls.busUtilRead 3.66
+system.mem_ctrls.busUtilWrite 3.83
+system.mem_ctrls.avgRdQLen 1.00
+system.mem_ctrls.avgWrQLen 25.94
+system.mem_ctrls.readRowHits 22215
+system.mem_ctrls.writeRowHits 34592
+system.mem_ctrls.readRowHitRate 59.25
+system.mem_ctrls.writeRowHitRate 88.26
+system.mem_ctrls.avgGap 33.92
+system.mem_ctrls.pageHitRate 74.08
+system.mem_ctrls_0.actEnergy 73070760
+system.mem_ctrls_0.preEnergy 39532584
+system.mem_ctrls_0.readEnergy 245010528
+system.mem_ctrls_0.writeEnergy 186934464
+system.mem_ctrls_0.refreshEnergy 396442800.000000
+system.mem_ctrls_0.actBackEnergy 606409320
+system.mem_ctrls_0.preBackEnergy 10673664
+system.mem_ctrls_0.actPowerDownEnergy 1616441112
+system.mem_ctrls_0.prePowerDownEnergy 34766592
+system.mem_ctrls_0.selfRefreshEnergy 32456160
+system.mem_ctrls_0.totalEnergy 3241737984
+system.mem_ctrls_0.averagePower 633.555966
+system.mem_ctrls_0.totalIdleTime 3758823
+system.mem_ctrls_0.memoryStateTime::IDLE 4588
+system.mem_ctrls_0.memoryStateTime::REF 167730
+system.mem_ctrls_0.memoryStateTime::SREF 123729
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 90538
+system.mem_ctrls_0.memoryStateTime::ACT 1185323
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 3544827
+system.mem_ctrls_1.actEnergy 68729640
+system.mem_ctrls_1.preEnergy 37183272
+system.mem_ctrls_1.readEnergy 183320928
+system.mem_ctrls_1.writeEnergy 140238432
+system.mem_ctrls_1.refreshEnergy 405662400.000000
+system.mem_ctrls_1.actBackEnergy 592863384
+system.mem_ctrls_1.preBackEnergy 9519360
+system.mem_ctrls_1.actPowerDownEnergy 1630196352
+system.mem_ctrls_1.prePowerDownEnergy 75447936
+system.mem_ctrls_1.selfRefreshEnergy 8193840
+system.mem_ctrls_1.totalEnergy 3151355544
+system.mem_ctrls_1.averagePower 615.891881
+system.mem_ctrls_1.totalIdleTime 3791773
+system.mem_ctrls_1.memoryStateTime::IDLE 5752
+system.mem_ctrls_1.memoryStateTime::REF 171636
+system.mem_ctrls_1.memoryStateTime::SREF 20335
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 196479
+system.mem_ctrls_1.memoryStateTime::ACT 1147541
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 3574992
+system.pwrStateResidencyTicks::UNDEFINED 5116735
+system.cpu.clk_domain.clock 1
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 182
+system.cpu.pwrStateResidencyTicks::ON 5116735
+system.cpu.numCycles 5116735
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 267015
+system.cpu.committedOps 267785
+system.cpu.num_int_alu_accesses 266368
+system.cpu.num_fp_alu_accesses 12
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 15688
+system.cpu.num_conditional_control_insts 41235
+system.cpu.num_int_insts 266368
+system.cpu.num_fp_insts 12
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 334582
+system.cpu.num_int_register_writes 178375
+system.cpu.num_fp_register_reads 12
+system.cpu.num_fp_register_writes 0
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 109347
+system.cpu.num_load_insts 67812
+system.cpu.num_store_insts 41535
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 5116735
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 56923
+system.cpu.op_class::No_OpClass 191 0.07% 0.07%
+system.cpu.op_class::IntAlu 157759 58.87% 58.94%
+system.cpu.op_class::IntMult 436 0.16% 59.11%
+system.cpu.op_class::IntDiv 234 0.09% 59.19%
+system.cpu.op_class::FloatAdd 0 0.00% 59.19%
+system.cpu.op_class::FloatCmp 0 0.00% 59.19%
+system.cpu.op_class::FloatCvt 0 0.00% 59.19%
+system.cpu.op_class::FloatMult 0 0.00% 59.19%
+system.cpu.op_class::FloatMultAcc 0 0.00% 59.19%
+system.cpu.op_class::FloatDiv 0 0.00% 59.19%
+system.cpu.op_class::FloatMisc 0 0.00% 59.19%
+system.cpu.op_class::FloatSqrt 0 0.00% 59.19%
+system.cpu.op_class::SimdAdd 0 0.00% 59.19%
+system.cpu.op_class::SimdAddAcc 0 0.00% 59.19%
+system.cpu.op_class::SimdAlu 0 0.00% 59.19%
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+system.ruby.Load_Linked.latency_hist_seqr | 774 99.36% 99.36% | 0 0.00% 99.36% | 0 0.00% 99.36% | 0 0.00% 99.36% | 2 0.26% 99.61% | 0 0.00% 99.61% | 0 0.00% 99.61% | 0 0.00% 99.61% | 3 0.39% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.latency_hist_seqr::total 779
+system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Load_Linked.hit_latency_hist_seqr::samples 774
+system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1
+system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1
+system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 774 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.hit_latency_hist_seqr::total 774
+system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 8
+system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 79
+system.ruby.Load_Linked.miss_latency_hist_seqr::samples 5
+system.ruby.Load_Linked.miss_latency_hist_seqr::mean 53
+system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 49.854558
+system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 19.170290
+system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.miss_latency_hist_seqr::total 5
+system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.latency_hist_seqr::samples 779
+system.ruby.Store_Conditional.latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 779 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.latency_hist_seqr::total 779
+system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 779
+system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 779 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.hit_latency_hist_seqr::total 779
+system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
+system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 75421
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.717479
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.204627
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.705830
+system.ruby.Directory.miss_mach_latency_hist_seqr | 39088 51.83% 51.83% | 33767 44.77% 96.60% | 1655 2.19% 98.79% | 362 0.48% 99.27% | 284 0.38% 99.65% | 231 0.31% 99.95% | 22 0.03% 99.98% | 2 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 75421
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 34494
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 54.026642
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.971041
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 36.132660
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 20557 59.60% 59.60% | 12917 37.45% 97.04% | 658 1.91% 98.95% | 143 0.41% 99.37% | 114 0.33% 99.70% | 91 0.26% 99.96% | 12 0.03% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 34494
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 13381
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.404305
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 40.813638
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.306980
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10097 75.46% 75.46% | 3033 22.67% 98.12% | 165 1.23% 99.36% | 31 0.23% 99.59% | 21 0.16% 99.75% | 26 0.19% 99.94% | 2 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 6 0.04% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 13381
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 27541
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 67.837551
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 60.346853
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 39.212462
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 8432 30.62% 30.62% | 17814 64.68% 95.30% | 832 3.02% 98.32% | 188 0.68% 99.00% | 149 0.54% 99.54% | 114 0.41% 99.96% | 8 0.03% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 27541
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 5
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 53
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 49.854558
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 19.170290
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 5
+system.ruby.Directory_Controller.GETX 75421 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 75417 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 75421 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 75417 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 75421 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 75417 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 75421 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 75417 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 67033 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 310176 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 42314 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 75421 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 75417 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 75417 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 34494 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 27541 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 13386 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 32539 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 282635 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 28928 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 75417 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 75417 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 62035 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 13386 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
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+exit_on_work_items=false
+init_param=0
+kernel=
+kernel_addr_check=true
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+load_offset=0
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+memories=system.physmem
+mmap_using_noreserve=false
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+num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+readfile=
+symbolfile=
+thermal_components=
+thermal_model=Null
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+default_p_state=UNDEFINED
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+eventq_index=0
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+profile=0
+progress_interval=0
+simpoint_start_insts=
+socket_id=0
+switched_out=false
+syscallRetryLatency=10000
+system=system
+tracer=system.cpu.tracer
+wait_for_remote_gdb=false
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=262144
+system=system
+tag_latency=2
+tags=system.cpu.dcache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.slave[1]
+
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=262144
+tag_latency=2
+
+[system.cpu.dtb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.icache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=2
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=2
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=true
+max_miss_count=0
+mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=131072
+system=system
+tag_latency=2
+tags=system.cpu.icache.tags
+tgts_per_mshr=20
+write_buffers=8
+writeback_clean=true
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.slave[0]
+
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=2
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=131072
+tag_latency=2
+
+[system.cpu.interrupts]
+type=RiscvInterrupts
+eventq_index=0
+
+[system.cpu.isa]
+type=RiscvISA
+eventq_index=0
+
+[system.cpu.itb]
+type=RiscvTLB
+eventq_index=0
+size=64
+
+[system.cpu.l2cache]
+type=Cache
+children=tags
+addr_ranges=0:18446744073709551615:0:0:0:0
+assoc=8
+clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+data_latency=20
+default_p_state=UNDEFINED
+demand_mshr_reserve=1
+eventq_index=0
+is_read_only=false
+max_miss_count=0
+mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=2097152
+system=system
+tag_latency=20
+tags=system.cpu.l2cache.tags
+tgts_per_mshr=12
+write_buffers=8
+writeback_clean=false
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+data_latency=20
+default_p_state=UNDEFINED
+eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+sequential_access=false
+size=2097152
+tag_latency=20
+
+[system.cpu.toL2Bus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=0
+frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
+response_latency=1
+snoop_filter=system.cpu.toL2Bus.snoop_filter
+snoop_response_latency=1
+system=system
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
+[system.cpu.tracer]
+type=ExeTracer
+eventq_index=0
+
+[system.cpu.workload]
+type=Process
+cmd=insttest
+cwd=
+drivers=
+egid=100
+env=
+errout=cerr
+euid=100
+eventq_index=0
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest
+gid=100
+input=cin
+kvmInSE=false
+maxStackSize=67108864
+output=cout
+pgid=100
+pid=100
+ppid=0
+simpoint=0
+system=system
+uid=100
+useArchPT=false
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+domain_id=-1
+eventq_index=0
+init_perf_level=0
+voltage_domain=system.voltage_domain
+
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
+[system.membus]
+type=CoherentXBar
+children=snoop_filter
+clk_domain=system.clk_domain
+default_p_state=UNDEFINED
+eventq_index=0
+forward_latency=4
+frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
+response_latency=2
+snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.system_port system.cpu.l2cache.mem_side
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+default_p_state=UNDEFINED
+eventq_index=0
+in_addr_map=true
+kvm_map=true
+latency=30000
+latency_var=0
+null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
+range=0:134217727:0:0:0:0
+port=system.membus.master[0]
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
--- /dev/null
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "kernel": "",
+ "mmap_using_noreserve": false,
+ "kernel_addr_check": true,
+ "membus": {
+ "point_of_coherency": true,
+ "system": "system",
+ "response_latency": 2,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 4,
+ "clk_domain": "system.clk_domain",
+ "width": 16,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 3,
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.l2cache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.membus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 1
+ },
+ "power_model": null,
+ "path": "system.membus",
+ "snoop_response_latency": 4,
+ "name": "membus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "symbolfile": "",
+ "readfile": "",
+ "thermal_model": null,
+ "cxx_class": "System",
+ "work_begin_cpu_id_exit": -1,
+ "load_offset": 0,
+ "work_begin_exit_count": 0,
+ "p_state_clk_gate_min": 1000,
+ "memories": [
+ "system.physmem"
+ ],
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": [
+ 1000
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "mem_ranges": [],
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "dvfs_handler": {
+ "enable": false,
+ "name": "dvfs_handler",
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
+ "eventq_index": 0,
+ "cxx_class": "DVFSHandler",
+ "domains": [],
+ "path": "system.dvfs_handler",
+ "type": "DVFSHandler"
+ },
+ "work_end_exit_count": 0,
+ "type": "System",
+ "voltage_domain": {
+ "name": "voltage_domain",
+ "eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "boot_osflags": "a",
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "physmem": {
+ "range": "0:134217727:0:0:0:0",
+ "latency": 30000,
+ "name": "physmem",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "kvm_map": true,
+ "clk_domain": "system.clk_domain",
+ "power_model": null,
+ "latency_var": 0,
+ "bandwidth": "73.000000",
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.physmem",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "power_model": null,
+ "work_cpus_ckpt_count": 0,
+ "thermal_components": [],
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
+ "init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain",
+ "domain_id": -1
+ },
+ "work_end_ckpt_count": 0,
+ "mem_mode": "timing",
+ "name": "system",
+ "init_param": 0,
+ "p_state_clk_gate_bins": 20,
+ "load_addr_mask": 1099511627775,
+ "cpu": [
+ {
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "system": "system",
+ "icache": {
+ "cpu_side": {
+ "peer": "system.cpu.icache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 131072,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": true,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 131072,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.icache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": true,
+ "prefetch_on_access": false,
+ "path": "system.cpu.icache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "icache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "TimingSimpleCPU",
+ "max_loads_all_threads": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "checker": null,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "toL2Bus": {
+ "point_of_coherency": false,
+ "system": "system",
+ "response_latency": 1,
+ "cxx_class": "CoherentXBar",
+ "forward_latency": 0,
+ "clk_domain": "system.cpu_clk_domain",
+ "width": 32,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "master": {
+ "peer": [
+ "system.cpu.l2cache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "type": "CoherentXBar",
+ "frontend_latency": 1,
+ "slave": {
+ "peer": [
+ "system.cpu.icache.mem_side",
+ "system.cpu.dcache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "p_state_clk_gate_min": 1000,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
+ "power_model": null,
+ "path": "system.cpu.toL2Bus",
+ "snoop_response_latency": 1,
+ "name": "toL2Bus",
+ "p_state_clk_gate_bins": 20,
+ "use_default_range": false
+ },
+ "do_quiesce": true,
+ "type": "TimingSimpleCPU",
+ "profile": 0,
+ "icache_port": {
+ "peer": "system.cpu.icache.cpu_side",
+ "role": "MASTER"
+ },
+ "p_state_clk_gate_bins": 20,
+ "p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "RiscvInterrupts",
+ "name": "interrupts",
+ "cxx_class": "RiscvISA::Interrupts"
+ }
+ ],
+ "dcache_port": {
+ "peer": "system.cpu.dcache.cpu_side",
+ "role": "MASTER"
+ },
+ "socket_id": 0,
+ "power_model": null,
+ "max_insts_all_threads": 0,
+ "l2cache": {
+ "cpu_side": {
+ "peer": "system.cpu.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "Cache",
+ "size": 2097152,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 2097152,
+ "tag_latency": 20,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.l2cache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 20
+ },
+ "tgts_per_mshr": 12,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.l2cache",
+ "data_latency": 20,
+ "tag_latency": 20,
+ "name": "l2cache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 8
+ },
+ "path": "system.cpu",
+ "max_loads_any_thread": 0,
+ "switched_out": false,
+ "workload": [
+ {
+ "uid": 100,
+ "pid": 100,
+ "kvmInSE": false,
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest",
+ "drivers": [],
+ "system": "system",
+ "gid": 100,
+ "eventq_index": 0,
+ "env": [],
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
+ "cwd": "",
+ "pgid": 100,
+ "simpoint": 0,
+ "euid": 100,
+ "input": "cin",
+ "path": "system.cpu.workload",
+ "name": "workload",
+ "cmd": [
+ "insttest"
+ ],
+ "errout": "cerr",
+ "useArchPT": false,
+ "egid": 100,
+ "output": "cout"
+ }
+ ],
+ "name": "cpu",
+ "wait_for_remote_gdb": false,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "RiscvISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "RiscvTLB",
+ "size": 64
+ },
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "dcache": {
+ "cpu_side": {
+ "peer": "system.cpu.dcache_port",
+ "role": "SLAVE"
+ },
+ "clusivity": "mostly_incl",
+ "prefetcher": null,
+ "system": "system",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "Cache",
+ "size": 262144,
+ "type": "Cache",
+ "clk_domain": "system.cpu_clk_domain",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "default_p_state": "UNDEFINED",
+ "p_state_clk_gate_max": 1000000000000,
+ "mem_side": {
+ "peer": "system.cpu.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "writeback_clean": false,
+ "p_state_clk_gate_min": 1000,
+ "tags": {
+ "size": 262144,
+ "tag_latency": 2,
+ "name": "tags",
+ "p_state_clk_gate_min": 1000,
+ "eventq_index": 0,
+ "p_state_clk_gate_bins": 20,
+ "default_p_state": "UNDEFINED",
+ "clk_domain": "system.cpu_clk_domain",
+ "power_model": null,
+ "sequential_access": false,
+ "assoc": 2,
+ "cxx_class": "LRU",
+ "p_state_clk_gate_max": 1000000000000,
+ "path": "system.cpu.dcache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "data_latency": 2
+ },
+ "tgts_per_mshr": 20,
+ "demand_mshr_reserve": 1,
+ "power_model": null,
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
+ "is_read_only": false,
+ "prefetch_on_access": false,
+ "path": "system.cpu.dcache",
+ "data_latency": 2,
+ "tag_latency": 2,
+ "name": "dcache",
+ "p_state_clk_gate_bins": 20,
+ "sequential_access": false,
+ "assoc": 2
+ },
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "RiscvISA",
+ "name": "isa",
+ "cxx_class": "RiscvISA::ISA"
+ }
+ ],
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ }
+ ],
+ "multi_thread": false,
+ "exit_on_work_items": false,
+ "work_item_id": -1,
+ "num_work_ids": 16
+ },
+ "time_sync_period": 100000000000,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 100000000,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest'
+info: Increasing stack size by one page.
--- /dev/null
+Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simout
+Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:12:18
+gem5 executing on boldrock, pid 2089
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing
+
+Global frequency set at 1000000000000 ticks per second
+lui: PASS
+lui, negative: PASS
+auipc: 0x184D6
+auipc: PASS
+jal: PASS
+jalr: PASS
+beq, equal: PASS
+beq, not equal: PASS
+bne, equal: PASS
+bne, not equal: PASS
+blt, less: PASS
+blt, equal: PASS
+blt, greater: PASS
+bge, less: PASS
+bge, equal: PASS
+bge, greater: PASS
+bltu, greater: PASS
+bltu, equal: PASS
+bltu, less: PASS
+bgeu, greater: PASS
+bgeu, equal: PASS
+bgeu, less: PASS
+lb, positive: PASS
+lb, negative: PASS
+lh, positive: PASS
+lh, negative: PASS
+lw, positive: PASS
+lw, negative: PASS
+lbu: PASS
+lhu: PASS
+sb: PASS
+sh: PASS
+sw: PASS
+addi: PASS
+addi, overflow: PASS
+slti, true: PASS
+slti, false: PASS
+sltiu, false: PASS
+sltiu, true: PASS
+xori (1): PASS
+xori (0): PASS
+ori (1): PASS
+ori (A): PASS
+andi (0): PASS
+andi (1): PASS
+slli, general: PASS
+slli, erase: PASS
+srli, general: PASS
+srli, erase: PASS
+srli, negative: PASS
+srai, general: PASS
+srai, erase: PASS
+srai, negative: PASS
+add: PASS
+add, overflow: PASS
+sub: PASS
+sub, "overflow": PASS
+sll, general: PASS
+sll, erase: PASS
+slt, true: PASS
+slt, false: PASS
+sltu, false: PASS
+sltu, true: PASS
+xor (1): PASS
+xor (0): PASS
+srl, general: PASS
+srl, erase: PASS
+srl, negative: PASS
+sra, general: PASS
+sra, erase: PASS
+sra, negative: PASS
+or (1): PASS
+or (A): PASS
+and (0): PASS
+and (-1): PASS
+Bytes written: 15
+open, write: PASS
+access F_OK: PASS
+access R_OK: PASS
+access W_OK: PASS
+access X_OK: PASS
+stat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+fstat:
+ st_dev = 2430
+ st_ino = 73671954
+ st_mode = 33188
+ st_nlink = 1
+ st_uid = 1001
+ st_gid = 1001
+ st_rdev = 0
+ st_size = 15
+ st_blksize = 8192
+ st_blocks = 8
+open, stat: PASS
+Bytes read: 15
+String read: this is a test
+open, read, unlink: PASS
+times:
+ tms_utime = 0
+ tms_stime = 0
+ tms_cutime = 0
+ tms_cstime = 0
+times: \e[1;31mFAIL\e[0m (expected 1; found 0)
+timeval:
+ tv_sec = 1000000000
+ tv_usec = 400
+gettimeofday: PASS
+Cycles: 818147
+rdcycle: PASS
+Time: 1499980395
+rdtime: PASS
+Instructions Retired: 214447
+rdinstret: PASS
+lwu: PASS
+ld: PASS
+sd: PASS
+addiw: PASS
+addiw, overflow: PASS
+addiw, truncate: PASS
+slliw, general: PASS
+slliw, erase: PASS
+slliw, truncate: PASS
+srliw, general: PASS
+srliw, erase: PASS
+srliw, negative: PASS
+srliw, truncate: PASS
+sraiw, general: PASS
+sraiw, erase: PASS
+sraiw, negative: PASS
+sraiw, truncate: PASS
+addw: PASS
+addw, overflow: PASS
+addw, truncate: PASS
+subw: PASS
+subw, "overflow": PASS
+subw, truncate: PASS
+sllw, general: PASS
+sllw, erase: PASS
+sllw, truncate: PASS
+srlw, general: PASS
+srlw, erase: PASS
+srlw, negative: PASS
+srlw, truncate: PASS
+sraw, general: PASS
+sraw, erase: PASS
+sraw, negative: PASS
+sraw, truncate: PASS
+Exiting @ tick 508585500 because exiting with last active thread context
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000509
+sim_ticks 508585500
+final_tick 508585500
+sim_freq 1000000000000
+host_inst_rate 3721
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+system.cpu.l2cache.ReadCleanReq_accesses::total 955
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 259
+system.cpu.l2cache.ReadSharedReq_accesses::total 259
+system.cpu.l2cache.demand_accesses::cpu.inst 955
+system.cpu.l2cache.demand_accesses::cpu.data 484
+system.cpu.l2cache.demand_accesses::total 1439
+system.cpu.l2cache.overall_accesses::cpu.inst 955
+system.cpu.l2cache.overall_accesses::cpu.data 484
+system.cpu.l2cache.overall_accesses::total 1439
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
+system.cpu.l2cache.ReadExReq_miss_rate::total 1
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997906
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997906
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 1
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997906
+system.cpu.l2cache.demand_miss_rate::cpu.data 1
+system.cpu.l2cache.demand_miss_rate::total 0.998610
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997906
+system.cpu.l2cache.overall_miss_rate::cpu.data 1
+system.cpu.l2cache.overall_miss_rate::total 0.998610
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.524659
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.524659
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.524659
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.demand_avg_miss_latency::total 60500.347947
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.524659
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
+system.cpu.l2cache.overall_avg_miss_latency::total 60500.347947
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 225
+system.cpu.l2cache.ReadExReq_mshr_misses::total 225
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 259
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 259
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 953
+system.cpu.l2cache.demand_mshr_misses::cpu.data 484
+system.cpu.l2cache.demand_mshr_misses::total 1437
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 953
+system.cpu.l2cache.overall_mshr_misses::cpu.data 484
+system.cpu.l2cache.overall_mshr_misses::total 1437
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11362500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11362500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48127000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48127000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13079500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13079500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48127000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24442000
+system.cpu.l2cache.demand_mshr_miss_latency::total 72569000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48127000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24442000
+system.cpu.l2cache.overall_mshr_miss_latency::total 72569000
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997906
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997906
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
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+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.524659
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.524659
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.347947
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.347947
+system.cpu.toL2Bus.snoop_filter.tot_requests 1483
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 44
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508585500
+system.cpu.toL2Bus.trans_dist::ReadResp 1214
+system.cpu.toL2Bus.trans_dist::WritebackClean 44
+system.cpu.toL2Bus.trans_dist::ReadExReq 225
+system.cpu.toL2Bus.trans_dist::ReadExResp 225
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 955
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 259
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1954
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 968
+system.cpu.toL2Bus.pkt_count::total 2922
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63936
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30976
+system.cpu.toL2Bus.pkt_size::total 94912
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1439
+system.cpu.toL2Bus.snoop_fanout::mean 0
+system.cpu.toL2Bus.snoop_fanout::stdev 0
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1439 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 0
+system.cpu.toL2Bus.snoop_fanout::total 1439
+system.cpu.toL2Bus.reqLayer0.occupancy 785500
+system.cpu.toL2Bus.reqLayer0.utilization 0.2
+system.cpu.toL2Bus.respLayer0.occupancy 1432500
+system.cpu.toL2Bus.respLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer1.occupancy 726000
+system.cpu.toL2Bus.respLayer1.utilization 0.1
+system.membus.snoop_filter.tot_requests 1437
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 508585500
+system.membus.trans_dist::ReadResp 1212
+system.membus.trans_dist::ReadExReq 225
+system.membus.trans_dist::ReadExResp 225
+system.membus.trans_dist::ReadSharedReq 1212
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2874
+system.membus.pkt_count::total 2874
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 91968
+system.membus.pkt_size::total 91968
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1437
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1437 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1437
+system.membus.reqLayer0.occupancy 1437500
+system.membus.reqLayer0.utilization 0.3
+system.membus.respLayer1.occupancy 7185000
+system.membus.respLayer1.utilization 1.4
+
+---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
threadPolicy=RoundRobin
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"max_loads_all_threads": 0,
"executeMemoryIssueLimit": 1,
"decodeCycleInput": true,
+ "syscallRetryLatency": 10000,
"max_loads_any_thread": 0,
"executeLSQTransfersQueueSize": 2,
"p_state_clk_gate_max": 1000000000000,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:44
-gem5 executing on zizzer, pid 34094
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:12:00
+gem5 executing on boldrock, pid 2002
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
mul: PASS
mul, overflow: PASS
mulh: PASS
remuw/0: PASS
remuw, "overflow": PASS
remuw, sign extend: PASS
-Exiting @ tick 165091500 because target called exit()
+Exiting @ tick 177558500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000165 # Number of seconds simulated
-sim_ticks 165091500 # Number of ticks simulated
-final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 261359 # Simulator instruction rate (inst/s)
-host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 380682439 # Simulator tick rate (ticks/s)
-host_mem_usage 261856 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
-sim_insts 113337 # Number of instructions simulated
-sim_ops 113337 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory
-system.physmem.bytes_read::total 66752 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1043 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 93 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5 # Per bank write bursts
-system.physmem.perBankRdBursts::2 17 # Per bank write bursts
-system.physmem.perBankRdBursts::3 108 # Per bank write bursts
-system.physmem.perBankRdBursts::4 59 # Per bank write bursts
-system.physmem.perBankRdBursts::5 95 # Per bank write bursts
-system.physmem.perBankRdBursts::6 66 # Per bank write bursts
-system.physmem.perBankRdBursts::7 26 # Per bank write bursts
-system.physmem.perBankRdBursts::8 58 # Per bank write bursts
-system.physmem.perBankRdBursts::9 78 # Per bank write bursts
-system.physmem.perBankRdBursts::10 82 # Per bank write bursts
-system.physmem.perBankRdBursts::11 51 # Per bank write bursts
-system.physmem.perBankRdBursts::12 133 # Per bank write bursts
-system.physmem.perBankRdBursts::13 67 # Per bank write bursts
-system.physmem.perBankRdBursts::14 98 # Per bank write bursts
-system.physmem.perBankRdBursts::15 7 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 164764000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1043 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation
-system.physmem.totQLat 16727250 # Total ticks spent queuing
-system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.16 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 829 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 157971.24 # Average gap between requests
-system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
-system.physmem_0.averagePower 555.750261 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states
-system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
-system.physmem_1.averagePower 547.351788 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 31695 # Number of BP lookups
-system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 15330 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 45 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 330183 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113337 # Number of instructions committed
-system.cpu.committedOps 113337 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 2.913285 # CPI: cycles per instruction
-system.cpu.ipc 0.343255 # IPC: instructions per cycle
-system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction
-system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction
-system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction
-system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction
-system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction
-system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.op_class_0::total 113337 # Class of committed instruction
-system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
-system.cpu.dcache.overall_hits::total 43871 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses
-system.cpu.dcache.overall_misses::total 453 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 845 # Transaction distribution
-system.membus.trans_dist::ReadExReq 198 # Transaction distribution
-system.membus.trans_dist::ReadExResp 198 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1043 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1043 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
+sim_seconds 0.000178
+sim_ticks 177558500
+final_tick 177558500
+sim_freq 1000000000000
+host_inst_rate 5771
+host_op_rate 5782
+host_tick_rate 9526846
+host_mem_usage 272764
+host_seconds 18.64
+sim_insts 107550
+sim_ops 107762
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 177558500
+system.physmem.bytes_read::cpu.inst 60544
+system.physmem.bytes_read::cpu.data 29504
+system.physmem.bytes_read::total 90048
+system.physmem.bytes_inst_read::cpu.inst 60544
+system.physmem.bytes_inst_read::total 60544
+system.physmem.num_reads::cpu.inst 946
+system.physmem.num_reads::cpu.data 461
+system.physmem.num_reads::total 1407
+system.physmem.bw_read::cpu.inst 340980578
+system.physmem.bw_read::cpu.data 166164954
+system.physmem.bw_read::total 507145532
+system.physmem.bw_inst_read::cpu.inst 340980578
+system.physmem.bw_inst_read::total 340980578
+system.physmem.bw_total::cpu.inst 340980578
+system.physmem.bw_total::cpu.data 166164954
+system.physmem.bw_total::total 507145532
+system.physmem.readReqs 1407
+system.physmem.writeReqs 0
+system.physmem.readBursts 1407
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 90048
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 90048
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 165
+system.physmem.perBankRdBursts::1 82
+system.physmem.perBankRdBursts::2 125
+system.physmem.perBankRdBursts::3 86
+system.physmem.perBankRdBursts::4 28
+system.physmem.perBankRdBursts::5 90
+system.physmem.perBankRdBursts::6 29
+system.physmem.perBankRdBursts::7 35
+system.physmem.perBankRdBursts::8 84
+system.physmem.perBankRdBursts::9 137
+system.physmem.perBankRdBursts::10 194
+system.physmem.perBankRdBursts::11 146
+system.physmem.perBankRdBursts::12 52
+system.physmem.perBankRdBursts::13 53
+system.physmem.perBankRdBursts::14 55
+system.physmem.perBankRdBursts::15 46
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
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+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 177461500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1407
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+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 1197
+system.physmem.rdQLenPdf::1 197
+system.physmem.rdQLenPdf::2 13
+system.physmem.rdQLenPdf::3 0
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+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 273
+system.physmem.bytesPerActivate::mean 322.578755
+system.physmem.bytesPerActivate::gmean 213.541597
+system.physmem.bytesPerActivate::stdev 289.786791
+system.physmem.bytesPerActivate::0-127 76 27.84% 27.84%
+system.physmem.bytesPerActivate::128-255 60 21.98% 49.82%
+system.physmem.bytesPerActivate::256-383 48 17.58% 67.40%
+system.physmem.bytesPerActivate::384-511 26 9.52% 76.92%
+system.physmem.bytesPerActivate::512-639 16 5.86% 82.78%
+system.physmem.bytesPerActivate::640-767 15 5.49% 88.28%
+system.physmem.bytesPerActivate::768-895 7 2.56% 90.84%
+system.physmem.bytesPerActivate::896-1023 7 2.56% 93.41%
+system.physmem.bytesPerActivate::1024-1151 18 6.59% 100.00%
+system.physmem.bytesPerActivate::total 273
+system.physmem.totQLat 18087250
+system.physmem.totMemAccLat 44468500
+system.physmem.totBusLat 7035000
+system.physmem.avgQLat 12855.19
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 31605.19
+system.physmem.avgRdBW 507.15
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 507.15
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 3.96
+system.physmem.busUtilRead 3.96
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.13
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1122
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 79.74
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 126127.58
+system.physmem.pageHitRate 79.74
+system.physmem_0.actEnergy 821100
+system.physmem_0.preEnergy 413655
+system.physmem_0.readEnergy 4569600
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 13522080.000000
+system.physmem_0.actBackEnergy 11049450
+system.physmem_0.preBackEnergy 315840
+system.physmem_0.actPowerDownEnergy 64094790
+system.physmem_0.prePowerDownEnergy 4587360
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 99373875
+system.physmem_0.averagePower 559.667575
+system.physmem_0.totalIdleTime 152474000
+system.physmem_0.memoryStateTime::IDLE 144000
+system.physmem_0.memoryStateTime::REF 5720000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 11945000
+system.physmem_0.memoryStateTime::ACT 19174000
+system.physmem_0.memoryStateTime::ACT_PDN 140575500
+system.physmem_1.actEnergy 1213800
+system.physmem_1.preEnergy 622380
+system.physmem_1.readEnergy 5476380
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 13522080.000000
+system.physmem_1.actBackEnergy 12400350
+system.physmem_1.preBackEnergy 386400
+system.physmem_1.actPowerDownEnergy 59656770
+system.physmem_1.prePowerDownEnergy 7116480
+system.physmem_1.selfRefreshEnergy 0
+system.physmem_1.totalEnergy 100394640
+system.physmem_1.averagePower 565.416461
+system.physmem_1.totalIdleTime 149184750
+system.physmem_1.memoryStateTime::IDLE 398000
+system.physmem_1.memoryStateTime::REF 5720000
+system.physmem_1.memoryStateTime::SREF 0
+system.physmem_1.memoryStateTime::PRE_PDN 18527500
+system.physmem_1.memoryStateTime::ACT 22078000
+system.physmem_1.memoryStateTime::ACT_PDN 130835000
+system.pwrStateResidencyTicks::UNDEFINED 177558500
+system.cpu.branchPred.lookups 32035
+system.cpu.branchPred.condPredicted 21823
+system.cpu.branchPred.condIncorrect 2767
+system.cpu.branchPred.BTBLookups 24464
+system.cpu.branchPred.BTBHits 11324
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 46.288424
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 6634
+system.cpu.branchPred.indirectHits 3359
+system.cpu.branchPred.indirectMisses 3275
+system.cpu.branchPredindirectMispredicted 1300
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 45
+system.cpu.pwrStateResidencyTicks::ON 177558500
+system.cpu.numCycles 355117
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 107550
+system.cpu.committedOps 107762
+system.cpu.discardedOps 7803
+system.cpu.numFetchSuspends 0
+system.cpu.cpi 3.301878
+system.cpu.ipc 0.302858
+system.cpu.op_class_0::No_OpClass 49 0.05% 0.05%
+system.cpu.op_class_0::IntAlu 65954 61.20% 61.25%
+system.cpu.op_class_0::IntMult 124 0.12% 61.36%
+system.cpu.op_class_0::IntDiv 30 0.03% 61.39%
+system.cpu.op_class_0::FloatAdd 0 0.00% 61.39%
+system.cpu.op_class_0::FloatCmp 0 0.00% 61.39%
+system.cpu.op_class_0::FloatCvt 0 0.00% 61.39%
+system.cpu.op_class_0::FloatMult 0 0.00% 61.39%
+system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.39%
+system.cpu.op_class_0::FloatDiv 0 0.00% 61.39%
+system.cpu.op_class_0::FloatMisc 0 0.00% 61.39%
+system.cpu.op_class_0::FloatSqrt 0 0.00% 61.39%
+system.cpu.op_class_0::SimdAdd 0 0.00% 61.39%
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.39%
+system.cpu.op_class_0::SimdAlu 0 0.00% 61.39%
+system.cpu.op_class_0::SimdCmp 0 0.00% 61.39%
+system.cpu.op_class_0::SimdCvt 0 0.00% 61.39%
+system.cpu.op_class_0::SimdMisc 0 0.00% 61.39%
+system.cpu.op_class_0::SimdMult 0 0.00% 61.39%
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.39%
+system.cpu.op_class_0::SimdShift 0 0.00% 61.39%
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.39%
+system.cpu.op_class_0::SimdSqrt 0 0.00% 61.39%
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.39%
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15870000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68512500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68512500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17793500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17793500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68512500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 33663500
+system.cpu.l2cache.demand_mshr_miss_latency::total 102176000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68512500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 33663500
+system.cpu.l2cache.overall_mshr_miss_latency::total 102176000
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994748
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994748
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.995833
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.995833
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994748
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.997835
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.995757
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994748
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.997835
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.995757
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71486.486486
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71486.486486
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72346.884900
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72346.884900
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74449.790795
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74449.790795
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72346.884900
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73022.776573
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72568.181818
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72346.884900
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73022.776573
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72568.181818
+system.cpu.toL2Bus.snoop_filter.tot_requests 1487
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 74
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 177558500
+system.cpu.toL2Bus.trans_dist::ReadResp 1191
+system.cpu.toL2Bus.trans_dist::WritebackClean 73
+system.cpu.toL2Bus.trans_dist::ReadExReq 222
+system.cpu.toL2Bus.trans_dist::ReadExResp 222
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 952
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 240
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1976
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 924
+system.cpu.toL2Bus.pkt_count::total 2900
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65536
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29568
+system.cpu.toL2Bus.pkt_size::total 95104
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1414
+system.cpu.toL2Bus.snoop_fanout::mean 0.000707
+system.cpu.toL2Bus.snoop_fanout::stdev 0.026593
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1413 99.93% 99.93%
+system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 1414
+system.cpu.toL2Bus.reqLayer0.occupancy 816500
+system.cpu.toL2Bus.reqLayer0.utilization 0.5
+system.cpu.toL2Bus.respLayer0.occupancy 1426500
+system.cpu.toL2Bus.respLayer0.utilization 0.8
+system.cpu.toL2Bus.respLayer1.occupancy 693000
+system.cpu.toL2Bus.respLayer1.utilization 0.4
+system.membus.snoop_filter.tot_requests 1407
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 177558500
+system.membus.trans_dist::ReadResp 1185
+system.membus.trans_dist::ReadExReq 222
+system.membus.trans_dist::ReadExResp 222
+system.membus.trans_dist::ReadSharedReq 1185
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2814
+system.membus.pkt_count::total 2814
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 90048
+system.membus.pkt_size::total 90048
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1407
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1407 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1407
+system.membus.reqLayer0.occupancy 1632000
+system.membus.reqLayer0.utilization 0.9
+system.membus.respLayer1.occupancy 7488500
+system.membus.respLayer1.utilization 4.2
---------- End Simulation Statistics ----------
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
+numPhysVecRegs=256
numROBEntries=192
numRobs=1
numThreads=1
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
+wait_for_remote_gdb=false
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
"decodeToFetchDelay": 1,
"renameWidth": 8,
"numThreads": 1,
+ "syscallRetryLatency": 10000,
"squashWidth": 8,
"function_trace": false,
"backComSize": 5,
"switched_out": false,
"smtLSQPolicy": "Partitioned",
"fetchBufferSize": 64,
+ "wait_for_remote_gdb": false,
+ "cacheStorePorts": 200,
"simpoint_start_insts": [],
"max_insts_any_thread": 0,
"smtROBThreshold": 100,
"issueWidth": 8,
"LSQCheckLoads": true,
"commitToRenameDelay": 1,
- "cachePorts": 200,
"system": "system",
"checker": null,
"numPhysFloatRegs": 256,
"default_p_state": "UNDEFINED",
"type": "DerivO3CPU",
"wbWidth": 8,
+ "numPhysVecRegs": 256,
"interrupts": [
{
"eventq_index": 0,
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:44
-gem5 executing on zizzer, pid 34095
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:11:34
+gem5 executing on boldrock, pid 1866
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
mul: PASS
mul, overflow: PASS
mulh: PASS
remuw/0: PASS
remuw, "overflow": PASS
remuw, sign extend: PASS
-Exiting @ tick 66726000 because target called exit()
+Exiting @ tick 124491500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000067 # Number of seconds simulated
-sim_ticks 66743000 # Number of ticks simulated
-final_tick 66743000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 234636 # Simulator instruction rate (inst/s)
-host_op_rate 234630 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 138224430 # Simulator tick rate (ticks/s)
-host_mem_usage 263644 # Number of bytes of host memory used
-host_seconds 0.48 # Real time elapsed on the host
-sim_insts 113291 # Number of instructions simulated
-sim_ops 113291 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 49408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 66368 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 49408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 49408 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 772 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1037 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 740272388 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 254109045 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 994381433 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 740272388 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 740272388 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 740272388 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 254109045 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 994381433 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1038 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 1038 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 66432 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 66432 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 89 # Per bank write bursts
-system.physmem.perBankRdBursts::1 8 # Per bank write bursts
-system.physmem.perBankRdBursts::2 16 # Per bank write bursts
-system.physmem.perBankRdBursts::3 108 # Per bank write bursts
-system.physmem.perBankRdBursts::4 63 # Per bank write bursts
-system.physmem.perBankRdBursts::5 91 # Per bank write bursts
-system.physmem.perBankRdBursts::6 61 # Per bank write bursts
-system.physmem.perBankRdBursts::7 30 # Per bank write bursts
-system.physmem.perBankRdBursts::8 56 # Per bank write bursts
-system.physmem.perBankRdBursts::9 76 # Per bank write bursts
-system.physmem.perBankRdBursts::10 79 # Per bank write bursts
-system.physmem.perBankRdBursts::11 53 # Per bank write bursts
-system.physmem.perBankRdBursts::12 133 # Per bank write bursts
-system.physmem.perBankRdBursts::13 64 # Per bank write bursts
-system.physmem.perBankRdBursts::14 104 # Per bank write bursts
-system.physmem.perBankRdBursts::15 7 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 66724000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1038 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 579 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 110 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 201 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 318.407960 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 195.437814 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 320.986499 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 66 32.84% 32.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 49 24.38% 57.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 28 13.93% 71.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 5.47% 76.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 11 5.47% 82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 6 2.99% 85.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 1.49% 86.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5 2.49% 89.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 22 10.95% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 201 # Bytes accessed per row activation
-system.physmem.totQLat 13663500 # Total ticks spent queuing
-system.physmem.totMemAccLat 33126000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5190000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13163.29 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31913.29 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 995.34 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 995.34 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.78 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.78 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 824 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.38 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 64281.31 # Average gap between requests
-system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 821100 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 406065 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3327240 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 6538470 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 110400 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 22321770 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 1215840 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 39658005 # Total energy per rank (pJ)
-system.physmem_0.averagePower 594.183051 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 51789750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 53500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 3164000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 12517250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 48928250 # Time in different power states
-system.physmem_1.actEnergy 706860 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 356730 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 6307620 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 140640 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 21247890 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 2284320 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 40045260 # Total energy per rank (pJ)
-system.physmem_1.averagePower 599.985167 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 52550750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 144500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 5948000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 11967750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 46602750 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 40127 # Number of BP lookups
-system.cpu.branchPred.condPredicted 25071 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2677 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 34324 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 19560 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 56.986365 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 7732 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 3910 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 3822 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 1192 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 45 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 133487 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 32821 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 168943 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 40127 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23470 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 44129 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5494 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 22264 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1272 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.102406 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.833567 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 43897 54.63% 54.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3425 4.26% 58.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6099 7.59% 66.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5421 6.75% 73.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2445 3.04% 76.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6593 8.20% 84.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1925 2.40% 86.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1654 2.06% 88.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8898 11.07% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80357 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.300606 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.265614 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33044 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 11875 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 32363 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 936 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2139 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 19097 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 639 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 154927 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 1938 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2139 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34647 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3538 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1406 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 31612 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 7015 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 148450 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 267 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 101534 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 195335 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 195335 # Number of integer rename lookups
-system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 25346 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 57 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 3248 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29003 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22614 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 628 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 137191 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 60 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 131006 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 401 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23957 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13441 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80357 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.630300 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.012996 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 38076 47.38% 47.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10267 12.78% 60.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8067 10.04% 70.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 8077 10.05% 80.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5915 7.36% 87.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4760 5.92% 93.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3768 4.69% 98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1110 1.38% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 317 0.39% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80357 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 179 6.20% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1370 47.45% 53.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 1338 46.35% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 81559 62.26% 62.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.39% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 27992 21.37% 83.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21251 16.22% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 131006 # Type of FU issued
-system.cpu.iq.rate 0.981414 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2887 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022037 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 345657 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 161246 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 125018 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 133848 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2541 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5223 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2902 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2139 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2305 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 218 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 137249 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 965 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29003 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22614 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 58 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1896 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2394 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 126750 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 27173 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4256 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 47912 # number of memory reference insts executed
-system.cpu.iew.exec_branches 29064 # Number of branches executed
-system.cpu.iew.exec_stores 20739 # Number of stores executed
-system.cpu.iew.exec_rate 0.949531 # Inst execution rate
-system.cpu.iew.wb_sent 125653 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 125018 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 49237 # num instructions producing a value
-system.cpu.iew.wb_consumers 72853 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.936556 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.675840 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 23968 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2069 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 75913 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.492379 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.297345 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 42174 55.56% 55.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 10790 14.21% 69.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 5413 7.13% 76.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4064 5.35% 82.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3292 4.34% 86.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 3056 4.03% 90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 2525 3.33% 93.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 907 1.19% 95.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 3692 4.86% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 75913 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113291 # Number of instructions committed
-system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 43492 # Number of memory references committed
-system.cpu.commit.loads 23780 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 25920 # Number of branches committed
-system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 113291 # Number of committed integer instructions.
-system.cpu.commit.function_calls 8529 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 69651 61.48% 61.48% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 122 0.11% 61.59% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 26 0.02% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.61% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 23780 20.99% 82.60% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 19712 17.40% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 113291 # Class of committed instruction
-system.cpu.commit.bw_lim_events 3692 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 208895 # The number of ROB reads
-system.cpu.rob.rob_writes 279024 # The number of ROB writes
-system.cpu.timesIdled 415 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 53130 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 113291 # Number of Instructions Simulated
-system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.178267 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.178267 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.848704 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.848704 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 166268 # number of integer regfile reads
-system.cpu.int_regfile_writes 85929 # number of integer regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 217.985310 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42417 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 160.064151 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 217.985310 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.053219 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.053219 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88517 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88517 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 24171 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 24171 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 42417 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 42417 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42417 # number of overall hits
-system.cpu.dcache.overall_hits::total 42417 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 243 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 243 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1709 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1709 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1709 # number of overall misses
-system.cpu.dcache.overall_misses::total 1709 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 20232000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 20232000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 95961940 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 95961940 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 116193940 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 116193940 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 116193940 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 116193940 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 44126 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 44126 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 44126 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 44126 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009953 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.009953 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.038730 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.038730 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.038730 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.038730 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83259.259259 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 83259.259259 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65458.349250 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65458.349250 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67989.432417 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 67989.432417 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67989.432417 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 173 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1442 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1442 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1442 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1442 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15709000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 15709000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22100500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22100500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22100500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22100500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002867 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002867 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009994 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009994 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006051 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006051 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006051 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91307.142857 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91307.142857 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79741.116751 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79741.116751 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82773.408240 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 82773.408240 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 16 # number of replacements
-system.cpu.icache.tags.tagsinuse 390.093191 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 21217 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 773 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 27.447607 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 390.093191 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.190475 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.190475 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 757 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.369629 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 45285 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 45285 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 21217 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 21217 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 21217 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 21217 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 21217 # number of overall hits
-system.cpu.icache.overall_hits::total 21217 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses
-system.cpu.icache.overall_misses::total 1039 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 81350998 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 81350998 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 81350998 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 81350998 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 81350998 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 81350998 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22256 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 22256 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 22256 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 22256 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 22256 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 22256 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.046684 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.046684 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.046684 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.046684 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78297.399423 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 78297.399423 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 78297.399423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 78297.399423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 78297.399423 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 37 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 67.783784 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 16 # number of writebacks
-system.cpu.icache.writebacks::total 16 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 266 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 266 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 266 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 266 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 773 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 773 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 773 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 773 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65540000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 65540000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65540000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 65540000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65540000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 65540000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.034732 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.034732 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.034732 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84786.545925 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84786.545925 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84786.545925 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 84786.545925 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 612.540827 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 1037 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.015429 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.513827 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 218.027000 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012040 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.006654 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.018693 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 1037 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031647 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 9477 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 9477 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 197 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 197 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 772 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 772 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 70 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 70 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 1039 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses
-system.cpu.l2cache.overall_misses::total 1039 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15413500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 15413500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64376500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 64376500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6288000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 6288000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 64376500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 21701500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 86078000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 64376500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 21701500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 86078000 # number of overall miss cycles
-system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 197 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 197 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 772 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 772 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 70 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 70 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 772 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 267 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1039 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 772 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 267 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1039 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78241.116751 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78241.116751 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83389.248705 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83389.248705 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89828.571429 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89828.571429 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 82846.968239 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83389.248705 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81279.026217 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 82846.968239 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 772 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 772 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 70 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 70 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 1039 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 1039 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13443500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13443500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56656500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56656500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5608000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5608000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56656500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19051500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 75708000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56656500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19051500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 75708000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68241.116751 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68241.116751 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73389.248705 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73389.248705 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80114.285714 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80114.285714 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73389.248705 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71353.932584 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72866.217517 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1056 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 841 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 773 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1561 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2093 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50432 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 67392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 1040 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000962 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.031009 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1039 99.90% 99.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1040 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 544000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1159500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 1038 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 66743000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 840 # Transaction distribution
-system.membus.trans_dist::ReadExReq 197 # Transaction distribution
-system.membus.trans_dist::ReadExResp 197 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 841 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2075 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2075 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 66368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1038 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1038 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1038 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1251500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5471250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 8.2 # Layer utilization (%)
+sim_seconds 0.000124
+sim_ticks 124491500
+final_tick 124491500
+sim_freq 1000000000000
+host_inst_rate 5956
+host_op_rate 5968
+host_tick_rate 6896930
+host_mem_usage 272248
+host_seconds 18.05
+sim_insts 107505
+sim_ops 107717
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 124491500
+system.physmem.bytes_read::cpu.inst 55232
+system.physmem.bytes_read::cpu.data 29568
+system.physmem.bytes_read::total 84800
+system.physmem.bytes_inst_read::cpu.inst 55232
+system.physmem.bytes_inst_read::total 55232
+system.physmem.num_reads::cpu.inst 863
+system.physmem.num_reads::cpu.data 462
+system.physmem.num_reads::total 1325
+system.physmem.bw_read::cpu.inst 443660812
+system.physmem.bw_read::cpu.data 237510191
+system.physmem.bw_read::total 681171004
+system.physmem.bw_inst_read::cpu.inst 443660812
+system.physmem.bw_inst_read::total 443660812
+system.physmem.bw_total::cpu.inst 443660812
+system.physmem.bw_total::cpu.data 237510191
+system.physmem.bw_total::total 681171004
+system.physmem.readReqs 1325
+system.physmem.writeReqs 0
+system.physmem.readBursts 1325
+system.physmem.writeBursts 0
+system.physmem.bytesReadDRAM 84800
+system.physmem.bytesReadWrQ 0
+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 84800
+system.physmem.bytesWrittenSys 0
+system.physmem.servicedByWrQ 0
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 160
+system.physmem.perBankRdBursts::1 75
+system.physmem.perBankRdBursts::2 130
+system.physmem.perBankRdBursts::3 69
+system.physmem.perBankRdBursts::4 28
+system.physmem.perBankRdBursts::5 73
+system.physmem.perBankRdBursts::6 30
+system.physmem.perBankRdBursts::7 36
+system.physmem.perBankRdBursts::8 80
+system.physmem.perBankRdBursts::9 128
+system.physmem.perBankRdBursts::10 170
+system.physmem.perBankRdBursts::11 139
+system.physmem.perBankRdBursts::12 54
+system.physmem.perBankRdBursts::13 52
+system.physmem.perBankRdBursts::14 50
+system.physmem.perBankRdBursts::15 51
+system.physmem.perBankWrBursts::0 0
+system.physmem.perBankWrBursts::1 0
+system.physmem.perBankWrBursts::2 0
+system.physmem.perBankWrBursts::3 0
+system.physmem.perBankWrBursts::4 0
+system.physmem.perBankWrBursts::5 0
+system.physmem.perBankWrBursts::6 0
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 0
+system.physmem.perBankWrBursts::10 0
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 124370500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 1325
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 0
+system.physmem.rdQLenPdf::0 795
+system.physmem.rdQLenPdf::1 342
+system.physmem.rdQLenPdf::2 133
+system.physmem.rdQLenPdf::3 44
+system.physmem.rdQLenPdf::4 10
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 0
+system.physmem.rdQLenPdf::7 0
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+system.physmem.rdQLenPdf::9 0
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+system.physmem.rdQLenPdf::12 0
+system.physmem.rdQLenPdf::13 0
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+system.physmem.rdQLenPdf::16 0
+system.physmem.rdQLenPdf::17 0
+system.physmem.rdQLenPdf::18 0
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+system.physmem.rdQLenPdf::20 0
+system.physmem.rdQLenPdf::21 0
+system.physmem.rdQLenPdf::22 0
+system.physmem.rdQLenPdf::23 0
+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
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+system.physmem.rdQLenPdf::28 0
+system.physmem.rdQLenPdf::29 0
+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 0
+system.physmem.wrQLenPdf::1 0
+system.physmem.wrQLenPdf::2 0
+system.physmem.wrQLenPdf::3 0
+system.physmem.wrQLenPdf::4 0
+system.physmem.wrQLenPdf::5 0
+system.physmem.wrQLenPdf::6 0
+system.physmem.wrQLenPdf::7 0
+system.physmem.wrQLenPdf::8 0
+system.physmem.wrQLenPdf::9 0
+system.physmem.wrQLenPdf::10 0
+system.physmem.wrQLenPdf::11 0
+system.physmem.wrQLenPdf::12 0
+system.physmem.wrQLenPdf::13 0
+system.physmem.wrQLenPdf::14 0
+system.physmem.wrQLenPdf::15 0
+system.physmem.wrQLenPdf::16 0
+system.physmem.wrQLenPdf::17 0
+system.physmem.wrQLenPdf::18 0
+system.physmem.wrQLenPdf::19 0
+system.physmem.wrQLenPdf::20 0
+system.physmem.wrQLenPdf::21 0
+system.physmem.wrQLenPdf::22 0
+system.physmem.wrQLenPdf::23 0
+system.physmem.wrQLenPdf::24 0
+system.physmem.wrQLenPdf::25 0
+system.physmem.wrQLenPdf::26 0
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+system.physmem.wrQLenPdf::30 0
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+system.physmem.wrQLenPdf::32 0
+system.physmem.wrQLenPdf::33 0
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+system.physmem.wrQLenPdf::35 0
+system.physmem.wrQLenPdf::36 0
+system.physmem.wrQLenPdf::37 0
+system.physmem.wrQLenPdf::38 0
+system.physmem.wrQLenPdf::39 0
+system.physmem.wrQLenPdf::40 0
+system.physmem.wrQLenPdf::41 0
+system.physmem.wrQLenPdf::42 0
+system.physmem.wrQLenPdf::43 0
+system.physmem.wrQLenPdf::44 0
+system.physmem.wrQLenPdf::45 0
+system.physmem.wrQLenPdf::46 0
+system.physmem.wrQLenPdf::47 0
+system.physmem.wrQLenPdf::48 0
+system.physmem.wrQLenPdf::49 0
+system.physmem.wrQLenPdf::50 0
+system.physmem.wrQLenPdf::51 0
+system.physmem.wrQLenPdf::52 0
+system.physmem.wrQLenPdf::53 0
+system.physmem.wrQLenPdf::54 0
+system.physmem.wrQLenPdf::55 0
+system.physmem.wrQLenPdf::56 0
+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
+system.physmem.wrQLenPdf::59 0
+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 293
+system.physmem.bytesPerActivate::mean 282.866894
+system.physmem.bytesPerActivate::gmean 183.394708
+system.physmem.bytesPerActivate::stdev 273.006748
+system.physmem.bytesPerActivate::0-127 100 34.13% 34.13%
+system.physmem.bytesPerActivate::128-255 66 22.53% 56.66%
+system.physmem.bytesPerActivate::256-383 47 16.04% 72.70%
+system.physmem.bytesPerActivate::384-511 26 8.87% 81.57%
+system.physmem.bytesPerActivate::512-639 11 3.75% 85.32%
+system.physmem.bytesPerActivate::640-767 15 5.12% 90.44%
+system.physmem.bytesPerActivate::768-895 9 3.07% 93.52%
+system.physmem.bytesPerActivate::896-1023 4 1.37% 94.88%
+system.physmem.bytesPerActivate::1024-1151 15 5.12% 100.00%
+system.physmem.bytesPerActivate::total 293
+system.physmem.totQLat 20133000
+system.physmem.totMemAccLat 44976750
+system.physmem.totBusLat 6625000
+system.physmem.avgQLat 15194.72
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 33944.72
+system.physmem.avgRdBW 681.17
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 681.17
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 5.32
+system.physmem.busUtilRead 5.32
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.54
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 1019
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 76.91
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 93864.53
+system.physmem.pageHitRate 76.91
+system.physmem_0.actEnergy 956760
+system.physmem_0.preEnergy 481965
+system.physmem_0.readEnergy 4291140
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 9219600.000000
+system.physmem_0.actBackEnergy 9317790
+system.physmem_0.preBackEnergy 204960
+system.physmem_0.actPowerDownEnergy 46016100
+system.physmem_0.prePowerDownEnergy 1003200
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 71491515
+system.physmem_0.averagePower 574.263630
+system.physmem_0.totalIdleTime 101911500
+system.physmem_0.memoryStateTime::IDLE 89500
+system.physmem_0.memoryStateTime::REF 3900000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 2612500
+system.physmem_0.memoryStateTime::ACT 16963750
+system.physmem_0.memoryStateTime::ACT_PDN 100925750
+system.physmem_1.actEnergy 1228080
+system.physmem_1.preEnergy 629970
+system.physmem_1.readEnergy 5169360
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 9219600.000000
+system.physmem_1.actBackEnergy 9878670
+system.physmem_1.preBackEnergy 257760
+system.physmem_1.actPowerDownEnergy 41086740
+system.physmem_1.prePowerDownEnergy 4629120
+system.physmem_1.selfRefreshEnergy 0
+system.physmem_1.totalEnergy 72099300
+system.physmem_1.averagePower 579.145732
+system.physmem_1.totalIdleTime 102065000
+system.physmem_1.memoryStateTime::IDLE 260500
+system.physmem_1.memoryStateTime::REF 3900000
+system.physmem_1.memoryStateTime::SREF 0
+system.physmem_1.memoryStateTime::PRE_PDN 12050750
+system.physmem_1.memoryStateTime::ACT 18181250
+system.physmem_1.memoryStateTime::ACT_PDN 90099000
+system.pwrStateResidencyTicks::UNDEFINED 124491500
+system.cpu.branchPred.lookups 34816
+system.cpu.branchPred.condPredicted 24305
+system.cpu.branchPred.condIncorrect 7878
+system.cpu.branchPred.BTBLookups 27691
+system.cpu.branchPred.BTBHits 13759
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 49.687624
+system.cpu.branchPred.usedRAS 0
+system.cpu.branchPred.RASInCorrect 0
+system.cpu.branchPred.indirectLookups 7171
+system.cpu.branchPred.indirectHits 3706
+system.cpu.branchPred.indirectMisses 3465
+system.cpu.branchPredindirectMispredicted 1414
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
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+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 45
+system.cpu.pwrStateResidencyTicks::ON 124491500
+system.cpu.numCycles 248984
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 46747
+system.cpu.fetch.Insts 152710
+system.cpu.fetch.Branches 34816
+system.cpu.fetch.predictedBranches 17465
+system.cpu.fetch.Cycles 114549
+system.cpu.fetch.SquashCycles 15876
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+system.cpu.fetch.CacheLines 27073
+system.cpu.fetch.IcacheSquashes 1404
+system.cpu.fetch.rateDist::samples 169333
+system.cpu.fetch.rateDist::mean 0.903238
+system.cpu.fetch.rateDist::stdev 0.994367
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00%
+system.cpu.fetch.rateDist::0 63074 37.25% 37.25%
+system.cpu.fetch.rateDist::1 77291 45.64% 82.89%
+system.cpu.fetch.rateDist::2 18218 10.76% 93.65%
+system.cpu.fetch.rateDist::3 6642 3.92% 97.57%
+system.cpu.fetch.rateDist::4 2533 1.50% 99.07%
+system.cpu.fetch.rateDist::5 841 0.50% 99.57%
+system.cpu.fetch.rateDist::6 409 0.24% 99.81%
+system.cpu.fetch.rateDist::7 96 0.06% 99.86%
+system.cpu.fetch.rateDist::8 229 0.14% 100.00%
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00%
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::total 169333
+system.cpu.fetch.branchRate 0.139832
+system.cpu.fetch.rate 0.613333
+system.cpu.decode.IdleCycles 53035
+system.cpu.decode.BlockedCycles 15088
+system.cpu.decode.RunCycles 95872
+system.cpu.decode.UnblockCycles 411
+system.cpu.decode.SquashCycles 4927
+system.cpu.decode.BranchResolved 13489
+system.cpu.decode.BranchMispred 3125
+system.cpu.decode.DecodedInsts 138749
+system.cpu.decode.SquashedInsts 4432
+system.cpu.rename.SquashCycles 4927
+system.cpu.rename.IdleCycles 59325
+system.cpu.rename.BlockCycles 2075
+system.cpu.rename.serializeStallCycles 7298
+system.cpu.rename.RunCycles 89979
+system.cpu.rename.UnblockCycles 5729
+system.cpu.rename.RenamedInsts 132331
+system.cpu.rename.ROBFullEvents 3
+system.cpu.rename.IQFullEvents 12
+system.cpu.rename.LQFullEvents 2887
+system.cpu.rename.SQFullEvents 2573
+system.cpu.rename.RenamedOperands 88185
+system.cpu.rename.RenameLookups 161560
+system.cpu.rename.int_rename_lookups 161362
+system.cpu.rename.fp_rename_lookups 198
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+system.cpu.rename.serializingInsts 307
+system.cpu.rename.tempSerializingInsts 307
+system.cpu.rename.skidInsts 859
+system.cpu.memDep0.insertedLoads 28420
+system.cpu.memDep0.insertedStores 17484
+system.cpu.memDep0.conflictingLoads 175
+system.cpu.memDep0.conflictingStores 17
+system.cpu.iq.iqInstsAdded 121763
+system.cpu.iq.iqNonSpecInstsAdded 551
+system.cpu.iq.iqInstsIssued 119946
+system.cpu.iq.iqSquashedInstsIssued 110
+system.cpu.iq.iqSquashedInstsExamined 14590
+system.cpu.iq.iqSquashedOperandsExamined 6084
+system.cpu.iq.iqSquashedNonSpecRemoved 47
+system.cpu.iq.issued_per_cycle::samples 169333
+system.cpu.iq.issued_per_cycle::mean 0.708344
+system.cpu.iq.issued_per_cycle::stdev 0.867381
+system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
+system.cpu.iq.issued_per_cycle::0 82784 48.89% 48.89%
+system.cpu.iq.issued_per_cycle::1 62057 36.65% 85.54%
+system.cpu.iq.issued_per_cycle::2 18132 10.71% 96.24%
+system.cpu.iq.issued_per_cycle::3 4720 2.79% 99.03%
+system.cpu.iq.issued_per_cycle::4 1062 0.63% 99.66%
+system.cpu.iq.issued_per_cycle::5 352 0.21% 99.87%
+system.cpu.iq.issued_per_cycle::6 152 0.09% 99.96%
+system.cpu.iq.issued_per_cycle::7 47 0.03% 99.98%
+system.cpu.iq.issued_per_cycle::8 27 0.02% 100.00%
+system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00%
+system.cpu.iq.issued_per_cycle::min_value 0
+system.cpu.iq.issued_per_cycle::max_value 8
+system.cpu.iq.issued_per_cycle::total 169333
+system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00%
+system.cpu.iq.fu_full::IntAlu 19 10.33% 10.33%
+system.cpu.iq.fu_full::IntMult 0 0.00% 10.33%
+system.cpu.iq.fu_full::IntDiv 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatMult 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.33%
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdMult 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdShift 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.33%
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.33%
+system.cpu.iq.fu_full::MemRead 60 32.61% 42.93%
+system.cpu.iq.fu_full::MemWrite 102 55.43% 98.37%
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+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1340
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+system.membus.pkt_count::total 2650
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+system.membus.snoops 0
+system.membus.snoopTraffic 0
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+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1325 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
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+system.membus.reqLayer0.utilization 1.3
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---------- End Simulation Statistics ----------
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
width=1
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:49
-gem5 executing on zizzer, pid 34098
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:10:51
+gem5 executing on boldrock, pid 1656
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
mul: PASS
mul, overflow: PASS
mulh: PASS
remuw/0: PASS
remuw, "overflow": PASS
remuw, sign extend: PASS
-Exiting @ tick 56668000 because target called exit()
+Exiting @ tick 67349000 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000057 # Number of seconds simulated
-sim_ticks 56668000 # Number of ticks simulated
-final_tick 56668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 42634 # Simulator instruction rate (inst/s)
-host_op_rate 42633 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 21324951 # Simulator tick rate (ticks/s)
-host_mem_usage 233724 # Number of bytes of host memory used
-host_seconds 2.66 # Real time elapsed on the host
-sim_insts 113291 # Number of instructions simulated
-sim_ops 113291 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 453348 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 156046 # Number of bytes read from this memory
-system.physmem.bytes_read::total 609394 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 453348 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 453348 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 110317 # Number of bytes written to this memory
-system.physmem.bytes_written::total 110317 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 113337 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 23780 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 137117 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 19712 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 19712 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8000070587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2753688149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10753758735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8000070587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8000070587 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1946724783 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1946724783 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8000070587 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4700412931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12700483518 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 45 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 56668000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 113337 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113291 # Number of instructions committed
-system.cpu.committedOps 113291 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 8529 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls
-system.cpu.num_int_insts 113292 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 151096 # number of times the integer registers were read
-system.cpu.num_int_register_writes 76188 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 43493 # number of memory refs
-system.cpu.num_load_insts 23780 # Number of load instructions
-system.cpu.num_store_insts 19713 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 113337 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 25920 # Number of branches fetched
-system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction
-system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction
-system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction
-system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 113337 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 137117 # Transaction distribution
-system.membus.trans_dist::ReadResp 137117 # Transaction distribution
-system.membus.trans_dist::WriteReq 19712 # Transaction distribution
-system.membus.trans_dist::WriteResp 19712 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 226674 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 86984 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 313658 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 453348 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 266363 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 719711 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 156829 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 156829 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 156829 # Request fanout histogram
+sim_seconds 0.000067
+sim_ticks 67349000
+final_tick 67349000
+sim_freq 1000000000000
+host_inst_rate 5719
+host_op_rate 5730
+host_tick_rate 3582584
+host_mem_usage 259188
+host_seconds 18.80
+sim_insts 107505
+sim_ops 107717
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 67349000
+system.physmem.bytes_read::cpu.inst 537948
+system.physmem.bytes_read::cpu.data 170929
+system.physmem.bytes_read::total 708877
+system.physmem.bytes_inst_read::cpu.inst 537948
+system.physmem.bytes_inst_read::total 537948
+system.physmem.bytes_written::cpu.data 109969
+system.physmem.bytes_written::total 109969
+system.physmem.num_reads::cpu.inst 134487
+system.physmem.num_reads::cpu.data 25266
+system.physmem.num_reads::total 159753
+system.physmem.num_writes::cpu.data 16339
+system.physmem.num_writes::total 16339
+system.physmem.bw_read::cpu.inst 7987468262
+system.physmem.bw_read::cpu.data 2537958990
+system.physmem.bw_read::total 10525427252
+system.physmem.bw_inst_read::cpu.inst 7987468262
+system.physmem.bw_inst_read::total 7987468262
+system.physmem.bw_write::cpu.data 1632823056
+system.physmem.bw_write::total 1632823056
+system.physmem.bw_total::cpu.inst 7987468262
+system.physmem.bw_total::cpu.data 4170782046
+system.physmem.bw_total::total 12158250308
+system.pwrStateResidencyTicks::UNDEFINED 67349000
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 45
+system.cpu.pwrStateResidencyTicks::ON 67349000
+system.cpu.numCycles 134699
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 107505
+system.cpu.committedOps 107717
+system.cpu.num_int_alu_accesses 107132
+system.cpu.num_fp_alu_accesses 12
+system.cpu.num_vec_alu_accesses 0
+system.cpu.num_func_calls 6215
+system.cpu.num_conditional_control_insts 17634
+system.cpu.num_int_insts 107132
+system.cpu.num_fp_insts 12
+system.cpu.num_vec_insts 0
+system.cpu.num_int_register_reads 134283
+system.cpu.num_int_register_writes 70918
+system.cpu.num_fp_register_reads 12
+system.cpu.num_fp_register_writes 0
+system.cpu.num_vec_register_reads 0
+system.cpu.num_vec_register_writes 0
+system.cpu.num_mem_refs 41605
+system.cpu.num_load_insts 25266
+system.cpu.num_store_insts 16339
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 134699
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 23849
+system.cpu.op_class::No_OpClass 49 0.05% 0.05%
+system.cpu.op_class::IntAlu 65954 61.20% 61.25%
+system.cpu.op_class::IntMult 124 0.12% 61.36%
+system.cpu.op_class::IntDiv 30 0.03% 61.39%
+system.cpu.op_class::FloatAdd 0 0.00% 61.39%
+system.cpu.op_class::FloatCmp 0 0.00% 61.39%
+system.cpu.op_class::FloatCvt 0 0.00% 61.39%
+system.cpu.op_class::FloatMult 0 0.00% 61.39%
+system.cpu.op_class::FloatMultAcc 0 0.00% 61.39%
+system.cpu.op_class::FloatDiv 0 0.00% 61.39%
+system.cpu.op_class::FloatMisc 0 0.00% 61.39%
+system.cpu.op_class::FloatSqrt 0 0.00% 61.39%
+system.cpu.op_class::SimdAdd 0 0.00% 61.39%
+system.cpu.op_class::SimdAddAcc 0 0.00% 61.39%
+system.cpu.op_class::SimdAlu 0 0.00% 61.39%
+system.cpu.op_class::SimdCmp 0 0.00% 61.39%
+system.cpu.op_class::SimdCvt 0 0.00% 61.39%
+system.cpu.op_class::SimdMisc 0 0.00% 61.39%
+system.cpu.op_class::SimdMult 0 0.00% 61.39%
+system.cpu.op_class::SimdMultAcc 0 0.00% 61.39%
+system.cpu.op_class::SimdShift 0 0.00% 61.39%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 61.39%
+system.cpu.op_class::SimdSqrt 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatMult 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.39%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.39%
+system.cpu.op_class::MemRead 25266 23.45% 84.84%
+system.cpu.op_class::MemWrite 16327 15.15% 99.99%
+system.cpu.op_class::FloatMemRead 0 0.00% 99.99%
+system.cpu.op_class::FloatMemWrite 12 0.01% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 107762
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 67349000
+system.membus.trans_dist::ReadReq 159516
+system.membus.trans_dist::ReadResp 159753
+system.membus.trans_dist::WriteReq 16102
+system.membus.trans_dist::WriteResp 16102
+system.membus.trans_dist::LoadLockedReq 237
+system.membus.trans_dist::StoreCondReq 237
+system.membus.trans_dist::StoreCondResp 237
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 268974
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 83210
+system.membus.pkt_count::total 352184
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 537948
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 280898
+system.membus.pkt_size::total 818846
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 176092
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 176092 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 176092
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
[system.ruby.dir_cntrl0]
type=Directory_Controller
children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory
+addr_ranges=0:268435455:5:0:0:0
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
ruby_system=system.ruby
system=system
to_memory_controller_latency=1
-transitions_per_cycle=4
+transitions_per_cycle=32
version=0
memory=system.mem_ctrls.port
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+addr_ranges=0:268435455:5:0:0:0
eventq_index=0
-numa_high_bit=5
-size=268435456
-version=0
[system.ruby.dir_cntrl0.dmaRequestToDir]
type=MessageBuffer
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer
+addr_ranges=0:18446744073709551615:0:0:0:0
buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
"path": "system.ruby.l1_cntrl0.requestFromCache",
"type": "MessageBuffer"
},
- "cxx_class": "L1Cache_Controller",
"forwardToCache": {
"ordered": true,
"name": "forwardToCache",
"support_data_reqs": true,
"is_cpu_sequencer": true
},
- "type": "L1Cache_Controller",
+ "cxx_class": "L1Cache_Controller",
"issue_latency": 2,
+ "type": "L1Cache_Controller",
"recycle_latency": 10,
"clk_domain": "system.cpu.clk_domain",
"version": 0,
},
"ruby_system": "system.ruby",
"name": "l1_cntrl0",
+ "addr_ranges": [
+ "0:18446744073709551615:0:0:0:0"
+ ],
"p_state_clk_gate_bins": 20,
"mandatoryQueue": {
"ordered": false,
"path": "system.ruby.dir_cntrl0.responseFromDir",
"type": "MessageBuffer"
},
- "transitions_per_cycle": 4,
+ "transitions_per_cycle": 32,
"memory": {
"peer": "system.mem_ctrls.port",
"role": "MASTER"
},
"power_model": null,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"buffer_size": 0,
"ruby_system": "system.ruby",
"requestToDir": {
"p_state_clk_gate_bins": 20,
"directory": {
"name": "directory",
- "version": 0,
+ "addr_ranges": [
+ "0:268435455:5:0:0:0"
+ ],
"eventq_index": 0,
"cxx_class": "DirectoryMemory",
"path": "system.ruby.dir_cntrl0.directory",
- "type": "RubyDirectoryMemory",
- "numa_high_bit": 5,
- "size": 268435456
+ "type": "RubyDirectoryMemory"
},
"path": "system.ruby.dir_cntrl0"
}
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
+warn: rounding error > tolerance
+ 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:53
-gem5 executing on zizzer, pid 34103
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:09:50
+gem5 executing on boldrock, pid 1343
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
mul: PASS
mul, overflow: PASS
mulh: PASS
remuw/0: PASS
remuw, "overflow": PASS
remuw, sign extend: PASS
-Exiting @ tick 1841805 because target called exit()
+Exiting @ tick 1858825 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.001842 # Number of seconds simulated
-sim_ticks 1841805 # Number of ticks simulated
-final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 106701 # Simulator instruction rate (inst/s)
-host_op_rate 106700 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1734637 # Simulator tick rate (ticks/s)
-host_mem_usage 428500 # Number of bytes of host memory used
-host_seconds 1.06 # Real time elapsed on the host
-sim_insts 113291 # Number of instructions simulated
-sim_ops 113291 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1901888 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 1901888 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1901632 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 1901632 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 29717 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 29717 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 29713 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 29713 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032621803 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1032621803 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032482809 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1032482809 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2065104612 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2065104612 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 29717 # Number of read requests accepted
-system.mem_ctrls.writeReqs 29713 # Number of write requests accepted
-system.mem_ctrls.readBursts 29717 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 29713 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 810816 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 1091072 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 842496 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 1901888 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 1901632 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 17048 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 16517 # Number of DRAM write bursts merged with an existing one
-system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 1366 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 3 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 241 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 400 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 244 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 371 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 334 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 67 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 341 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 2380 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 1301 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 1236 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 1592 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 483 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 2223 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 87 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 1405 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 3 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 241 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 412 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 257 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 383 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 346 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 69 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 351 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 2448 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 1316 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 1275 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 1634 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 505 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 2424 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 95 # Per bank write bursts
-system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 1841733 # Total gap between requests
-system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 29717 # Read request sizes (log2)
-system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 29713 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 12669 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 104 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 124 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 715 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 812 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 810 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 826 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 868 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 857 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 811 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 807 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 806 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 805 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 4235 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 390.135537 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 255.090286 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 338.320461 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 828 19.55% 19.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 1136 26.82% 46.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 580 13.70% 60.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 361 8.52% 68.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 278 6.56% 75.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 169 3.99% 79.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 146 3.45% 82.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 150 3.54% 86.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 587 13.86% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 4235 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 805 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.719255 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.645655 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 1.595450 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 50 6.21% 6.21% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 309 38.39% 44.60% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 373 46.34% 90.93% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 65 8.07% 99.01% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 7 0.87% 99.88% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 0.12% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 805 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 805 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.352795 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.329834 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.903150 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 691 85.84% 85.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 4 0.50% 86.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 56 6.96% 93.29% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 48 5.96% 99.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 6 0.75% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 805 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 239535 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 480246 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 63345 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 18.91 # Average queueing delay per DRAM burst
-system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 37.91 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 440.23 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 457.43 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1032.62 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1032.48 # Average system write bandwidth in MiByte/s
-system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 7.01 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 3.44 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 9468 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 12124 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 74.73 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 91.88 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 30.99 # Average gap between requests
-system.mem_ctrls.pageHitRate 83.48 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 10074540 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 5448240 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 34569024 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 26024832 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 127230480.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 197709288 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 3259392 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.actPowerDownEnergy 446690304 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_0.prePowerDownEnergy 61497984 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_0.selfRefreshEnergy 65163360 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_0.totalEnergy 977667444 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 530.820279 # Core power per rank (mW)
-system.mem_ctrls_0.totalIdleTime 1399707 # Total Idle time Per DRAM Rank
-system.mem_ctrls_0.memoryStateTime::IDLE 2653 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 53850 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::SREF 260009 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 160151 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 385558 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 979584 # Time in different power states
-system.mem_ctrls_1.actEnergy 20206200 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 10915800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 110161632 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 83920896 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 145055040.000000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 217978032 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3880704 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.actPowerDownEnergy 529686864 # Energy for active power-down per rank (pJ)
-system.mem_ctrls_1.prePowerDownEnergy 51989376 # Energy for precharge power-down per rank (pJ)
-system.mem_ctrls_1.selfRefreshEnergy 18024480 # Energy for self refresh per rank (pJ)
-system.mem_ctrls_1.totalEnergy 1191819024 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 647.092946 # Core power per rank (mW)
-system.mem_ctrls_1.totalIdleTime 1353468 # Total Idle time Per DRAM Rank
-system.mem_ctrls_1.memoryStateTime::IDLE 3236 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 61408 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::SREF 56694 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 135389 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 423484 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 1161594 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.cpu.clk_domain.clock 1 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 45 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 1841805 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1841805 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113291 # Number of instructions committed
-system.cpu.committedOps 113291 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 8529 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls
-system.cpu.num_int_insts 113292 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 151096 # number of times the integer registers were read
-system.cpu.num_int_register_writes 76188 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 43493 # number of memory refs
-system.cpu.num_load_insts 23780 # Number of load instructions
-system.cpu.num_store_insts 19713 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1841805 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 25920 # Number of branches fetched
-system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction
-system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction
-system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction
-system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 113337 # Class of executed instruction
-system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.ruby.delayHist::bucket_size 1 # delay histogram for all message
-system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 59430 # delay histogram for all message
-system.ruby.delayHist | 59430 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 59430 # delay histogram for all message
+sim_seconds 0.001859
+sim_ticks 1858825
+final_tick 1858825
+sim_freq 1000000000
+host_inst_rate 3630
+host_op_rate 3637
+host_tick_rate 62766
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+system.mem_ctrls.bytesPerActivate::1024-1151 346 6.61% 100.00%
+system.mem_ctrls.bytesPerActivate::total 5236
+system.mem_ctrls.rdPerTurnAround::samples 810
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+system.mem_ctrls.rdPerTurnAround::18-19 78 9.63% 99.51%
+system.mem_ctrls.rdPerTurnAround::20-21 3 0.37% 99.88%
+system.mem_ctrls.rdPerTurnAround::34-35 1 0.12% 100.00%
+system.mem_ctrls.rdPerTurnAround::total 810
+system.mem_ctrls.wrPerTurnAround::samples 810
+system.mem_ctrls.wrPerTurnAround::mean 16.404938
+system.mem_ctrls.wrPerTurnAround::gmean 16.379881
+system.mem_ctrls.wrPerTurnAround::stdev 0.941542
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+system.mem_ctrls.wrPerTurnAround::17 11 1.36% 84.57%
+system.mem_ctrls.wrPerTurnAround::18 60 7.41% 91.98%
+system.mem_ctrls.wrPerTurnAround::19 63 7.78% 99.75%
+system.mem_ctrls.wrPerTurnAround::20 2 0.25% 100.00%
+system.mem_ctrls.wrPerTurnAround::total 810
+system.mem_ctrls.totQLat 246353
+system.mem_ctrls.totMemAccLat 486380
+system.mem_ctrls.totBusLat 63165
+system.mem_ctrls.avgQLat 19.50
+system.mem_ctrls.avgBusLat 5.00
+system.mem_ctrls.avgMemAccLat 38.50
+system.mem_ctrls.avgRdBW 434.96
+system.mem_ctrls.avgWrBW 457.51
+system.mem_ctrls.avgRdBWSys 992.87
+system.mem_ctrls.avgWrBWSys 992.73
+system.mem_ctrls.peakBW 12800.00
+system.mem_ctrls.busUtil 6.97
+system.mem_ctrls.busUtilRead 3.40
+system.mem_ctrls.busUtilWrite 3.57
+system.mem_ctrls.avgRdQLen 1.00
+system.mem_ctrls.avgWrQLen 26.25
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+system.mem_ctrls.avgGap 32.23
+system.mem_ctrls.pageHitRate 79.66
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+system.mem_ctrls_0.actBackEnergy 210861240
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+system.mem_ctrls_1.actEnergy 27803160
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+system.mem_ctrls_1.memoryStateTime::IDLE 2339
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+system.cpu.op_class::MemRead 25266 23.45% 84.84%
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+system.cpu.op_class::total 107762
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+system.ruby.delayHist::samples 57670
+system.ruby.delayHist | 57670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.delayHist::total 57670
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 156830
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system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 156830 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
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-system.ruby.latency_hist_seqr::gmean 2.067079
-system.ruby.latency_hist_seqr::stdev 25.213617
-system.ruby.latency_hist_seqr | 144536 92.16% 92.16% | 11426 7.29% 99.45% | 606 0.39% 99.83% | 87 0.06% 99.89% | 95 0.06% 99.95% | 65 0.04% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00%
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system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
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system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 127112 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 127112
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system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
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-system.ruby.miss_latency_hist_seqr::gmean 46.160524
-system.ruby.miss_latency_hist_seqr::stdev 34.809845
-system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00%
-system.ruby.miss_latency_hist_seqr::total 29717
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-system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.016133 # Average number of messages in buffer
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-system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses
-system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.016133 # Average number of messages in buffer
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-system.ruby.network.routers0.percent_links_utilized 8.066815
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-system.ruby.network.routers0.msg_count.Data::2 29713
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-system.ruby.network.routers0.msg_bytes.Data::2 2139336
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-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704
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-system.ruby.network.routers1.percent_links_utilized 8.066815
-system.ruby.network.routers1.msg_count.Control::2 29717
-system.ruby.network.routers1.msg_count.Data::2 29713
-system.ruby.network.routers1.msg_count.Response_Data::4 29717
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-system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704
-system.ruby.network.int_link_buffers02.avg_buf_msgs 0.032267 # Average number of messages in buffer
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-system.ruby.network.int_link_buffers17.avg_buf_msgs 0.032267 # Average number of messages in buffer
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-system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.016133 # Average number of messages in buffer
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-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 8.066815
-system.ruby.network.routers2.msg_count.Control::2 29717
-system.ruby.network.routers2.msg_count.Data::2 29713
-system.ruby.network.routers2.msg_count.Response_Data::4 29717
-system.ruby.network.routers2.msg_count.Writeback_Control::3 29713
-system.ruby.network.routers2.msg_bytes.Control::2 237736
-system.ruby.network.routers2.msg_bytes.Data::2 2139336
-system.ruby.network.routers2.msg_bytes.Response_Data::4 2139624
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 237704
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.ruby.network.msg_count.Control 89151
-system.ruby.network.msg_count.Data 89139
-system.ruby.network.msg_count.Response_Data 89151
-system.ruby.network.msg_count.Writeback_Control 89139
-system.ruby.network.msg_byte.Control 713208
-system.ruby.network.msg_byte.Data 6418008
-system.ruby.network.msg_byte.Response_Data 6418872
-system.ruby.network.msg_byte.Writeback_Control 713112
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 8.067249
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 29717
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 29713
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2139624
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 237704
-system.ruby.network.routers0.throttle1.link_utilization 8.066381
-system.ruby.network.routers0.throttle1.msg_count.Control::2 29717
-system.ruby.network.routers0.throttle1.msg_count.Data::2 29713
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 237736
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2139336
-system.ruby.network.routers1.throttle0.link_utilization 8.066381
-system.ruby.network.routers1.throttle0.msg_count.Control::2 29717
-system.ruby.network.routers1.throttle0.msg_count.Data::2 29713
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 237736
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2139336
-system.ruby.network.routers1.throttle1.link_utilization 8.067249
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 29717
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 29713
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2139624
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 237704
-system.ruby.network.routers2.throttle0.link_utilization 8.067249
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 29717
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 29713
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2139624
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 237704
-system.ruby.network.routers2.throttle1.link_utilization 8.066381
-system.ruby.network.routers2.throttle1.msg_count.Control::2 29717
-system.ruby.network.routers2.throttle1.msg_count.Data::2 29713
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 237736
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2139336
-system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 29717 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 29717 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 29717 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 29713 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 29713 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 29713 # delay histogram for vnet_2
+system.ruby.miss_latency_hist_seqr::samples 28837
+system.ruby.miss_latency_hist_seqr::mean 53.246801
+system.ruby.miss_latency_hist_seqr::gmean 46.837910
+system.ruby.miss_latency_hist_seqr::stdev 34.758587
+system.ruby.miss_latency_hist_seqr | 16673 57.82% 57.82% | 11377 39.45% 97.27% | 529 1.83% 99.11% | 95 0.33% 99.43% | 91 0.32% 99.75% | 54 0.19% 99.94% | 8 0.03% 99.97% | 3 0.01% 99.98% | 0 0.00% 99.98% | 7 0.02% 100.00%
+system.ruby.miss_latency_hist_seqr::total 28837
+system.ruby.Directory.incomplete_times_seqr 28836
+system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015511
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+system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.751023
+system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015514
+system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999963
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+system.ruby.Load_Linked.hit_latency_hist_seqr::samples 45
+system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1
+system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1
+system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 45 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.hit_latency_hist_seqr::total 45
+system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 32
+system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 319
+system.ruby.Load_Linked.miss_latency_hist_seqr::samples 192
+system.ruby.Load_Linked.miss_latency_hist_seqr::mean 56.312500
+system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 49.908811
+system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 34.375449
+system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 89 46.35% 46.35% | 95 49.48% 95.83% | 1 0.52% 96.35% | 1 0.52% 96.88% | 2 1.04% 97.92% | 3 1.56% 99.48% | 0 0.00% 99.48% | 0 0.00% 99.48% | 1 0.52% 100.00%
+system.ruby.Load_Linked.miss_latency_hist_seqr::total 192
+system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.latency_hist_seqr::samples 237
+system.ruby.Store_Conditional.latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.latency_hist_seqr::total 237
+system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 237
+system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 237 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.hit_latency_hist_seqr::total 237
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 29717
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.423327
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.160524
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.809845
-system.ruby.Directory.miss_mach_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 29717
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 28837
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.246801
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.837910
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.758587
+system.ruby.Directory.miss_mach_latency_hist_seqr | 16673 57.82% 57.82% | 11377 39.45% 97.27% | 529 1.83% 99.11% | 95 0.33% 99.43% | 91 0.32% 99.75% | 54 0.19% 99.94% | 8 0.03% 99.97% | 3 0.01% 99.98% | 0 0.00% 99.98% | 7 0.02% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 28837
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 10971
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 49.864552
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.959200
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.000652
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 10971
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 12623
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.559693
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.183238
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.139513
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7520 59.57% 59.57% | 4779 37.86% 97.43% | 221 1.75% 99.18% | 36 0.29% 99.47% | 38 0.30% 99.77% | 23 0.18% 99.95% | 4 0.03% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 12623
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5190
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.606166
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.775024
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.868458
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00%
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5190
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5390
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.346753
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.966782
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.990026
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4229 78.46% 78.46% | 1070 19.85% 98.31% | 62 1.15% 99.46% | 8 0.15% 99.61% | 10 0.19% 99.80% | 6 0.11% 99.91% | 0 0.00% 99.91% | 1 0.02% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5390
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13556
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 57.487017
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.839427
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.033938
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13556
-system.ruby.Directory_Controller.GETX 29717 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 29713 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 29717 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 29713 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 29717 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 29713 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 29717 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 29713 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 23780 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 113337 0.00% 0.00%
-system.ruby.L1Cache_Controller.Store 19712 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 29717 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 29713 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 29713 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 10971 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Ifetch 13556 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Store 5190 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 12809 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 99781 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Store 14522 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 29713 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 29713 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 24527 0.00% 0.00%
-system.ruby.L1Cache_Controller.IM.Data 5190 0.00% 0.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 10632
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.026147
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.223378
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.074822
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4835 45.48% 45.48% | 5432 51.09% 96.57% | 243 2.29% 98.85% | 48 0.45% 99.30% | 42 0.40% 99.70% | 25 0.24% 99.93% | 4 0.04% 99.97% | 1 0.01% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 10632
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 192
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 56.312500
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 49.908811
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 34.375449
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 89 46.35% 46.35% | 95 49.48% 95.83% | 1 0.52% 96.35% | 1 0.52% 96.88% | 2 1.04% 97.92% | 3 1.56% 99.48% | 0 0.00% 99.48% | 0 0.00% 99.48% | 1 0.52% 100.00%
+system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 192
+system.ruby.Directory_Controller.GETX 28837 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 28833 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 28837 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 28833 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 28837 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 28833 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 28837 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 28833 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 25029 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 134487 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 16576 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 28837 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 28833 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 28833 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 12623 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 10632 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 5582 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 12406 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 123855 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 10994 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 28833 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 28833 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 23255 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Data 5582 0.00% 0.00%
---------- End Simulation Statistics ----------
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
+wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=insttest
cwd=
drivers=
errout=cerr
euid=100
eventq_index=0
-executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest
+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
},
"p_state_clk_gate_bins": 20,
"p_state_clk_gate_min": 1000,
+ "syscallRetryLatency": 10000,
"interrupts": [
{
"eventq_index": 0,
"uid": 100,
"pid": 100,
"kvmInSE": false,
- "cxx_class": "LiveProcess",
- "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest",
+ "cxx_class": "Process",
+ "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest",
"drivers": [],
"system": "system",
"gid": 100,
"eventq_index": 0,
"env": [],
- "input": "cin",
- "ppid": 99,
- "type": "LiveProcess",
+ "maxStackSize": 67108864,
+ "ppid": 0,
+ "type": "Process",
"cwd": "",
+ "pgid": 100,
"simpoint": 0,
"euid": 100,
+ "input": "cin",
"path": "system.cpu.workload",
- "max_stack_size": 67108864,
"name": "workload",
"cmd": [
"insttest"
}
],
"name": "cpu",
+ "wait_for_remote_gdb": false,
"dtb": {
"name": "dtb",
"eventq_index": 0,
-warn: Unknown operating system; assuming Linux.
warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings.
+ Returning '/home/ar4jc/gem5/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest'
+info: Increasing stack size by one page.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 30 2016 14:33:35
-gem5 started Nov 30 2016 16:18:50
-gem5 executing on zizzer, pid 34099
-command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing
+gem5 compiled Jul 13 2017 17:09:45
+gem5 started Jul 13 2017 17:12:17
+gem5 executing on boldrock, pid 2077
+command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
mul: PASS
mul, overflow: PASS
mulh: PASS
remuw/0: PASS
remuw, "overflow": PASS
remuw, sign extend: PASS
-Exiting @ tick 209715500 because target called exit()
+Exiting @ tick 246972500 because exiting with last active thread context
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000210 # Number of seconds simulated
-sim_ticks 209715500 # Number of ticks simulated
-final_tick 209715500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 42175 # Simulator instruction rate (inst/s)
-host_op_rate 42174 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 78069260 # Simulator tick rate (ticks/s)
-host_mem_usage 242960 # Number of bytes of host memory used
-host_seconds 2.69 # Real time elapsed on the host
-sim_insts 113291 # Number of instructions simulated
-sim_ops 113291 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 37952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 16640 # Number of bytes read from this memory
-system.physmem.bytes_read::total 54592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 37952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 37952 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 593 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 260 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 853 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 180968979 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 79345590 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 260314569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 180968979 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 180968979 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 180968979 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 79345590 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 260314569 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 45 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 209715500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 419431 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 113291 # Number of instructions committed
-system.cpu.committedOps 113291 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 8529 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls
-system.cpu.num_int_insts 113292 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 151096 # number of times the integer registers were read
-system.cpu.num_int_register_writes 76188 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 43493 # number of memory refs
-system.cpu.num_load_insts 23780 # Number of load instructions
-system.cpu.num_store_insts 19713 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 419431 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 25920 # Number of branches fetched
-system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction
-system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction
-system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction
-system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction
-system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction
-system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 113337 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 215.473039 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 43232 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 260 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 166.276923 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 215.473039 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.052606 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.052606 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 260 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.063477 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 87244 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 87244 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 23719 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23719 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19513 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19513 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 43232 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 43232 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 43232 # number of overall hits
-system.cpu.dcache.overall_hits::total 43232 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 260 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 260 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 260 # number of overall misses
-system.cpu.dcache.overall_misses::total 260 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3843000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 16380000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16380000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 16380000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16380000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23780 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23780 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 43492 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 43492 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 43492 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 43492 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002565 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002565 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010095 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010095 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005978 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005978 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005978 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005978 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 16120000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16120000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 16120000 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002565 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010095 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005978 # mshr miss rate for demand accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.005978 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 6 # number of replacements
-system.cpu.icache.tags.tagsinuse 302.746737 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 112745 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 593 # Sample count of references to valid blocks.
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-system.cpu.icache.tags.occ_blocks::cpu.inst 302.746737 # Average occupied blocks per requestor
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-system.cpu.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.286621 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 227269 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 227269 # Number of data accesses
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-system.cpu.icache.ReadReq_hits::total 112745 # number of ReadReq hits
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-system.cpu.icache.demand_hits::total 112745 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 112745 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 593 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 593 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 593 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 37359500 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 37359500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 37359500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 37359500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 113338 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 113338 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 113338 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 113338 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 113338 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 113338 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total 63000.843170 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 63000.843170 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 63000.843170 # average overall miss latency
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-system.cpu.icache.overall_mshr_misses::total 593 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 36766500 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total 36766500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36766500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36766500 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.843170 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.843170 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency
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-system.cpu.l2cache.tags.replacements 0 # number of replacements
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-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 304.845382 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.026031 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 7725 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 7725 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackClean_hits::writebacks 6 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 6 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 593 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 593 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses
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-system.cpu.l2cache.demand_misses::cpu.data 260 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 853 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 593 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 260 # number of overall misses
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+system.cpu.toL2Bus.trans_dist::ReadSharedReq 233
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1410
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 912
+system.cpu.toL2Bus.pkt_count::total 2322
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46208
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29184
+system.cpu.toL2Bus.pkt_size::total 75392
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 1144
+system.cpu.toL2Bus.snoop_fanout::mean 0
+system.cpu.toL2Bus.snoop_fanout::stdev 0
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1144 100.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 0
+system.cpu.toL2Bus.snoop_fanout::total 1144
+system.cpu.toL2Bus.reqLayer0.occupancy 623000
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 1032000
+system.cpu.toL2Bus.respLayer0.utilization 0.4
+system.cpu.toL2Bus.respLayer1.occupancy 684000
+system.cpu.toL2Bus.respLayer1.utilization 0.3
+system.membus.snoop_filter.tot_requests 1143
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 246972500
+system.membus.trans_dist::ReadResp 920
+system.membus.trans_dist::ReadExReq 223
+system.membus.trans_dist::ReadExResp 223
+system.membus.trans_dist::ReadSharedReq 920
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2286
+system.membus.pkt_count::total 2286
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73152
+system.membus.pkt_size::total 73152
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1143
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1143 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1143
+system.membus.reqLayer0.occupancy 1144500
+system.membus.reqLayer0.utilization 0.5
+system.membus.respLayer1.occupancy 5715000
+system.membus.respLayer1.utilization 2.3
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff