MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.

The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 3c8c9a9866a0d965844aed4669d1e260a5596b93..1cad7e4bebafb53c555345c39b518e1b90bcfd97 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -91,12 +91,6 @@ ISA::ISA()
     init();
 }
 
-ISA::ISA(BaseCPU *_cpu)
-{
-    cpu = _cpu;
-    init();
-}
-
 void
 ISA::init()
 {
@@ -173,11 +167,10 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
 //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
 void
 ISA::reset(std::string core_name, ThreadID num_threads,
-                   unsigned num_vpes, BaseCPU *_cpu)
+                   unsigned num_vpes, BaseCPU *cpu)
 {
     DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
             num_threads, num_vpes);
-    cpu = _cpu;
 
     MipsISA::CoreSpecific &cp = cpu->coreParams;
 
@@ -499,7 +492,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
 
     miscRegFile[misc_reg][reg_sel] = cp0_val;
 
-    scheduleCP0Update(1);
+    scheduleCP0Update(tc->getCpuPtr(), 1);
 }
 
 /**
@@ -528,7 +521,7 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
 }
 
 void
-ISA::scheduleCP0Update(int delay)
+ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
 {
     if (!cp0Updated) {
         cp0Updated = true;
@@ -540,7 +533,7 @@ ISA::scheduleCP0Update(int delay)
 }
 
 void
-ISA::updateCPU()
+ISA::updateCPU(BaseCPU *cpu)
 {
     ///////////////////////////////////////////////////////////////////
     //
@@ -578,7 +571,7 @@ ISA::CP0Event::process()
     switch (cp0EventType)
     {
       case UpdateCP0:
-        cp0->updateCPU();
+        cp0->updateCPU(cpu);
         break;
     }
 }

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 165adff83daa9913be5a498576bc802183ebbc7c..3f7afcdd0d6cb76352484c75071bc052a939a9c6 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -64,18 +64,15 @@ namespace MipsISA
         std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
         std::vector<BankType> bankType;
 
-        BaseCPU *cpu;
-
       public:
         ISA();
-        ISA(BaseCPU *_cpu);
 
         void init();
 
         void clear(unsigned tid_or_vpn = 0);
 
         void reset(std::string core_name, ThreadID num_threads,
-                   unsigned num_vpes, BaseCPU *_cpu);
+                   unsigned num_vpes, BaseCPU *cpu);
 
         void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
 
@@ -147,11 +144,11 @@ namespace MipsISA
         };
 
         // Schedule a CP0 Update Event
-        void scheduleCP0Update(int delay = 0);
+        void scheduleCP0Update(BaseCPU *cpu, int delay = 0);
 
         // If any changes have been made, then check the state for changes
         // and if necessary alert the CPU
-        void updateCPU();
+        void updateCPU(BaseCPU *cpu);
 
         // Keep a List of CPU Events that need to be deallocated
         std::queue<CP0Event*> cp0EventRemoveList;