Fix memtester to use functional access, fix cache to work functionally now that we...

src/cpu/memtest/memtest.cc:
    Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
    Fix cache to handle functional accesses properly based on memtester changes
    Still need to fix functional accesses in timing mode now that the memtester can test it.

--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 024cd7e41ed4ccb1718dbb557b7ae45aab7458ea..cb643e5d9c89c3fb50420035892e9bdb3cf47952 100644 (file)
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -72,8 +72,8 @@ void
 MemTest::CpuPort::recvFunctional(Packet *pkt)
 {
     //Do nothing if we see one come through
-    if (curTick != 0)//Supress warning durring initialization
-        warn("Functional Writes not implemented in MemTester\n");
+//    if (curTick != 0)//Supress warning durring initialization
+//        warn("Functional Writes not implemented in MemTester\n");
     //Need to find any response values that intersect and update
     return;
 }
@@ -345,8 +345,8 @@ MemTest::tick()
     } else {
         paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
     }
-    //bool probe = (random() % 2 == 1) && !req->isUncacheable();
-    bool probe = false;
+    bool probe = (random() % 2 == 1) && !(flags & UNCACHEABLE);
+    //bool probe = false;
 
     paddr &= ~((1 << access_size) - 1);
     req->setPhys(paddr, 1 << access_size, flags);
@@ -388,6 +388,7 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
+            pkt->makeAtomicResponse();
             completeRequest(pkt);
         } else {
 //         req->completionEvent = new MemCompleteEvent(req, result, this);
@@ -431,6 +432,7 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
+            pkt->makeAtomicResponse();
             completeRequest(pkt);
         } else {
 //         req->completionEvent = new MemCompleteEvent(req, NULL, this);

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index c4acc03e7b34f34f29366d4340b2dbc0fba3e16f..d8afcb00955101f37fb07eada0c3227e62bfd258 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -593,6 +593,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                     if (pkt->isWrite()) {
                         memcpy(pkt_data, write_data, data_size);
                     } else {
+                        pkt->flags |= SATISFIED;
+                        pkt->result = Packet::Success;
                         memcpy(write_data, pkt_data, data_size);
                     }
                 }
@@ -626,11 +628,19 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
                 if (pkt->isWrite()) {
                     memcpy(pkt_data, write_data, data_size);
                 } else {
+                    pkt->flags |= SATISFIED;
+                    pkt->result = Packet::Success;
                     memcpy(write_data, pkt_data, data_size);
                 }
 
             }
         }
+        if (pkt->isRead()
+            && pkt->result != Packet::Success
+            && otherSidePort == memSidePort) {
+            otherSidePort->sendFunctional(pkt);
+            assert(pkt->result == Packet::Success);
+        }
         return 0;
     } else if (!blk) {
         // update the cache state and statistics