lexer doesn't seem to return TOK_REG for logic anymore

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 08db36276cc123a91cb34f484e677ebb0e764844..ea0a09599cc154813904992b4e61bc78e39cf939 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1261,13 +1261,14 @@ enum_type: TOK_ENUM {
 
 enum_base_type: int_vec param_range
        | int_atom
-       | /* nothing */         { addRange(astbuf1); }
+       | /* nothing */         {astbuf1->is_reg = true; addRange(astbuf1); }
        ;
 
-int_atom: TOK_INTEGER          { addRange(astbuf1); }          // probably should do byte, range [7:0] here
+int_atom: TOK_INTEGER          {astbuf1->is_reg=true; addRange(astbuf1); }             // probably should do byte, range [7:0] here
        ;
 
-int_vec: TOK_REG               { astbuf1->is_reg = true; }     // lexer returns this for logic|bit too
+int_vec: TOK_REG {astbuf1->is_reg = true;}
+       | TOK_LOGIC  {astbuf1->is_logic = true;}
        ;
 
 enum_name_list: