add SIMD section

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index d5adea1c61d1843b4bee5fb90bd5c1689c3f106c..8dc72630b9584a7bb058c6ddfa26046545abf532 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1109,8 +1109,8 @@ with minimum disruption and effort.
   even an in-order single-issue implementation with a single ALU would still
   appear to have parallel vectoristion.
 * hard-to-judge: if actual inherent underlying ALU parallelism is added it's
-  hard to say if there would be pluses or minuses.  At worse it would
-  be "no worse" than existing register renaming, OoO, VLIW and register
+  hard to say if there would be pluses or minuses (on die area).  At worse it
+  would be "no worse" than existing register renaming, OoO, VLIW and register
   file cacheing schemes.
 
 ## RVV (as it stands, Draft 0.4 Section 17, RISC-V ISA V2.3-Draft)