Add test

diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 160c767fb873c77310cf5ff8d1765ad163ef5eab..7e928ec781b2376f1548c70409e7507d510c2376 100644 (file)
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -1,6 +1,5 @@
 read_verilog test_arith.v
 synth_ice40
-techmap -map ../cells_sim.v
 rename test gate
 
 read_verilog test_arith.v
@@ -8,3 +7,13 @@ rename test gold
 
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
+
+delete A:whitebox # Necessary since whiteboxes cannot
+                  # be overwritten...
+synth_ice40 -top gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter