aarch64: Add "c" constraint

Mirror arm in letting "c" match the condition code register.

	* config/aarch64/constraints.md (c): New constraint.

From-SVN: r278223

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c96683b1d1b739574ff3b9d6afe35beb06eecff2..ea547f7cf40748aea7e82eaf3c4df6e2bd04eb00 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2019-11-14  Richard Henderson  <richard.henderson@linaro.org>
+
+       * config/aarch64/constraints.md (c): New constraint.
+
 2019-11-14  Jan Hubicka  <hubicka@ucw.cz>
 
        * ipa-fnsummary.c (ipa_call_context::estimate_size_and_time,

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index d0c3dd5bc1f1b61457299b30241c02e3e101b608..b9e5d13e851912c2d5b27a2d0dbc764bde3fa36f 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -39,6 +39,10 @@
 (define_register_constraint "y" "FP_LO8_REGS"
   "Floating point and SIMD vector registers V0 - V7.")
 
+(define_constraint "c"
+ "@internal The condition code register."
+  (match_operand 0 "cc_register"))
+
 (define_constraint "I"
  "A constant that can be used with an ADD operation."
  (and (match_code "const_int")