machxo2: Improve FACADE_FF simulation model.
authorWilliam D. Jones <thor0505@comcast.net>
Sat, 21 Nov 2020 02:24:39 +0000 (21:24 -0500)
committerMarcelina Koƛcielnicka <mwk@0x04.net>
Tue, 23 Feb 2021 16:39:58 +0000 (17:39 +0100)
techlibs/machxo2/cells_sim.v

index 2c4d2f462735e5d935e2ed4181731183cf306ed3..8d93a4a33e119fa7b18e99374798ca6fa2ad64c5 100644 (file)
@@ -24,7 +24,8 @@ module FACADE_FF #(
        parameter LSRMUX = "LSR",
        parameter LSRONMUX = "LSRMUX",
        parameter SRMODE = "LSR_OVER_CE",
-       parameter REGSET = "SET"
+       parameter REGSET = "SET",
+       parameter REGMODE = "FF"
 ) (
        input CLK, DI, LSR, CE,
        output reg Q
@@ -41,22 +42,29 @@ module FACADE_FF #(
        endgenerate
 
        wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+       wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
        wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
        wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
        generate
-               if (SRMODE == "ASYNC") begin
-                       always @(posedge muxclk, posedge muxlsr)
-                               if (muxlsr)
-                                       Q <= srval;
-                               else if (muxce)
-                                       Q <= DI;
+               if (REGMODE == "FF") begin
+                       if (SRMODE == "ASYNC") begin
+                               always @(posedge muxclk, posedge muxlsron)
+                                       if (muxlsron)
+                                               Q <= srval;
+                                       else if (muxce)
+                                               Q <= DI;
+                       end else begin
+                               always @(posedge muxclk)
+                                       if (muxlsron)
+                                               Q <= srval;
+                                       else if (muxce)
+                                               Q <= DI;
+                       end
+               end else if (REGMODE == "LATCH") begin
+                       ERROR_UNSUPPORTED_FF_MODE error();
                end else begin
-                       always @(posedge muxclk)
-                               if (muxlsr)
-                                       Q <= srval;
-                               else if (muxce)
-                                       Q <= DI;
+                       ERROR_UNKNOWN_FF_MODE error();
                end
        endgenerate
 endmodule