Added RTLIL NEW_WIRE macro

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 6271aeef8313d21fe76b651a84bb6d438ebf66c9..5075215cd142a1981529a80625cee86f0d27a867 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -382,6 +382,15 @@ RTLIL::Module *RTLIL::Module::clone() const
        return new_mod;
 }
 
+RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name)
+{
+       RTLIL::Wire *wire = new RTLIL::Wire;
+       wire->width = width;
+       wire->name = name;
+       add(wire);
+       return wire;
+}
+
 void RTLIL::Module::add(RTLIL::Wire *wire)
 {
        assert(!wire->name.empty());

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7796ce96927392372a89317e8cf4a95cc0def4ad..a3d1dafd998140d44749d09d185c74deaf7f6d74 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -129,6 +129,9 @@ namespace RTLIL
 #define NEW_ID \
        RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
 
+#define NEW_WIRE(_mod, _width) \
+       (_mod)->new_wire(_width, NEW_ID)
+
        template <typename T> struct sort_by_name {
                bool operator()(T *a, T *b) const {
                        return a->name < b->name;
@@ -244,6 +247,7 @@ struct RTLIL::Module {
        virtual size_t count_id(RTLIL::IdString id);
        virtual void check();
        virtual void optimize();
+       RTLIL::SigSpec new_wire(int width, RTLIL::IdString name);
        void add(RTLIL::Wire *wire);
        void add(RTLIL::Cell *cell);
        void fixup_ports();