[AArch64] Fix g++.target/aarch64/sve/vcond_1_run.C

This had been failing since a mass renaming.  Noticed it a few times
before but somehow never got around to fixing it.

2019-10-31  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	* g++.target/aarch64/sve/vcond_1_run.C: Update test name.

From-SVN: r277683

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 93e26dee8bd3106b73c3018b177c641008c92baf..1830b4d691f176fa3dfe0d209b970fbc70a573d1 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-10-31  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * g++.target/aarch64/sve/vcond_1_run.C: Update test name.
+
 2019-10-31  Richard Sandiford  <richard.sandiford@arm.com>
 
        * gcc.target/aarch64/sve/vcond_4.c: Split parts out into...

diff --git a/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
index d01745e6864758ec6b0c880f5436052fed3b156b..2df33710d8fa89e7f0810dd8bf23551921c9d9b7 100644 (file)
--- a/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C
@@ -2,7 +2,7 @@
 /* { dg-options "-O" } */
 /* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */
 
-#include "sve_vcond_1.c"
+#include "vcond_1.C"
 
 #define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0]))