[(set_attr "op_type" "RS")
(set_attr "atype" "mem")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand:QI 1 "s_operand" "")
- (match_operand 2 "const_int_operand" "")
- (const_int 0)))]
- "!TARGET_64BIT && !reload_completed
+(define_insn_and_split "*extractqi"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
+ (match_operand 2 "const_int_operand" "n")
+ (const_int 0)))
+ (clobber (reg:CC 33))]
+ "!TARGET_64BIT
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
+ "#"
+ "&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], QImode, 0);
-}")
+}"
+ [(set_attr "type" "o2")
+ (set_attr "atype" "mem")])
-(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand:QI 1 "s_operand" "")
- (match_operand 2 "const_int_operand" "")
- (const_int 0)))]
- "!TARGET_64BIT && !reload_completed
+(define_insn_and_split "*extracthi"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
+ (match_operand 2 "const_int_operand" "n")
+ (const_int 0)))
+ (clobber (reg:CC 33))]
+ "!TARGET_64BIT
&& INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
+ "#"
+ "&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))])
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
operands[1] = change_address (operands[1], HImode, 0);
-}")
+}"
+ [(set_attr "type" "o2")
+ (set_attr "atype" "mem")])
;
; extendsidi2 instruction pattern(s).
"llgh\\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "atype" "mem")])
+
+(define_insn_and_split "*zero_extendhisi2_31"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
+ (clobber (reg:CC 33))]
+ "!TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (strict_low_part (match_dup 2)) (match_dup 1))
+ (clobber (reg:CC 33))])]
+ "operands[2] = gen_lowpart (HImode, operands[0]);"
+ [(set_attr "type" "o2")
+ (set_attr "atype" "mem")])
;
; zero_extendqisi2 instruction pattern(s).
"llgc\\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "atype" "mem")])
+
+(define_insn_and_split "*zero_extendqisi2_31"
+ [(set (match_operand:SI 0 "register_operand" "=&d")
+ (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+ "!TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (strict_low_part (match_dup 2)) (match_dup 1))]
+ "operands[2] = gen_lowpart (QImode, operands[0]);"
+ [(set_attr "type" "o2")
+ (set_attr "atype" "mem")])
;
; zero_extendqihi2 instruction pattern(s).
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))
- (clobber (reg:CC 33))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "atype" "mem")])
+(define_insn_and_split "*zero_extendqihi2_31"
+ [(set (match_operand:HI 0 "register_operand" "=&d")
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+ "!TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (set (strict_low_part (match_dup 2)) (match_dup 1))]
+ "operands[2] = gen_lowpart (QImode, operands[0]);"
+ [(set_attr "type" "o2")
+ (set_attr "atype" "mem")])
+
+
;
; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
;