arm.h (CLASS_LIKELY_SPILLED_P): Define.

	* arm.h (CLASS_LIKELY_SPILLED_P): Define.
testsuite
	* gcc.dg/spill-1.c: New test.

From-SVN: r80519

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 231b9e76e70816f38ed06ff2f6b93d45c9e756d9..dfda231368d4de4979790e9541a838751362f602 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2004-04-08  Paul Brook  <paul@codesourcery.com>
+
+       * arm.h (CLASS_LIKELY_SPILLED_P): Define.
+
 2004-04-08  Paul Brook  <paul@codesourcery.com>
 
        * explow.c (promote_mode): Use PROMOTE_FUNCTION_MODE instead of

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 0c3f2fe326ec7276cdd55c51079adacdea896307..8af53df8c8893501d369deb2b7a94b817cd474bf 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1378,6 +1378,13 @@ enum reg_class
      || reg_classes_intersect_p (VFP_REGS, (CLASS))    \
    : 0)
 
+/* We need to define this for LO_REGS on thumb.  Otherwise we can end up
+   using r0-r4 for function arguments, r7 for the stack frame and don't
+   have enough left over to do doubleword arithmetic.  */
+#define CLASS_LIKELY_SPILLED_P(CLASS)  \
+    ((TARGET_THUMB && (CLASS) == LO_REGS)      \
+     || (CLASS) == CC_REG)
+                                     
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS  (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
 #define BASE_REG_CLASS   (TARGET_THUMB ? LO_REGS : GENERAL_REGS)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d0aa28f22b9202776558fcd01ccb16f035b5d4a3..d714f2ef3d19fea272a842ef70536de220082d25 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2004-04-08  Paul Brook  <paul@codesourcery.com>
+
+       * gcc.dg/spill-1.c: New test.
+
 2004-04-08  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
        * gcc.dg/torture/builtin-ctype-2.c: New test.

diff --git a/gcc/testsuite/gcc.dg/spill-1.c b/gcc/testsuite/gcc.dg/spill-1.c
new file mode 100644 (file)
index 0000000..b85942e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/spill-1.c
@@ -0,0 +1,15 @@
+/* This caused an ICE during register spilling when targeting thumb.
+   There are 8 registers available for arithmetic operations (r0-r7)
+   r7 is the frame pointer, and r0-r3 are used to pass arguments.
+   Combine was extending the lives of the arguments (in r0-r3) up until the
+   call to z. This leaves only 3 regs free which isn't enough to preform the
+   doubleword addition.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+void z(int);
+int foo(int a, int b, int c, int d, long long *q) 
+{ 
+  *q=*q+1; 
+  z (a+b+c+d); 
+}
+