stats: Fix all stats usages to deal with template fixes

diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh
index aab96b15075b480cbde435e0db0eb266efa7266a..8372693098ecc53bc860b7e32142a6c9aec848d3 100644 (file)
--- a/src/arch/alpha/kernel_stats.hh
+++ b/src/arch/alpha/kernel_stats.hh
@@ -62,15 +62,15 @@ class Statistics : public ::Kernel::Statistics
     void changeMode(cpu_mode newmode, ThreadContext *tc);
 
   private:
-    Stats::Vector<> _callpal;
-//    Stats::Vector<> _faults;
+    Stats::Vector _callpal;
+//    Stats::Vector _faults;
 
-    Stats::Vector<> _mode;
-    Stats::Vector<> _modeGood;
+    Stats::Vector _mode;
+    Stats::Vector _modeGood;
     Stats::Formula _modeFraction;
-    Stats::Vector<> _modeTicks;
+    Stats::Vector _modeTicks;
 
-    Stats::Scalar<> _swap_context;
+    Stats::Scalar _swap_context;
 
   public:
     Statistics(System *system);

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 877533797ee581a2c66c7df84bb6b6f3bd342df3..6438895341fe913e049a9942927c79c9e8f76950 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -121,9 +121,9 @@ class TLB : public BaseTLB
 class ITB : public TLB
 {
   protected:
-    mutable Stats::Scalar<> hits;
-    mutable Stats::Scalar<> misses;
-    mutable Stats::Scalar<> acv;
+    mutable Stats::Scalar hits;
+    mutable Stats::Scalar misses;
+    mutable Stats::Scalar acv;
     mutable Stats::Formula accesses;
 
   public:
@@ -139,14 +139,14 @@ class ITB : public TLB
 class DTB : public TLB
 {
   protected:
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
     Stats::Formula acv;

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 1ab9d77e50616031d08a8b2fd9165833fd7f7052..dc0babf9ab2c0730c173b86852d8fa477c821ac5 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -96,14 +96,14 @@ class TLB : public BaseTLB
     void nextnlu() { if (++nlu >= size) nlu = 0; }
     MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
     Stats::Formula invalids;

diff --git a/src/base/hybrid_pred.hh b/src/base/hybrid_pred.hh
index cb1d6003b172b14af7d9526b3e8b99f5670e5103..5e478553b7920d20d2996b16d1b593e9c055e0ed 100644 (file)
--- a/src/base/hybrid_pred.hh
+++ b/src/base/hybrid_pred.hh
@@ -62,12 +62,12 @@ class HybridPredictor : public GenericPredictor
     //
     //  Stats
     //
-    Stats::Scalar<> pred_one; //num_one_preds
-    Stats::Scalar<> pred_zero; //num_zero_preds
-    Stats::Scalar<> correct_pred_one; //num_one_correct
-    Stats::Scalar<> correct_pred_zero; //num_zero_correct
-    Stats::Scalar<> record_one; //num_one_updates
-    Stats::Scalar<> record_zero; //num_zero_updates
+    Stats::Scalar pred_one; //num_one_preds
+    Stats::Scalar pred_zero; //num_zero_preds
+    Stats::Scalar correct_pred_one; //num_one_correct
+    Stats::Scalar correct_pred_zero; //num_zero_correct
+    Stats::Scalar record_one; //num_one_updates
+    Stats::Scalar record_zero; //num_zero_updates
 
     Stats::Formula total_preds;
     Stats::Formula frac_preds_zero;

diff --git a/src/base/sat_counter.hh b/src/base/sat_counter.hh
index 79de11156cbc29a518351b057089146e3f152474..38c4ec74f7a78318ae5b2f00740fe06b1cc1cd5b 100644 (file)
--- a/src/base/sat_counter.hh
+++ b/src/base/sat_counter.hh
@@ -64,13 +64,13 @@ class SaturatingCounterPred : public GenericPredictor
     unsigned *table;
 
     //  Statistics
-    Stats::Scalar<> predicted_one;      // Total predictions of one, preds_one
-    Stats::Scalar<> predicted_zero;     // Total predictions of zero, preds_zero
-    Stats::Scalar<> correct_pred_one;   // Total correct predictions of one, correct_one
-    Stats::Scalar<> correct_pred_zero;  // Total correct predictions of zero, correct_zero
+    Stats::Scalar predicted_one;      // Total predictions of one, preds_one
+    Stats::Scalar predicted_zero;     // Total predictions of zero, preds_zero
+    Stats::Scalar correct_pred_one;   // Total correct predictions of one, correct_one
+    Stats::Scalar correct_pred_zero;  // Total correct predictions of zero, correct_zero
 
-    Stats::Scalar<> record_zero;        //updates_zero
-    Stats::Scalar<> record_one;         //updates_one
+    Stats::Scalar record_zero;        //updates_zero
+    Stats::Scalar record_one;         //updates_one
 
     Stats::Formula preds_total;
     Stats::Formula pred_frac_zero;

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c8215e047cbfc978d5f419809c3e9c6f3c5634fe..8af3295eb945848814a58aab2bcbf9d97078d47a 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -304,7 +304,7 @@ class BaseCPU : public MemObject
 
   public:
     // Number of CPU cycles simulated
-    Stats::Scalar<> numCycles;
+    Stats::Scalar numCycles;
 };
 
 #endif // __CPU_BASE_HH__

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 36c90a0e9dc0610e74af2334c3c48e1a9f29ff41..adcd2801981891eb3b6884b67701a381216f137d 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -638,25 +638,25 @@ class InOrderCPU : public BaseCPU
     inline void tickThreadStats();
 
     /** Per-Thread Tick */
-    Stats::Vector<> threadCycles;
+    Stats::Vector threadCycles;
 
     /** Tick for SMT */
-    Stats::Scalar<> smtCycles;
+    Stats::Scalar smtCycles;
 
     /** Stat for total number of times the CPU is descheduled. */
-    Stats::Scalar<> timesIdled;
+    Stats::Scalar timesIdled;
 
     /** Stat for total number of cycles the CPU spends descheduled. */
-    Stats::Scalar<> idleCycles;
+    Stats::Scalar idleCycles;
 
     /** Stat for the number of committed instructions per thread. */
-    Stats::Vector<> committedInsts;
+    Stats::Vector committedInsts;
 
     /** Stat for the number of committed instructions per thread. */
-    Stats::Vector<> smtCommittedInsts;
+    Stats::Vector smtCommittedInsts;
 
     /** Stat for the total number of committed instructions. */
-    Stats::Scalar<> totalCommittedInsts;
+    Stats::Scalar totalCommittedInsts;
 
     /** Stat for the CPI per thread. */
     Stats::Formula cpi;

diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh
index 2fd8f2215fc95115b224ea309404e68567463281..b074639fb63af50834eed11df9babb8131797148 100644 (file)
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -340,19 +340,19 @@ class PipelineStage
 
     //@TODO: Use Stats for the pipeline stages
     /** Stat for total number of idle cycles. */
-    //Stats::Scalar<> stageIdleCycles;
+    //Stats::Scalar stageIdleCycles;
     /** Stat for total number of blocked cycles. */
-    //Stats::Scalar<> stageBlockedCycles;
+    //Stats::Scalar stageBlockedCycles;
     /** Stat for total number of normal running cycles. */
-    //Stats::Scalar<> stageRunCycles;
+    //Stats::Scalar stageRunCycles;
     /** Stat for total number of unblocking cycles. */
-    //Stats::Scalar<> stageUnblockCycles;
+    //Stats::Scalar stageUnblockCycles;
     /** Stat for total number of squashing cycles. */
-    //Stats::Scalar<> stageSquashCycles;
+    //Stats::Scalar stageSquashCycles;
     /** Stat for total number of staged instructions. */
-    //Stats::Scalar<> stageProcessedInsts;
+    //Stats::Scalar stageProcessedInsts;
     /** Stat for total number of squashed instructions. */
-    //Stats::Scalar<> stageSquashedInsts;
+    //Stats::Scalar stageSquashedInsts;
 };
 
 #endif

diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index 9b9e3c3dc69529c699f918f0d3796fd89b524509..b857e59ed5158b0677ebbbcaa007ba33c393a5fe 100644 (file)
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -232,7 +232,7 @@ class Resource {
     //
     /////////////////////////////////////////////////////////////////
     /** Number of Instruction Requests the Resource Processes */
-    Stats::Scalar<> instReqsProcessed;
+    Stats::Scalar instReqsProcessed;
 };
 
 class ResourceEvent : public Event

diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh
index b945922a738c75290360514c1db4c4468b89e2ba..bd68459d105776b9799e2d74078dee656f42dcab 100644 (file)
--- a/src/cpu/inorder/resources/bpred_unit.hh
+++ b/src/cpu/inorder/resources/bpred_unit.hh
@@ -238,21 +238,21 @@ class BPredUnit
     ReturnAddrStack RAS[ThePipeline::MaxThreads];
 
     /** Stat for number of BP lookups. */
-    Stats::Scalar<> lookups;
+    Stats::Scalar lookups;
     /** Stat for number of conditional branches predicted. */
-    Stats::Scalar<> condPredicted;
+    Stats::Scalar condPredicted;
     /** Stat for number of conditional branches predicted incorrectly. */
-    Stats::Scalar<> condIncorrect;
+    Stats::Scalar condIncorrect;
     /** Stat for number of BTB lookups. */
-    Stats::Scalar<> BTBLookups;
+    Stats::Scalar BTBLookups;
     /** Stat for number of BTB hits. */
-    Stats::Scalar<> BTBHits;
+    Stats::Scalar BTBHits;
     /** Stat for number of times the BTB is correct. */
-    Stats::Scalar<> BTBCorrect;
+    Stats::Scalar BTBCorrect;
     /** Stat for number of times the RAS is used to get a target. */
-    Stats::Scalar<> usedRAS;
+    Stats::Scalar usedRAS;
     /** Stat for number of times the RAS is incorrect. */
-    Stats::Scalar<> RASIncorrect;
+    Stats::Scalar RASIncorrect;
 };
 
 #endif // __CPU_INORDER_BPRED_UNIT_HH__

diff --git a/src/cpu/inorder/resources/branch_predictor.hh b/src/cpu/inorder/resources/branch_predictor.hh
index 57745343c7c157660ac216764669fa7952cf4d7a..47053910d289c5130844010cafcb42054a813bd2 100644 (file)
--- a/src/cpu/inorder/resources/branch_predictor.hh
+++ b/src/cpu/inorder/resources/branch_predictor.hh
@@ -78,8 +78,8 @@ class BranchPredictor : public Resource {
     // RESOURCE STATISTICS
     //
     /////////////////////////////////////////////////////////////////
-    Stats::Scalar<> predictedTaken;
-    Stats::Scalar<> predictedNotTaken;
+    Stats::Scalar predictedTaken;
+    Stats::Scalar predictedNotTaken;
 
 };
 

diff --git a/src/cpu/inorder/resources/execution_unit.hh b/src/cpu/inorder/resources/execution_unit.hh
index e969497a237d3edfa83e0ed89160243ab9433c64..46691bbf25e13c10a758953087353807409fa595 100644 (file)
--- a/src/cpu/inorder/resources/execution_unit.hh
+++ b/src/cpu/inorder/resources/execution_unit.hh
@@ -69,8 +69,8 @@ class ExecutionUnit : public Resource {
     // RESOURCE STATISTICS
     //
     /////////////////////////////////////////////////////////////////
-    Stats::Scalar<> predictedTakenIncorrect;
-    Stats::Scalar<> predictedNotTakenIncorrect;
+    Stats::Scalar predictedTakenIncorrect;
+    Stats::Scalar predictedNotTakenIncorrect;
 };
 
 

diff --git a/src/cpu/inorder/resources/inst_buffer.hh b/src/cpu/inorder/resources/inst_buffer.hh
index f4851e868e54eb88ed4bd4bbc56551d7bf4d3cc8..baadd42ffb48bb19eb3eb74d278aa9e30972d4f1 100644 (file)
--- a/src/cpu/inorder/resources/inst_buffer.hh
+++ b/src/cpu/inorder/resources/inst_buffer.hh
@@ -86,7 +86,7 @@ class InstBuffer : public Resource {
     //
     /////////////////////////////////////////////////////////////////
     /** Number of Instruction Requests the Resource Processes */
-    Stats::Scalar<> instsBypassed;
+    Stats::Scalar instsBypassed;
 
 };
 

diff --git a/src/cpu/inorder/resources/mult_div_unit.hh b/src/cpu/inorder/resources/mult_div_unit.hh
index 003f6fbb173f08f807233803401da7b94b00b6af..76180714c98efe21c1b52b05a44d76061b633a03 100644 (file)
--- a/src/cpu/inorder/resources/mult_div_unit.hh
+++ b/src/cpu/inorder/resources/mult_div_unit.hh
@@ -116,10 +116,10 @@ class MultDivUnit : public Resource {
     std::string lastInstName;
 
     /** Number of Instruction Requests the Resource Processes */
-    Stats::Scalar<> multInstReqsProcessed;
+    Stats::Scalar multInstReqsProcessed;
 
     /** Number of Instruction Requests the Resource Processes */
-    Stats::Scalar<> divInstReqsProcessed;
+    Stats::Scalar divInstReqsProcessed;
 
     MDUEvent *mduEvent;    
 };

diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 82438b41f13088eed335c0c4e367d2440470308e..907659f699e40366434dc1900056f5fad0ccdbd1 100644 (file)
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -171,9 +171,9 @@ class MemTest : public MemObject
 
     bool atomic;
 
-    Stats::Scalar<> numReadsStat;
-    Stats::Scalar<> numWritesStat;
-    Stats::Scalar<> numCopiesStat;
+    Stats::Scalar numReadsStat;
+    Stats::Scalar numWritesStat;
+    Stats::Scalar numCopiesStat;
 
     // called by MemCompleteEvent::process()
     void completeRequest(PacketPtr pkt);

diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 34fe7417833576525e0821e7ef9a70f412db2e12..44f9bea79726c69d207084ebb8bb795a9281839d 100644 (file)
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -237,21 +237,21 @@ class BPredUnit
     ReturnAddrStack RAS[Impl::MaxThreads];
 
     /** Stat for number of BP lookups. */
-    Stats::Scalar<> lookups;
+    Stats::Scalar lookups;
     /** Stat for number of conditional branches predicted. */
-    Stats::Scalar<> condPredicted;
+    Stats::Scalar condPredicted;
     /** Stat for number of conditional branches predicted incorrectly. */
-    Stats::Scalar<> condIncorrect;
+    Stats::Scalar condIncorrect;
     /** Stat for number of BTB lookups. */
-    Stats::Scalar<> BTBLookups;
+    Stats::Scalar BTBLookups;
     /** Stat for number of BTB hits. */
-    Stats::Scalar<> BTBHits;
+    Stats::Scalar BTBHits;
     /** Stat for number of times the BTB is correct. */
-    Stats::Scalar<> BTBCorrect;
+    Stats::Scalar BTBCorrect;
     /** Stat for number of times the RAS is used to get a target. */
-    Stats::Scalar<> usedRAS;
+    Stats::Scalar usedRAS;
     /** Stat for number of times the RAS is incorrect. */
-    Stats::Scalar<> RASIncorrect;
+    Stats::Scalar RASIncorrect;
 };
 
 #endif // __CPU_O3_BPRED_UNIT_HH__

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ff1e517f22476392d2fdde1426c660ca25f919fa..f21c145692d4faa9af69c70d468881f99a7de529 100644 (file)
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -452,40 +452,40 @@ class DefaultCommit
     void updateComInstStats(DynInstPtr &inst);
 
     /** Stat for the total number of committed instructions. */
-    Stats::Scalar<> commitCommittedInsts;
+    Stats::Scalar commitCommittedInsts;
     /** Stat for the total number of squashed instructions discarded by commit.
      */
-    Stats::Scalar<> commitSquashedInsts;
+    Stats::Scalar commitSquashedInsts;
     /** Stat for the total number of times commit is told to squash.
      * @todo: Actually increment this stat.
      */
-    Stats::Scalar<> commitSquashEvents;
+    Stats::Scalar commitSquashEvents;
     /** Stat for the total number of times commit has had to stall due to a non-
      * speculative instruction reaching the head of the ROB.
      */
-    Stats::Scalar<> commitNonSpecStalls;
+    Stats::Scalar commitNonSpecStalls;
     /** Stat for the total number of branch mispredicts that caused a squash. */
-    Stats::Scalar<> branchMispredicts;
+    Stats::Scalar branchMispredicts;
     /** Distribution of the number of committed instructions each cycle. */
-    Stats::Distribution<> numCommittedDist;
+    Stats::Distribution numCommittedDist;
 
     /** Total number of instructions committed. */
-    Stats::Vector<> statComInst;
+    Stats::Vector statComInst;
     /** Total number of software prefetches committed. */
-    Stats::Vector<> statComSwp;
+    Stats::Vector statComSwp;
     /** Stat for the total number of committed memory references. */
-    Stats::Vector<> statComRefs;
+    Stats::Vector statComRefs;
     /** Stat for the total number of committed loads. */
-    Stats::Vector<> statComLoads;
+    Stats::Vector statComLoads;
     /** Total number of committed memory barriers. */
-    Stats::Vector<> statComMembars;
+    Stats::Vector statComMembars;
     /** Total number of committed branches. */
-    Stats::Vector<> statComBranches;
+    Stats::Vector statComBranches;
 
     /** Number of cycles where the commit bandwidth limit is reached. */
-    Stats::Scalar<> commitEligibleSamples;
+    Stats::Scalar commitEligibleSamples;
     /** Number of instructions not committed due to bandwidth limits. */
-    Stats::Vector<> commitEligible;
+    Stats::Vector commitEligible;
 };
 
 #endif // __CPU_O3_COMMIT_HH__

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f4ed28e8ef19c6343d26e8397d7a6b318c095606..942970f5f6fa325259f50db25fbbcea104bb9111 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -755,13 +755,13 @@ class FullO3CPU : public BaseO3CPU
     bool lockFlag;
 
     /** Stat for total number of times the CPU is descheduled. */
-    Stats::Scalar<> timesIdled;
+    Stats::Scalar timesIdled;
     /** Stat for total number of cycles the CPU spends descheduled. */
-    Stats::Scalar<> idleCycles;
+    Stats::Scalar idleCycles;
     /** Stat for the number of committed instructions per thread. */
-    Stats::Vector<> committedInsts;
+    Stats::Vector committedInsts;
     /** Stat for the total number of committed instructions. */
-    Stats::Scalar<> totalCommittedInsts;
+    Stats::Scalar totalCommittedInsts;
     /** Stat for the CPI per thread. */
     Stats::Formula cpi;
     /** Stat for the total CPI. */

diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index dc8063f2994b3d38eeb80af7626b1a23f2ad5a49..294b5b623016f196740f2b362506066231656fae 100644 (file)
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -288,27 +288,27 @@ class DefaultDecode
 
 
     /** Stat for total number of idle cycles. */
-    Stats::Scalar<> decodeIdleCycles;
+    Stats::Scalar decodeIdleCycles;
     /** Stat for total number of blocked cycles. */
-    Stats::Scalar<> decodeBlockedCycles;
+    Stats::Scalar decodeBlockedCycles;
     /** Stat for total number of normal running cycles. */
-    Stats::Scalar<> decodeRunCycles;
+    Stats::Scalar decodeRunCycles;
     /** Stat for total number of unblocking cycles. */
-    Stats::Scalar<> decodeUnblockCycles;
+    Stats::Scalar decodeUnblockCycles;
     /** Stat for total number of squashing cycles. */
-    Stats::Scalar<> decodeSquashCycles;
+    Stats::Scalar decodeSquashCycles;
     /** Stat for number of times a branch is resolved at decode. */
-    Stats::Scalar<> decodeBranchResolved;
+    Stats::Scalar decodeBranchResolved;
     /** Stat for number of times a branch mispredict is detected. */
-    Stats::Scalar<> decodeBranchMispred;
+    Stats::Scalar decodeBranchMispred;
     /** Stat for number of times decode detected a non-control instruction
      * incorrectly predicted as a branch.
      */
-    Stats::Scalar<> decodeControlMispred;
+    Stats::Scalar decodeControlMispred;
     /** Stat for total number of decoded instructions. */
-    Stats::Scalar<> decodeDecodedInsts;
+    Stats::Scalar decodeDecodedInsts;
     /** Stat for total number of squashed instructions. */
-    Stats::Scalar<> decodeSquashedInsts;
+    Stats::Scalar decodeSquashedInsts;
 };
 
 #endif // __CPU_O3_DECODE_HH__

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 9886b667555afbcc760012fc63473e4de54f57e8..08ccb094b91de807ca98874f2c30293b5e3d7af1 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -448,33 +448,33 @@ class DefaultFetch
 
     // @todo: Consider making these vectors and tracking on a per thread basis.
     /** Stat for total number of cycles stalled due to an icache miss. */
-    Stats::Scalar<> icacheStallCycles;
+    Stats::Scalar icacheStallCycles;
     /** Stat for total number of fetched instructions. */
-    Stats::Scalar<> fetchedInsts;
+    Stats::Scalar fetchedInsts;
     /** Total number of fetched branches. */
-    Stats::Scalar<> fetchedBranches;
+    Stats::Scalar fetchedBranches;
     /** Stat for total number of predicted branches. */
-    Stats::Scalar<> predictedBranches;
+    Stats::Scalar predictedBranches;
     /** Stat for total number of cycles spent fetching. */
-    Stats::Scalar<> fetchCycles;
+    Stats::Scalar fetchCycles;
     /** Stat for total number of cycles spent squashing. */
-    Stats::Scalar<> fetchSquashCycles;
+    Stats::Scalar fetchSquashCycles;
     /** Stat for total number of cycles spent blocked due to other stages in
      * the pipeline.
      */
-    Stats::Scalar<> fetchIdleCycles;
+    Stats::Scalar fetchIdleCycles;
     /** Total number of cycles spent blocked. */
-    Stats::Scalar<> fetchBlockedCycles;
+    Stats::Scalar fetchBlockedCycles;
     /** Total number of cycles spent in any other state. */
-    Stats::Scalar<> fetchMiscStallCycles;
+    Stats::Scalar fetchMiscStallCycles;
     /** Stat for total number of fetched cache lines. */
-    Stats::Scalar<> fetchedCacheLines;
+    Stats::Scalar fetchedCacheLines;
     /** Total number of outstanding icache accesses that were dropped
      * due to a squash.
      */
-    Stats::Scalar<> fetchIcacheSquashes;
+    Stats::Scalar fetchIcacheSquashes;
     /** Distribution of number of instructions fetched each cycle. */
-    Stats::Distribution<> fetchNisnDist;
+    Stats::Distribution fetchNisnDist;
     /** Rate of how often fetch was idle. */
     Stats::Formula idleRate;
     /** Number of branch fetches per cycle. */

diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index bc60f401b87041fa81c58412e31ab09a5b1b8dde..3458f09d6ee260ed1d793032cd97393dabdb253a 100644 (file)
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -465,69 +465,69 @@ class DefaultIEW
     bool switchedOut;
 
     /** Stat for total number of idle cycles. */
-    Stats::Scalar<> iewIdleCycles;
+    Stats::Scalar iewIdleCycles;
     /** Stat for total number of squashing cycles. */
-    Stats::Scalar<> iewSquashCycles;
+    Stats::Scalar iewSquashCycles;
     /** Stat for total number of blocking cycles. */
-    Stats::Scalar<> iewBlockCycles;
+    Stats::Scalar iewBlockCycles;
     /** Stat for total number of unblocking cycles. */
-    Stats::Scalar<> iewUnblockCycles;
+    Stats::Scalar iewUnblockCycles;
     /** Stat for total number of instructions dispatched. */
-    Stats::Scalar<> iewDispatchedInsts;
+    Stats::Scalar iewDispatchedInsts;
     /** Stat for total number of squashed instructions dispatch skips. */
-    Stats::Scalar<> iewDispSquashedInsts;
+    Stats::Scalar iewDispSquashedInsts;
     /** Stat for total number of dispatched load instructions. */
-    Stats::Scalar<> iewDispLoadInsts;
+    Stats::Scalar iewDispLoadInsts;
     /** Stat for total number of dispatched store instructions. */
-    Stats::Scalar<> iewDispStoreInsts;
+    Stats::Scalar iewDispStoreInsts;
     /** Stat for total number of dispatched non speculative instructions. */
-    Stats::Scalar<> iewDispNonSpecInsts;
+    Stats::Scalar iewDispNonSpecInsts;
     /** Stat for number of times the IQ becomes full. */
-    Stats::Scalar<> iewIQFullEvents;
+    Stats::Scalar iewIQFullEvents;
     /** Stat for number of times the LSQ becomes full. */
-    Stats::Scalar<> iewLSQFullEvents;
+    Stats::Scalar iewLSQFullEvents;
     /** Stat for total number of memory ordering violation events. */
-    Stats::Scalar<> memOrderViolationEvents;
+    Stats::Scalar memOrderViolationEvents;
     /** Stat for total number of incorrect predicted taken branches. */
-    Stats::Scalar<> predictedTakenIncorrect;
+    Stats::Scalar predictedTakenIncorrect;
     /** Stat for total number of incorrect predicted not taken branches. */
-    Stats::Scalar<> predictedNotTakenIncorrect;
+    Stats::Scalar predictedNotTakenIncorrect;
     /** Stat for total number of mispredicted branches detected at execute. */
     Stats::Formula branchMispredicts;
 
     /** Stat for total number of executed instructions. */
-    Stats::Scalar<> iewExecutedInsts;
+    Stats::Scalar iewExecutedInsts;
     /** Stat for total number of executed load instructions. */
-    Stats::Vector<> iewExecLoadInsts;
+    Stats::Vector iewExecLoadInsts;
     /** Stat for total number of executed store instructions. */
-//    Stats::Scalar<> iewExecStoreInsts;
+//    Stats::Scalar iewExecStoreInsts;
     /** Stat for total number of squashed instructions skipped at execute. */
-    Stats::Scalar<> iewExecSquashedInsts;
+    Stats::Scalar iewExecSquashedInsts;
     /** Number of executed software prefetches. */
-    Stats::Vector<> iewExecutedSwp;
+    Stats::Vector iewExecutedSwp;
     /** Number of executed nops. */
-    Stats::Vector<> iewExecutedNop;
+    Stats::Vector iewExecutedNop;
     /** Number of executed meomory references. */
-    Stats::Vector<> iewExecutedRefs;
+    Stats::Vector iewExecutedRefs;
     /** Number of executed branches. */
-    Stats::Vector<> iewExecutedBranches;
+    Stats::Vector iewExecutedBranches;
     /** Number of executed store instructions. */
     Stats::Formula iewExecStoreInsts;
     /** Number of instructions executed per cycle. */
     Stats::Formula iewExecRate;
 
     /** Number of instructions sent to commit. */
-    Stats::Vector<> iewInstsToCommit;
+    Stats::Vector iewInstsToCommit;
     /** Number of instructions that writeback. */
-    Stats::Vector<> writebackCount;
+    Stats::Vector writebackCount;
     /** Number of instructions that wake consumers. */
-    Stats::Vector<> producerInst;
+    Stats::Vector producerInst;
     /** Number of instructions that wake up from producers. */
-    Stats::Vector<> consumerInst;
+    Stats::Vector consumerInst;
     /** Number of instructions that were delayed in writing back due
      * to resource contention.
      */
-    Stats::Vector<> wbPenalized;
+    Stats::Vector wbPenalized;
     /** Number of instructions per cycle written back. */
     Stats::Formula wbRate;
     /** Average number of woken instructions per writeback. */

diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 43da1565d14e510b328f6768026cea53769c97f4..0c3f44436bd3ef44467031701d634ba78208566c 100644 (file)
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -443,58 +443,58 @@ class InstructionQueue
     void dumpInsts();
 
     /** Stat for number of instructions added. */
-    Stats::Scalar<> iqInstsAdded;
+    Stats::Scalar iqInstsAdded;
     /** Stat for number of non-speculative instructions added. */
-    Stats::Scalar<> iqNonSpecInstsAdded;
+    Stats::Scalar iqNonSpecInstsAdded;
 
-    Stats::Scalar<> iqInstsIssued;
+    Stats::Scalar iqInstsIssued;
     /** Stat for number of integer instructions issued. */
-    Stats::Scalar<> iqIntInstsIssued;
+    Stats::Scalar iqIntInstsIssued;
     /** Stat for number of floating point instructions issued. */
-    Stats::Scalar<> iqFloatInstsIssued;
+    Stats::Scalar iqFloatInstsIssued;
     /** Stat for number of branch instructions issued. */
-    Stats::Scalar<> iqBranchInstsIssued;
+    Stats::Scalar iqBranchInstsIssued;
     /** Stat for number of memory instructions issued. */
-    Stats::Scalar<> iqMemInstsIssued;
+    Stats::Scalar iqMemInstsIssued;
     /** Stat for number of miscellaneous instructions issued. */
-    Stats::Scalar<> iqMiscInstsIssued;
+    Stats::Scalar iqMiscInstsIssued;
     /** Stat for number of squashed instructions that were ready to issue. */
-    Stats::Scalar<> iqSquashedInstsIssued;
+    Stats::Scalar iqSquashedInstsIssued;
     /** Stat for number of squashed instructions examined when squashing. */
-    Stats::Scalar<> iqSquashedInstsExamined;
+    Stats::Scalar iqSquashedInstsExamined;
     /** Stat for number of squashed instruction operands examined when
      * squashing.
      */
-    Stats::Scalar<> iqSquashedOperandsExamined;
+    Stats::Scalar iqSquashedOperandsExamined;
     /** Stat for number of non-speculative instructions removed due to a squash.
      */
-    Stats::Scalar<> iqSquashedNonSpecRemoved;
+    Stats::Scalar iqSquashedNonSpecRemoved;
     // Also include number of instructions rescheduled and replayed.
 
     /** Distribution of number of instructions in the queue.
      * @todo: Need to create struct to track the entry time for each
      * instruction. */
-//    Stats::VectorDistribution<> queueResDist;
+//    Stats::VectorDistribution queueResDist;
     /** Distribution of the number of instructions issued. */
-    Stats::Distribution<> numIssuedDist;
+    Stats::Distribution numIssuedDist;
     /** Distribution of the cycles it takes to issue an instruction.
      * @todo: Need to create struct to track the ready time for each
      * instruction. */
-//    Stats::VectorDistribution<> issueDelayDist;
+//    Stats::VectorDistribution issueDelayDist;
 
     /** Number of times an instruction could not be issued because a
      * FU was busy.
      */
-    Stats::Vector<> statFuBusy;
-//    Stats::Vector<> dist_unissued;
+    Stats::Vector statFuBusy;
+//    Stats::Vector dist_unissued;
     /** Stat for total number issued for each instruction type. */
-    Stats::Vector2d<> statIssuedInstType;
+    Stats::Vector2d statIssuedInstType;
 
     /** Number of instructions issued per cycle. */
     Stats::Formula issueRate;
 
     /** Number of times the FU was busy. */
-    Stats::Vector<> fuBusy;
+    Stats::Vector fuBusy;
     /** Number of times the FU was busy per instruction issued. */
     Stats::Formula fuBusyRate;
 };

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 8af8f18e6fa1958fd934b9ab8147f428ceeb110b..5323e3a472319f1a1a19b09dc418364a165bff5d 100644 (file)
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -409,35 +409,35 @@ class LSQUnit {
     // of that in stage that is one level up, and only call executeLoad/Store
     // the appropriate number of times.
     /** Total number of loads forwaded from LSQ stores. */
-    Stats::Scalar<> lsqForwLoads;
+    Stats::Scalar lsqForwLoads;
 
     /** Total number of loads ignored due to invalid addresses. */
-    Stats::Scalar<> invAddrLoads;
+    Stats::Scalar invAddrLoads;
 
     /** Total number of squashed loads. */
-    Stats::Scalar<> lsqSquashedLoads;
+    Stats::Scalar lsqSquashedLoads;
 
     /** Total number of responses from the memory system that are
      * ignored due to the instruction already being squashed. */
-    Stats::Scalar<> lsqIgnoredResponses;
+    Stats::Scalar lsqIgnoredResponses;
 
     /** Tota number of memory ordering violations. */
-    Stats::Scalar<> lsqMemOrderViolation;
+    Stats::Scalar lsqMemOrderViolation;
 
     /** Total number of squashed stores. */
-    Stats::Scalar<> lsqSquashedStores;
+    Stats::Scalar lsqSquashedStores;
 
     /** Total number of software prefetches ignored due to invalid addresses. */
-    Stats::Scalar<> invAddrSwpfs;
+    Stats::Scalar invAddrSwpfs;
 
     /** Ready loads blocked due to partial store-forwarding. */
-    Stats::Scalar<> lsqBlockedLoads;
+    Stats::Scalar lsqBlockedLoads;
 
     /** Number of loads that were rescheduled. */
-    Stats::Scalar<> lsqRescheduledLoads;
+    Stats::Scalar lsqRescheduledLoads;
 
     /** Number of times the LSQ is blocked due to the cache. */
-    Stats::Scalar<> lsqCacheBlocked;
+    Stats::Scalar lsqCacheBlocked;
 
   public:
     /** Executes the load at the given index. */

diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index 4f66b459951801e31d8d12940e6dad5122712607..fa1c333207dc5f5206bb4a57df1ece9c19f520ea 100644 (file)
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -253,13 +253,13 @@ class MemDepUnit {
     int id;
 
     /** Stat for number of inserted loads. */
-    Stats::Scalar<> insertedLoads;
+    Stats::Scalar insertedLoads;
     /** Stat for number of inserted stores. */
-    Stats::Scalar<> insertedStores;
+    Stats::Scalar insertedStores;
     /** Stat for number of conflicting loads that had to wait for a store. */
-    Stats::Scalar<> conflictingLoads;
+    Stats::Scalar conflictingLoads;
     /** Stat for number of conflicting stores that had to wait for a store. */
-    Stats::Scalar<> conflictingStores;
+    Stats::Scalar conflictingStores;
 };
 
 #endif // __CPU_O3_MEM_DEP_UNIT_HH__

diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index c9e0d418dee36880eb646b2680c2a7644c045d8b..0fdf28b19667d3dcce0b38e20c80c98f6bb69706 100644 (file)
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -441,44 +441,44 @@ class DefaultRename
     inline void incrFullStat(const FullSource &source);
 
     /** Stat for total number of cycles spent squashing. */
-    Stats::Scalar<> renameSquashCycles;
+    Stats::Scalar renameSquashCycles;
     /** Stat for total number of cycles spent idle. */
-    Stats::Scalar<> renameIdleCycles;
+    Stats::Scalar renameIdleCycles;
     /** Stat for total number of cycles spent blocking. */
-    Stats::Scalar<> renameBlockCycles;
+    Stats::Scalar renameBlockCycles;
     /** Stat for total number of cycles spent stalling for a serializing inst. */
-    Stats::Scalar<> renameSerializeStallCycles;
+    Stats::Scalar renameSerializeStallCycles;
     /** Stat for total number of cycles spent running normally. */
-    Stats::Scalar<> renameRunCycles;
+    Stats::Scalar renameRunCycles;
     /** Stat for total number of cycles spent unblocking. */
-    Stats::Scalar<> renameUnblockCycles;
+    Stats::Scalar renameUnblockCycles;
     /** Stat for total number of renamed instructions. */
-    Stats::Scalar<> renameRenamedInsts;
+    Stats::Scalar renameRenamedInsts;
     /** Stat for total number of squashed instructions that rename discards. */
-    Stats::Scalar<> renameSquashedInsts;
+    Stats::Scalar renameSquashedInsts;
     /** Stat for total number of times that the ROB starts a stall in rename. */
-    Stats::Scalar<> renameROBFullEvents;
+    Stats::Scalar renameROBFullEvents;
     /** Stat for total number of times that the IQ starts a stall in rename. */
-    Stats::Scalar<> renameIQFullEvents;
+    Stats::Scalar renameIQFullEvents;
     /** Stat for total number of times that the LSQ starts a stall in rename. */
-    Stats::Scalar<> renameLSQFullEvents;
+    Stats::Scalar renameLSQFullEvents;
     /** Stat for total number of times that rename runs out of free registers
      * to use to rename. */
-    Stats::Scalar<> renameFullRegistersEvents;
+    Stats::Scalar renameFullRegistersEvents;
     /** Stat for total number of renamed destination registers. */
-    Stats::Scalar<> renameRenamedOperands;
+    Stats::Scalar renameRenamedOperands;
     /** Stat for total number of source register rename lookups. */
-    Stats::Scalar<> renameRenameLookups;
+    Stats::Scalar renameRenameLookups;
     /** Stat for total number of committed renaming mappings. */
-    Stats::Scalar<> renameCommittedMaps;
+    Stats::Scalar renameCommittedMaps;
     /** Stat for total number of mappings that were undone due to a squash. */
-    Stats::Scalar<> renameUndoneMaps;
+    Stats::Scalar renameUndoneMaps;
     /** Number of serialize instructions handled. */
-    Stats::Scalar<> renamedSerializing;
+    Stats::Scalar renamedSerializing;
     /** Number of instructions marked as temporarily serializing. */
-    Stats::Scalar<> renamedTempSerializing;
+    Stats::Scalar renamedTempSerializing;
     /** Number of instructions inserted into skid buffers. */
-    Stats::Scalar<> renameSkidInsts;
+    Stats::Scalar renameSkidInsts;
 };
 
 #endif // __CPU_O3_RENAME_HH__

diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh
index 84429f3c1b10ebfe4d0d5cb5f6b4923ad8951166..ca858ce2e6c9efe96f98748e6ab114e98595e9a5 100644 (file)
--- a/src/cpu/ozone/back_end.hh
+++ b/src/cpu/ozone/back_end.hh
@@ -157,13 +157,13 @@ class BackEnd
         int numInsts;
         int width;
 
-        Stats::VectorDistribution<> occ_dist;
+        Stats::VectorDistribution occ_dist;
 
-        Stats::Vector<> inst_count;
-        Stats::Vector<> peak_inst_count;
-        Stats::Scalar<> empty_count;
-        Stats::Scalar<> current_count;
-        Stats::Scalar<> fullCount;
+        Stats::Vector inst_count;
+        Stats::Vector peak_inst_count;
+        Stats::Scalar empty_count;
+        Stats::Scalar current_count;
+        Stats::Scalar fullCount;
 
         Stats::Formula occ_rate;
         Stats::Formula avg_residency;
@@ -371,45 +371,45 @@ class BackEnd
     bool fetchRedirect[Impl::MaxThreads];
 
     // number of cycles stalled for D-cache misses
-/*    Stats::Scalar<> dcacheStallCycles;
+/*    Stats::Scalar dcacheStallCycles;
       Counter lastDcacheStall;
 */
-    Stats::Vector<> rob_cap_events;
-    Stats::Vector<> rob_cap_inst_count;
-    Stats::Vector<> iq_cap_events;
-    Stats::Vector<> iq_cap_inst_count;
+    Stats::Vector rob_cap_events;
+    Stats::Vector rob_cap_inst_count;
+    Stats::Vector iq_cap_events;
+    Stats::Vector iq_cap_inst_count;
     // total number of instructions executed
-    Stats::Vector<> exe_inst;
-    Stats::Vector<> exe_swp;
-    Stats::Vector<> exe_nop;
-    Stats::Vector<> exe_refs;
-    Stats::Vector<> exe_loads;
-    Stats::Vector<> exe_branches;
+    Stats::Vector exe_inst;
+    Stats::Vector exe_swp;
+    Stats::Vector exe_nop;
+    Stats::Vector exe_refs;
+    Stats::Vector exe_loads;
+    Stats::Vector exe_branches;
 
-    Stats::Vector<> issued_ops;
+    Stats::Vector issued_ops;
 
     // total number of loads forwaded from LSQ stores
-    Stats::Vector<> lsq_forw_loads;
+    Stats::Vector lsq_forw_loads;
 
     // total number of loads ignored due to invalid addresses
-    Stats::Vector<> inv_addr_loads;
+    Stats::Vector inv_addr_loads;
 
     // total number of software prefetches ignored due to invalid addresses
-    Stats::Vector<> inv_addr_swpfs;
+    Stats::Vector inv_addr_swpfs;
     // ready loads blocked due to memory disambiguation
-    Stats::Vector<> lsq_blocked_loads;
+    Stats::Vector lsq_blocked_loads;
 
-    Stats::Scalar<> lsqInversion;
+    Stats::Scalar lsqInversion;
 
-    Stats::Vector<> n_issued_dist;
-    Stats::VectorDistribution<> issue_delay_dist;
+    Stats::Vector n_issued_dist;
+    Stats::VectorDistribution issue_delay_dist;
 
-    Stats::VectorDistribution<> queue_res_dist;
+    Stats::VectorDistribution queue_res_dist;
 /*
-    Stats::Vector<> stat_fu_busy;
-    Stats::Vector2d<> stat_fuBusy;
-    Stats::Vector<> dist_unissued;
-    Stats::Vector2d<> stat_issued_inst_type;
+    Stats::Vector stat_fu_busy;
+    Stats::Vector2d stat_fuBusy;
+    Stats::Vector dist_unissued;
+    Stats::Vector2d stat_issued_inst_type;
 
     Stats::Formula misspec_cnt;
     Stats::Formula misspec_ipc;
@@ -422,34 +422,34 @@ class BackEnd
     Stats::Formula commit_ipb;
     Stats::Formula lsq_inv_rate;
 */
-    Stats::Vector<> writeback_count;
-    Stats::Vector<> producer_inst;
-    Stats::Vector<> consumer_inst;
-    Stats::Vector<> wb_penalized;
+    Stats::Vector writeback_count;
+    Stats::Vector producer_inst;
+    Stats::Vector consumer_inst;
+    Stats::Vector wb_penalized;
 
     Stats::Formula wb_rate;
     Stats::Formula wb_fanout;
     Stats::Formula wb_penalized_rate;
 
     // total number of instructions committed
-    Stats::Vector<> stat_com_inst;
-    Stats::Vector<> stat_com_swp;
-    Stats::Vector<> stat_com_refs;
-    Stats::Vector<> stat_com_loads;
-    Stats::Vector<> stat_com_membars;
-    Stats::Vector<> stat_com_branches;
+    Stats::Vector stat_com_inst;
+    Stats::Vector stat_com_swp;
+    Stats::Vector stat_com_refs;
+    Stats::Vector stat_com_loads;
+    Stats::Vector stat_com_membars;
+    Stats::Vector stat_com_branches;
 
-    Stats::Distribution<> n_committed_dist;
+    Stats::Distribution n_committed_dist;
 
-    Stats::Scalar<> commit_eligible_samples;
-    Stats::Vector<> commit_eligible;
+    Stats::Scalar commit_eligible_samples;
+    Stats::Vector commit_eligible;
 
-    Stats::Scalar<> ROB_fcount;
+    Stats::Scalar ROB_fcount;
     Stats::Formula ROB_full_rate;
 
-    Stats::Vector<>  ROB_count;  // cumulative ROB occupancy
+    Stats::Vector  ROB_count;  // cumulative ROB occupancy
     Stats::Formula ROB_occ_rate;
-    Stats::VectorDistribution<> ROB_occ_dist;
+    Stats::VectorDistribution ROB_occ_dist;
   public:
     void dumpInsts();
 };

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 054fc1aa1666d8ef249ca2d5d045a1fe1b07d315..0bfb4bfa9d02506f1d13eba955aaaac966e88504 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -390,7 +390,7 @@ class OzoneCPU : public BaseCPU
     Counter startNumLoad;
 
     // number of idle cycles
-    Stats::Average<> notIdleFraction;
+    Stats::Average notIdleFraction;
     Stats::Formula idleFraction;
 
   public:
@@ -473,7 +473,7 @@ class OzoneCPU : public BaseCPU
 
     bool lockFlag;
 
-    Stats::Scalar<> quiesceCycles;
+    Stats::Scalar quiesceCycles;
 
     Checker<DynInstPtr> *checker;
 };

diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index fac2434491619e567657f6fd1a7dcc47103dc0f5..38fc89e3fecdb46b9a39f4f8b02395aee94fa7ba 100644 (file)
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -275,48 +275,48 @@ class FrontEnd
   private:
     // number of idle cycles
 /*
-    Stats::Average<> notIdleFraction;
+    Stats::Average notIdleFraction;
     Stats::Formula idleFraction;
 */
     // @todo: Consider making these vectors and tracking on a per thread basis.
     /** Stat for total number of cycles stalled due to an icache miss. */
-    Stats::Scalar<> icacheStallCycles;
+    Stats::Scalar icacheStallCycles;
     /** Stat for total number of fetched instructions. */
-    Stats::Scalar<> fetchedInsts;
-    Stats::Scalar<> fetchedBranches;
+    Stats::Scalar fetchedInsts;
+    Stats::Scalar fetchedBranches;
     /** Stat for total number of predicted branches. */
-    Stats::Scalar<> predictedBranches;
+    Stats::Scalar predictedBranches;
     /** Stat for total number of cycles spent fetching. */
-    Stats::Scalar<> fetchCycles;
+    Stats::Scalar fetchCycles;
 
-    Stats::Scalar<> fetchIdleCycles;
+    Stats::Scalar fetchIdleCycles;
     /** Stat for total number of cycles spent squashing. */
-    Stats::Scalar<> fetchSquashCycles;
+    Stats::Scalar fetchSquashCycles;
     /** Stat for total number of cycles spent blocked due to other stages in
      * the pipeline.
      */
-    Stats::Scalar<> fetchBlockedCycles;
+    Stats::Scalar fetchBlockedCycles;
     /** Stat for total number of fetched cache lines. */
-    Stats::Scalar<> fetchedCacheLines;
+    Stats::Scalar fetchedCacheLines;
 
-    Stats::Scalar<> fetchIcacheSquashes;
+    Stats::Scalar fetchIcacheSquashes;
     /** Distribution of number of instructions fetched each cycle. */
-    Stats::Distribution<> fetchNisnDist;
-//    Stats::Vector<> qfull_iq_occupancy;
-//    Stats::VectorDistribution<> qfull_iq_occ_dist_;
+    Stats::Distribution fetchNisnDist;
+//    Stats::Vector qfull_iq_occupancy;
+//    Stats::VectorDistribution qfull_iq_occ_dist_;
     Stats::Formula idleRate;
     Stats::Formula branchRate;
     Stats::Formula fetchRate;
-    Stats::Scalar<> IFQCount;   // cumulative IFQ occupancy
+    Stats::Scalar IFQCount;   // cumulative IFQ occupancy
     Stats::Formula IFQOccupancy;
     Stats::Formula IFQLatency;
-    Stats::Scalar<> IFQFcount; // cumulative IFQ full count
+    Stats::Scalar IFQFcount; // cumulative IFQ full count
     Stats::Formula IFQFullRate;
 
-    Stats::Scalar<> dispatchCountStat;
-    Stats::Scalar<> dispatchedSerializing;
-    Stats::Scalar<> dispatchedTempSerializing;
-    Stats::Scalar<> dispatchSerializeStallCycles;
+    Stats::Scalar dispatchCountStat;
+    Stats::Scalar dispatchedSerializing;
+    Stats::Scalar dispatchedTempSerializing;
+    Stats::Scalar dispatchSerializeStallCycles;
     Stats::Formula dispatchRate;
     Stats::Formula regIntFull;
     Stats::Formula regFpFull;

diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 0840591e02cf4db0aab5ba275f8965eedaa75ef7..e930144be8dfa6d1388309520d155865f3e6613c 100644 (file)
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -192,7 +192,7 @@ class InorderBackEnd
 
     TimeBuffer<CommStruct> *comm;
     // number of cycles stalled for D-cache misses
-    Stats::Scalar<> dcacheStallCycles;
+    Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 };
 

diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh
index a11d5204bc060b4904e98466474db9db12d1a5bc..e840d5c21b0a5e344b0631f238cf876d591ade0e 100644 (file)
--- a/src/cpu/ozone/inst_queue.hh
+++ b/src/cpu/ozone/inst_queue.hh
@@ -473,35 +473,35 @@ class InstQueue
     void dumpInsts();
 
     /** Stat for number of instructions added. */
-    Stats::Scalar<> iqInstsAdded;
+    Stats::Scalar iqInstsAdded;
     /** Stat for number of non-speculative instructions added. */
-    Stats::Scalar<> iqNonSpecInstsAdded;
-//    Stats::Scalar<> iqIntInstsAdded;
+    Stats::Scalar iqNonSpecInstsAdded;
+//    Stats::Scalar iqIntInstsAdded;
     /** Stat for number of integer instructions issued. */
-    Stats::Scalar<> iqIntInstsIssued;
-//    Stats::Scalar<> iqFloatInstsAdded;
+    Stats::Scalar iqIntInstsIssued;
+//    Stats::Scalar iqFloatInstsAdded;
     /** Stat for number of floating point instructions issued. */
-    Stats::Scalar<> iqFloatInstsIssued;
-//    Stats::Scalar<> iqBranchInstsAdded;
+    Stats::Scalar iqFloatInstsIssued;
+//    Stats::Scalar iqBranchInstsAdded;
     /** Stat for number of branch instructions issued. */
-    Stats::Scalar<> iqBranchInstsIssued;
-//    Stats::Scalar<> iqMemInstsAdded;
+    Stats::Scalar iqBranchInstsIssued;
+//    Stats::Scalar iqMemInstsAdded;
     /** Stat for number of memory instructions issued. */
-    Stats::Scalar<> iqMemInstsIssued;
-//    Stats::Scalar<> iqMiscInstsAdded;
+    Stats::Scalar iqMemInstsIssued;
+//    Stats::Scalar iqMiscInstsAdded;
     /** Stat for number of miscellaneous instructions issued. */
-    Stats::Scalar<> iqMiscInstsIssued;
+    Stats::Scalar iqMiscInstsIssued;
     /** Stat for number of squashed instructions that were ready to issue. */
-    Stats::Scalar<> iqSquashedInstsIssued;
+    Stats::Scalar iqSquashedInstsIssued;
     /** Stat for number of squashed instructions examined when squashing. */
-    Stats::Scalar<> iqSquashedInstsExamined;
+    Stats::Scalar iqSquashedInstsExamined;
     /** Stat for number of squashed instruction operands examined when
      * squashing.
      */
-    Stats::Scalar<> iqSquashedOperandsExamined;
+    Stats::Scalar iqSquashedOperandsExamined;
     /** Stat for number of non-speculative instructions removed due to a squash.
      */
-    Stats::Scalar<> iqSquashedNonSpecRemoved;
+    Stats::Scalar iqSquashedNonSpecRemoved;
 
 };
 

diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 981682c2658f020dfb8e2686a8c61d31e5ea1366..47be245e5e5324a692eaeb23a8c4063fed94a58a 100644 (file)
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -331,7 +331,7 @@ class OzoneLSQ {
 
     //list<InstSeqNum> mshrSeqNums;
 
-     //Stats::Scalar<> dcacheStallCycles;
+     //Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 
     /** Wire to read information from the issue stage time queue. */

diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh
index 8ab50d5c901ce12eb127b16cdd6c3e64791549d0..4a1657c9b131d2e4dc5c791d855c85935442704b 100644 (file)
--- a/src/cpu/ozone/lw_back_end.hh
+++ b/src/cpu/ozone/lw_back_end.hh
@@ -326,47 +326,47 @@ class LWBackEnd
     bool exactFullStall;
 
     // number of cycles stalled for D-cache misses
-/*    Stats::Scalar<> dcacheStallCycles;
+/*    Stats::Scalar dcacheStallCycles;
       Counter lastDcacheStall;
 */
-    Stats::Vector<> robCapEvents;
-    Stats::Vector<> robCapInstCount;
-    Stats::Vector<> iqCapEvents;
-    Stats::Vector<> iqCapInstCount;
+    Stats::Vector robCapEvents;
+    Stats::Vector robCapInstCount;
+    Stats::Vector iqCapEvents;
+    Stats::Vector iqCapInstCount;
     // total number of instructions executed
-    Stats::Vector<> exeInst;
-    Stats::Vector<> exeSwp;
-    Stats::Vector<> exeNop;
-    Stats::Vector<> exeRefs;
-    Stats::Vector<> exeLoads;
-    Stats::Vector<> exeBranches;
+    Stats::Vector exeInst;
+    Stats::Vector exeSwp;
+    Stats::Vector exeNop;
+    Stats::Vector exeRefs;
+    Stats::Vector exeLoads;
+    Stats::Vector exeBranches;
 
-    Stats::Vector<> issuedOps;
+    Stats::Vector issuedOps;
 
     // total number of loads forwaded from LSQ stores
-    Stats::Vector<> lsqForwLoads;
+    Stats::Vector lsqForwLoads;
 
     // total number of loads ignored due to invalid addresses
-    Stats::Vector<> invAddrLoads;
+    Stats::Vector invAddrLoads;
 
     // total number of software prefetches ignored due to invalid addresses
-    Stats::Vector<> invAddrSwpfs;
+    Stats::Vector invAddrSwpfs;
     // ready loads blocked due to memory disambiguation
-    Stats::Vector<> lsqBlockedLoads;
+    Stats::Vector lsqBlockedLoads;
 
-    Stats::Scalar<> lsqInversion;
+    Stats::Scalar lsqInversion;
 
-    Stats::Vector<> nIssuedDist;
+    Stats::Vector nIssuedDist;
 /*
-    Stats::VectorDistribution<> issueDelayDist;
+    Stats::VectorDistribution issueDelayDist;
 
-    Stats::VectorDistribution<> queueResDist;
+    Stats::VectorDistribution queueResDist;
 */
 /*
-    Stats::Vector<> stat_fu_busy;
-    Stats::Vector2d<> stat_fuBusy;
-    Stats::Vector<> dist_unissued;
-    Stats::Vector2d<> stat_issued_inst_type;
+    Stats::Vector stat_fu_busy;
+    Stats::Vector2d stat_fuBusy;
+    Stats::Vector dist_unissued;
+    Stats::Vector2d stat_issued_inst_type;
 
     Stats::Formula misspec_cnt;
     Stats::Formula misspec_ipc;
@@ -379,37 +379,37 @@ class LWBackEnd
     Stats::Formula commit_ipb;
     Stats::Formula lsq_inv_rate;
 */
-    Stats::Vector<> writebackCount;
-    Stats::Vector<> producerInst;
-    Stats::Vector<> consumerInst;
-    Stats::Vector<> wbPenalized;
+    Stats::Vector writebackCount;
+    Stats::Vector producerInst;
+    Stats::Vector consumerInst;
+    Stats::Vector wbPenalized;
 
     Stats::Formula wbRate;
     Stats::Formula wbFanout;
     Stats::Formula wbPenalizedRate;
 
     // total number of instructions committed
-    Stats::Vector<> statComInst;
-    Stats::Vector<> statComSwp;
-    Stats::Vector<> statComRefs;
-    Stats::Vector<> statComLoads;
-    Stats::Vector<> statComMembars;
-    Stats::Vector<> statComBranches;
+    Stats::Vector statComInst;
+    Stats::Vector statComSwp;
+    Stats::Vector statComRefs;
+    Stats::Vector statComLoads;
+    Stats::Vector statComMembars;
+    Stats::Vector statComBranches;
 
-    Stats::Distribution<> nCommittedDist;
+    Stats::Distribution nCommittedDist;
 
-    Stats::Scalar<> commitEligibleSamples;
-    Stats::Vector<> commitEligible;
+    Stats::Scalar commitEligibleSamples;
+    Stats::Vector commitEligible;
 
-    Stats::Vector<> squashedInsts;
-    Stats::Vector<> ROBSquashedInsts;
+    Stats::Vector squashedInsts;
+    Stats::Vector ROBSquashedInsts;
 
-    Stats::Scalar<> ROBFcount;
+    Stats::Scalar ROBFcount;
     Stats::Formula ROBFullRate;
 
-    Stats::Vector<>  ROBCount;   // cumulative ROB occupancy
+    Stats::Vector  ROBCount;   // cumulative ROB occupancy
     Stats::Formula ROBOccRate;
-//    Stats::VectorDistribution<> ROBOccDist;
+//    Stats::VectorDistribution ROBOccDist;
   public:
     void dumpInsts();
 

diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 2525da76e85ce82e3589b33634645c7318b31e82..4f8101bc015b992025a0fa68fc69d1ab02ef01a7 100644 (file)
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -411,9 +411,9 @@ class OzoneLWLSQ {
     //list<InstSeqNum> mshrSeqNums;
 
     /** Tota number of memory ordering violations. */
-    Stats::Scalar<> lsqMemOrderViolation;
+    Stats::Scalar lsqMemOrderViolation;
 
-     //Stats::Scalar<> dcacheStallCycles;
+     //Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 
     // Make these per thread?

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index d2ccc0ff10d026c0b40ccc81c67fdbebefbb2e75..e80606388d30313d16660d758fb0ed7fd6d87aa2 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -177,7 +177,7 @@ class BaseSimpleCPU : public BaseCPU
     // number of simulated instructions
     Counter numInst;
     Counter startNumInst;
-    Stats::Scalar<> numInsts;
+    Stats::Scalar numInsts;
 
     void countInst()
     {
@@ -196,30 +196,30 @@ class BaseSimpleCPU : public BaseCPU
     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 
     // number of simulated memory references
-    Stats::Scalar<> numMemRefs;
+    Stats::Scalar numMemRefs;
 
     // number of simulated loads
     Counter numLoad;
     Counter startNumLoad;
 
     // number of idle cycles
-    Stats::Average<> notIdleFraction;
+    Stats::Average notIdleFraction;
     Stats::Formula idleFraction;
 
     // number of cycles stalled for I-cache responses
-    Stats::Scalar<> icacheStallCycles;
+    Stats::Scalar icacheStallCycles;
     Counter lastIcacheStall;
 
     // number of cycles stalled for I-cache retries
-    Stats::Scalar<> icacheRetryCycles;
+    Stats::Scalar icacheRetryCycles;
     Counter lastIcacheRetry;
 
     // number of cycles stalled for D-cache responses
-    Stats::Scalar<> dcacheStallCycles;
+    Stats::Scalar dcacheStallCycles;
     Counter lastDcacheStall;
 
     // number of cycles stalled for D-cache retries
-    Stats::Scalar<> dcacheRetryCycles;
+    Stats::Scalar dcacheRetryCycles;
     Counter lastDcacheRetry;
 
     virtual void serialize(std::ostream &os);

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 4465ce635fc279ae09f05d2f6b0e278fc1336957..99f0c2a873a05367a5469b119fc0613da1340ec4 100644 (file)
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -155,9 +155,9 @@ struct ThreadState {
     /** Number of instructions committed. */
     Counter numInst;
     /** Stat for number instructions committed. */
-    Stats::Scalar<> numInsts;
+    Stats::Scalar numInsts;
     /** Stat for number of memory references. */
-    Stats::Scalar<> numMemRefs;
+    Stats::Scalar numMemRefs;
 
     /** Number of simulated loads, used for tracking events based on
      * the number of loads committed.

diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh
index 12531f68c1f7d6067c59d967b64f8ed1e7cbbf7a..dfe469588708f8f306a6e87c5ce01e7209e59a13 100644 (file)
--- a/src/dev/copy_engine.hh
+++ b/src/dev/copy_engine.hh
@@ -164,8 +164,8 @@ class CopyEngine : public PciDev
 
   private:
 
-    Stats::Vector<> bytesCopied;
-    Stats::Vector<> copiesProcessed;
+    Stats::Vector bytesCopied;
+    Stats::Vector copiesProcessed;
 
     // device registers
     CopyEngineReg::Regs regs;

diff --git a/src/dev/etherdevice.hh b/src/dev/etherdevice.hh
index e43f3b686fda7b0b1d4aa7203a54a32a8c1b4a1c..5d86275b4479cdaeb0cdf90c3efde541d4806840 100644 (file)
--- a/src/dev/etherdevice.hh
+++ b/src/dev/etherdevice.hh
@@ -69,20 +69,20 @@ class EtherDevice : public PciDev
     void regStats();
 
   protected:
-    Stats::Scalar<> txBytes;
-    Stats::Scalar<> rxBytes;
-    Stats::Scalar<> txPackets;
-    Stats::Scalar<> rxPackets;
-    Stats::Scalar<> txIpChecksums;
-    Stats::Scalar<> rxIpChecksums;
-    Stats::Scalar<> txTcpChecksums;
-    Stats::Scalar<> rxTcpChecksums;
-    Stats::Scalar<> txUdpChecksums;
-    Stats::Scalar<> rxUdpChecksums;
-    Stats::Scalar<> descDmaReads;
-    Stats::Scalar<> descDmaWrites;
-    Stats::Scalar<> descDmaRdBytes;
-    Stats::Scalar<> descDmaWrBytes;
+    Stats::Scalar txBytes;
+    Stats::Scalar rxBytes;
+    Stats::Scalar txPackets;
+    Stats::Scalar rxPackets;
+    Stats::Scalar txIpChecksums;
+    Stats::Scalar rxIpChecksums;
+    Stats::Scalar txTcpChecksums;
+    Stats::Scalar rxTcpChecksums;
+    Stats::Scalar txUdpChecksums;
+    Stats::Scalar rxUdpChecksums;
+    Stats::Scalar descDmaReads;
+    Stats::Scalar descDmaWrites;
+    Stats::Scalar descDmaRdBytes;
+    Stats::Scalar descDmaWrBytes;
     Stats::Formula totBandwidth;
     Stats::Formula totPackets;
     Stats::Formula totBytes;
@@ -91,33 +91,33 @@ class EtherDevice : public PciDev
     Stats::Formula rxBandwidth;
     Stats::Formula txPacketRate;
     Stats::Formula rxPacketRate;
-    Stats::Scalar<> postedSwi;
+    Stats::Scalar postedSwi;
     Stats::Formula coalescedSwi;
-    Stats::Scalar<> totalSwi;
-    Stats::Scalar<> postedRxIdle;
+    Stats::Scalar totalSwi;
+    Stats::Scalar postedRxIdle;
     Stats::Formula coalescedRxIdle;
-    Stats::Scalar<> totalRxIdle;
-    Stats::Scalar<> postedRxOk;
+    Stats::Scalar totalRxIdle;
+    Stats::Scalar postedRxOk;
     Stats::Formula coalescedRxOk;
-    Stats::Scalar<> totalRxOk;
-    Stats::Scalar<> postedRxDesc;
+    Stats::Scalar totalRxOk;
+    Stats::Scalar postedRxDesc;
     Stats::Formula coalescedRxDesc;
-    Stats::Scalar<> totalRxDesc;
-    Stats::Scalar<> postedTxOk;
+    Stats::Scalar totalRxDesc;
+    Stats::Scalar postedTxOk;
     Stats::Formula coalescedTxOk;
-    Stats::Scalar<> totalTxOk;
-    Stats::Scalar<> postedTxIdle;
+    Stats::Scalar totalTxOk;
+    Stats::Scalar postedTxIdle;
     Stats::Formula coalescedTxIdle;
-    Stats::Scalar<> totalTxIdle;
-    Stats::Scalar<> postedTxDesc;
+    Stats::Scalar totalTxIdle;
+    Stats::Scalar postedTxDesc;
     Stats::Formula coalescedTxDesc;
-    Stats::Scalar<> totalTxDesc;
-    Stats::Scalar<> postedRxOrn;
+    Stats::Scalar totalTxDesc;
+    Stats::Scalar postedRxOrn;
     Stats::Formula coalescedRxOrn;
-    Stats::Scalar<> totalRxOrn;
+    Stats::Scalar totalRxOrn;
     Stats::Formula coalescedTotal;
-    Stats::Scalar<> postedInterrupts;
-    Stats::Scalar<> droppedPackets;
+    Stats::Scalar postedInterrupts;
+    Stats::Scalar droppedPackets;
 };
 
 #endif //__DEV_ETHERDEVICE_HH__

diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh
index 68ae5c3c0b8e04e249f72210b1983d741146ee16..1b455e8ad3ba2f1f1718b9ef72ed527106ec1104 100644 (file)
--- a/src/dev/ide_disk.hh
+++ b/src/dev/ide_disk.hh
@@ -238,12 +238,12 @@ class IdeDisk : public SimObject
     /** Interrupt pending */
     bool intrPending;
 
-    Stats::Scalar<> dmaReadFullPages;
-    Stats::Scalar<> dmaReadBytes;
-    Stats::Scalar<> dmaReadTxs;
-    Stats::Scalar<> dmaWriteFullPages;
-    Stats::Scalar<> dmaWriteBytes;
-    Stats::Scalar<> dmaWriteTxs;
+    Stats::Scalar dmaReadFullPages;
+    Stats::Scalar dmaReadBytes;
+    Stats::Scalar dmaReadTxs;
+    Stats::Scalar dmaWriteFullPages;
+    Stats::Scalar dmaWriteBytes;
+    Stats::Scalar dmaWriteTxs;
     Stats::Formula rdBandwidth;
     Stats::Formula wrBandwidth;
     Stats::Formula totBandwidth;

diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh
index 3185e86963af5610006eba56df90ef84ebf5a512..cd8412ef4c226368226db608049a69d70f0d11cd 100644 (file)
--- a/src/dev/sinic.hh
+++ b/src/dev/sinic.hh
@@ -283,35 +283,35 @@ class Device : public Base
  * Statistics
  */
   private:
-    Stats::Scalar<> rxBytes;
+    Stats::Scalar rxBytes;
     Stats::Formula  rxBandwidth;
-    Stats::Scalar<> rxPackets;
+    Stats::Scalar rxPackets;
     Stats::Formula  rxPacketRate;
-    Stats::Scalar<> rxIpPackets;
-    Stats::Scalar<> rxTcpPackets;
-    Stats::Scalar<> rxUdpPackets;
-    Stats::Scalar<> rxIpChecksums;
-    Stats::Scalar<> rxTcpChecksums;
-    Stats::Scalar<> rxUdpChecksums;
-
-    Stats::Scalar<> txBytes;
+    Stats::Scalar rxIpPackets;
+    Stats::Scalar rxTcpPackets;
+    Stats::Scalar rxUdpPackets;
+    Stats::Scalar rxIpChecksums;
+    Stats::Scalar rxTcpChecksums;
+    Stats::Scalar rxUdpChecksums;
+
+    Stats::Scalar txBytes;
     Stats::Formula  txBandwidth;
     Stats::Formula totBandwidth;
     Stats::Formula totPackets;
     Stats::Formula totBytes;
     Stats::Formula totPacketRate;
-    Stats::Scalar<> txPackets;
+    Stats::Scalar txPackets;
     Stats::Formula  txPacketRate;
-    Stats::Scalar<> txIpPackets;
-    Stats::Scalar<> txTcpPackets;
-    Stats::Scalar<> txUdpPackets;
-    Stats::Scalar<> txIpChecksums;
-    Stats::Scalar<> txTcpChecksums;
-    Stats::Scalar<> txUdpChecksums;
-
-    Stats::Scalar<> totalVnicDistance;
-    Stats::Scalar<> numVnicDistance;
-    Stats::Scalar<> maxVnicDistance;
+    Stats::Scalar txIpPackets;
+    Stats::Scalar txTcpPackets;
+    Stats::Scalar txUdpPackets;
+    Stats::Scalar txIpChecksums;
+    Stats::Scalar txTcpChecksums;
+    Stats::Scalar txUdpChecksums;
+
+    Stats::Scalar totalVnicDistance;
+    Stats::Scalar numVnicDistance;
+    Stats::Scalar maxVnicDistance;
     Stats::Formula avgVnicDistance;
 
     int _maxVnicDistance;

diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh
index 66248c9c897068f1aff5579852fd8ff56bf8bba3..85a47ec0007993471dfe109368974945f83978aa 100644 (file)
--- a/src/kern/kernel_stats.hh
+++ b/src/kern/kernel_stats.hh
@@ -51,17 +51,17 @@ class Statistics : public Serializable
     std::string myname;
 
   protected:
-    Stats::Scalar<> _arm;
-    Stats::Scalar<> _quiesce;
-    Stats::Scalar<> _hwrei;
+    Stats::Scalar _arm;
+    Stats::Scalar _quiesce;
+    Stats::Scalar _hwrei;
 
-    Stats::Vector<> _iplCount;
-    Stats::Vector<> _iplGood;
-    Stats::Vector<> _iplTicks;
+    Stats::Vector _iplCount;
+    Stats::Vector _iplGood;
+    Stats::Vector _iplTicks;
     Stats::Formula _iplUsed;
 
-    Stats::Vector<> _syscall;
-//    Stats::Vector<> _faults;
+    Stats::Vector _syscall;
+//    Stats::Vector _faults;
 
   private:
     int iplLast;

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index fe191fb1c186e83c87e74d6bbe94361e403a440d..4319717e5b3714237840f5c3fc386d3a70110734 100644 (file)
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -223,14 +223,14 @@ class BaseCache : public MemObject
      */
 
     /** Number of hits per thread for each type of command. @sa Packet::Command */
-    Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
     /** Number of hits for demand accesses. */
     Stats::Formula demandHits;
     /** Number of hit for all accesses. */
     Stats::Formula overallHits;
 
     /** Number of misses per thread for each type of command. @sa Packet::Command */
-    Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
     /** Number of misses for demand accesses. */
     Stats::Formula demandMisses;
     /** Number of misses for all accesses. */
@@ -240,7 +240,7 @@ class BaseCache : public MemObject
      * Total number of cycles per thread/command spent waiting for a miss.
      * Used to calculate the average miss latency.
      */
-    Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
     /** Total number of cycles spent waiting for demand misses. */
     Stats::Formula demandMissLatency;
     /** Total number of cycles spent waiting for all misses. */
@@ -268,50 +268,50 @@ class BaseCache : public MemObject
     Stats::Formula overallAvgMissLatency;
 
     /** The total number of cycles blocked for each blocked cause. */
-    Stats::Vector<> blocked_cycles;
+    Stats::Vector blocked_cycles;
     /** The number of times this cache blocked for each blocked cause. */
-    Stats::Vector<> blocked_causes;
+    Stats::Vector blocked_causes;
 
     /** The average number of cycles blocked for each blocked cause. */
     Stats::Formula avg_blocked;
 
     /** The number of fast writes (WH64) performed. */
-    Stats::Scalar<> fastWrites;
+    Stats::Scalar fastWrites;
 
     /** The number of cache copies performed. */
-    Stats::Scalar<> cacheCopies;
+    Stats::Scalar cacheCopies;
 
     /** Number of blocks written back per thread. */
-    Stats::Vector<> writebacks;
+    Stats::Vector writebacks;
 
     /** Number of misses that hit in the MSHRs per command and thread. */
-    Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
     /** Demand misses that hit in the MSHRs. */
     Stats::Formula demandMshrHits;
     /** Total number of misses that hit in the MSHRs. */
     Stats::Formula overallMshrHits;
 
     /** Number of misses that miss in the MSHRs, per command and thread. */
-    Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
     /** Demand misses that miss in the MSHRs. */
     Stats::Formula demandMshrMisses;
     /** Total number of misses that miss in the MSHRs. */
     Stats::Formula overallMshrMisses;
 
     /** Number of misses that miss in the MSHRs, per command and thread. */
-    Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
     /** Total number of misses that miss in the MSHRs. */
     Stats::Formula overallMshrUncacheable;
 
     /** Total cycle latency of each MSHR miss, per command and thread. */
-    Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
     /** Total cycle latency of demand MSHR misses. */
     Stats::Formula demandMshrMissLatency;
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrMissLatency;
 
     /** Total cycle latency of each MSHR miss, per command and thread. */
-    Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
+    Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrUncacheableLatency;
 
@@ -342,11 +342,11 @@ class BaseCache : public MemObject
     Stats::Formula overallAvgMshrUncacheableLatency;
 
     /** The number of times a thread hit its MSHR cap. */
-    Stats::Vector<> mshr_cap_events;
+    Stats::Vector mshr_cap_events;
     /** The number of times software prefetches caused the MSHR to block. */
-    Stats::Vector<> soft_prefetch_mshr_full;
+    Stats::Vector soft_prefetch_mshr_full;
 
-    Stats::Scalar<> mshr_no_allocate_misses;
+    Stats::Scalar mshr_no_allocate_misses;
 
     /**
      * @}

diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 92040e899852696c86b6d56db20c97965cbb9717..fc027cb3beb4fc7440b48ad59073b1263f77edaf 100644 (file)
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -79,15 +79,15 @@ class BasePrefetcher
 
   public:
 
-    Stats::Scalar<> pfIdentified;
-    Stats::Scalar<> pfMSHRHit;
-    Stats::Scalar<> pfCacheHit;
-    Stats::Scalar<> pfBufferHit;
-    Stats::Scalar<> pfRemovedFull;
-    Stats::Scalar<> pfRemovedMSHR;
-    Stats::Scalar<> pfIssued;
-    Stats::Scalar<> pfSpanPage;
-    Stats::Scalar<> pfSquashed;
+    Stats::Scalar pfIdentified;
+    Stats::Scalar pfMSHRHit;
+    Stats::Scalar pfCacheHit;
+    Stats::Scalar pfBufferHit;
+    Stats::Scalar pfRemovedFull;
+    Stats::Scalar pfRemovedMSHR;
+    Stats::Scalar pfIssued;
+    Stats::Scalar pfSpanPage;
+    Stats::Scalar pfSquashed;
 
     void regStats(const std::string &name);
 

diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index b7b0c7ef03ac88115ef498c8aad2547b79a2ccf6..46c7186b13a3dd3e9ba807b5827931f6b8678493 100644 (file)
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -70,19 +70,19 @@ class BaseTags
      */
 
     /** Number of replacements of valid blocks per thread. */
-    Stats::Vector<> replacements;
+    Stats::Vector replacements;
     /** Per cycle average of the number of tags that hold valid data. */
-    Stats::Average<> tagsInUse;
+    Stats::Average tagsInUse;
 
     /** The total number of references to a block before it is replaced. */
-    Stats::Scalar<> totalRefs;
+    Stats::Scalar totalRefs;
 
     /**
      * The number of reference counts sampled. This is different from
      * replacements because we sample all the valid blocks when the simulator
      * exits.
      */
-    Stats::Scalar<> sampledRefs;
+    Stats::Scalar sampledRefs;
 
     /**
      * Average number of references to a block before is was replaced.
@@ -91,7 +91,7 @@ class BaseTags
     Stats::Formula avgRefs;
 
     /** The cycle that the warmup percentage was hit. */
-    Stats::Scalar<> warmupCycle;
+    Stats::Scalar warmupCycle;
     /**
      * @}
      */

diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 7925e18700540dadff8fad0cc6d26b650df148e0..4eab10c49f917a23fa0133522f49430b4224fe87 100644 (file)
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -139,11 +139,11 @@ class FALRU : public BaseTags
      */
 
     /** Hits in each cache size >= 128K. */
-    Stats::Vector<> hits;
+    Stats::Vector hits;
     /** Misses in each cache size >= 128K. */
-    Stats::Vector<> misses;
+    Stats::Vector misses;
     /** Total number of accesses. */
-    Stats::Scalar<> accesses;
+    Stats::Scalar accesses;
 
     /**
      * @}

diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 9e14dc119e0617115c716876fb41c6e477308365..45c8ee8012b20d6199e6a2d328ee5b9686705a92 100644 (file)
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -248,20 +248,20 @@ class IIC : public BaseTags
      */
 
     /** Hash hit depth of cache hits. */
-    Stats::Distribution<> hitHashDepth;
+    Stats::Distribution hitHashDepth;
     /** Hash depth for cache misses. */
-    Stats::Distribution<> missHashDepth;
+    Stats::Distribution missHashDepth;
     /** Count of accesses to each hash set. */
-    Stats::Distribution<> setAccess;
+    Stats::Distribution setAccess;
 
     /** The total hash depth for every miss. */
-    Stats::Scalar<> missDepthTotal;
+    Stats::Scalar missDepthTotal;
     /** The total hash depth for all hits. */
-    Stats::Scalar<> hitDepthTotal;
+    Stats::Scalar hitDepthTotal;
     /** The number of hash misses. */
-    Stats::Scalar<> hashMiss;
+    Stats::Scalar hashMiss;
     /** The number of hash hits. */
-    Stats::Scalar<> hashHit;
+    Stats::Scalar hashHit;
     /** @} */
 
   public:

diff --git a/src/mem/cache/tags/iic_repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh
index 22436b384a51453b97c834136c8d4622d5749b16..fe105d95aba3926e7c8bc5ab903a61ebf48b39ae 100644 (file)
--- a/src/mem/cache/tags/iic_repl/gen.hh
+++ b/src/mem/cache/tags/iic_repl/gen.hh
@@ -162,11 +162,11 @@ class GenRepl : public Repl
      * @{
      */
     /** The number of replacements from each pool. */
-    Stats::Distribution<> repl_pool;
+    Stats::Distribution repl_pool;
     /** The number of advances out of each pool. */
-    Stats::Distribution<> advance_pool;
+    Stats::Distribution advance_pool;
     /** The number of demotions from each pool. */
-    Stats::Distribution<> demote_pool;
+    Stats::Distribution demote_pool;
     /**
      * @}
      */

diff --git a/src/mem/dram.hh b/src/mem/dram.hh
index 352ca96ae1b228e387c4f4aafb026dbf5fa18b54..1745fa52b17b355c106a94eb59fb7370423e0178 100644 (file)
--- a/src/mem/dram.hh
+++ b/src/mem/dram.hh
@@ -117,27 +117,27 @@ class DRAMMemory : public PhysicalMemory
     Tick time_last_access;
 
 
-    Stats::Vector<> accesses;
-    Stats::Vector<> bytesRequested;
-    Stats::Vector<> bytesSent;
-    Stats::Vector<> compressedAccesses;
-
-    Stats::Vector<> cycles_nCKE;
-    Stats::Vector<> cycles_all_precharge_CKE;
-    Stats::Vector<> cycles_all_precharge_nCKE;
-    Stats::Vector<> cycles_bank_active_nCKE;
-    Stats::Vector<> cycles_avg_ACT;
-    Stats::Vector<> cycles_read_out;
-    Stats::Vector<> cycles_write_in;
-    Stats::Vector<> cycles_between_misses;
-    Stats::Vector<> other_bank_read_access_miss;
-    Stats::Vector<> other_bank_write_access_miss;
-    Stats::Scalar<> total_latency;
-    Stats::Scalar<> total_icache_req;
-    Stats::Scalar<> total_arb_latency;
+    Stats::Vector accesses;
+    Stats::Vector bytesRequested;
+    Stats::Vector bytesSent;
+    Stats::Vector compressedAccesses;
+
+    Stats::Vector cycles_nCKE;
+    Stats::Vector cycles_all_precharge_CKE;
+    Stats::Vector cycles_all_precharge_nCKE;
+    Stats::Vector cycles_bank_active_nCKE;
+    Stats::Vector cycles_avg_ACT;
+    Stats::Vector cycles_read_out;
+    Stats::Vector cycles_write_in;
+    Stats::Vector cycles_between_misses;
+    Stats::Vector other_bank_read_access_miss;
+    Stats::Vector other_bank_write_access_miss;
+    Stats::Scalar total_latency;
+    Stats::Scalar total_icache_req;
+    Stats::Scalar total_arb_latency;
     Stats::Formula avg_latency;
     Stats::Formula avg_arb_latency;
-    Stats::Vector2d<> bank_access_profile;
+    Stats::Vector2d bank_access_profile;
 
 
   protected:

diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index cfc6ad1052a60e468aade47a7a51a32f942e4ee6..75696641bdb47786a791850db0441d082cd0bea8 100644 (file)
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -41,7 +41,7 @@ class FaultBase;
 typedef RefCountingPtr<FaultBase> Fault;
 
 typedef const char * FaultName;
-typedef Stats::Scalar<> FaultStat;
+typedef Stats::Scalar FaultStat;
 
 // Each class has it's name statically define in _name,
 // and has a virtual function to access it's name.

diff --git a/src/sim/process.hh b/src/sim/process.hh
index 790adcb872aa6190dce35ad67c2a1a69846f120a..5272094677cee929779763d8ff95165badbee75e 100644 (file)
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -137,7 +137,7 @@ class Process : public SimObject
 
     std::string prog_fname;     // file name
 
-    Stats::Scalar<> num_syscalls;       // number of syscalls executed
+    Stats::Scalar num_syscalls;       // number of syscalls executed
 
 
   protected:

diff --git a/src/unittest/stattest.cc b/src/unittest/stattest.cc
index 30b7f8a6c5007bcc1009de8332375121c7bbaea2..3934786ec4cd25e467ab9185b927d6403f630d93 100644 (file)
--- a/src/unittest/stattest.cc
+++ b/src/unittest/stattest.cc
@@ -116,22 +116,22 @@ main(int argc, char *argv[])
     if (!text && (compat || descriptions))
         usage();
 
-    Scalar<> s1;
-    Scalar<> s2;
-    Average<> s3;
-    Scalar<> s4;
-    Vector<> s5;
-    Distribution<> s6;
-    Vector<> s7;
-    AverageVector<> s8;
-    StandardDeviation<> s9;
-    AverageDeviation<> s10;
-    Scalar<> s11;
-    Distribution<> s12;
-    VectorDistribution<> s13;
-    VectorStandardDeviation<> s14;
-    VectorAverageDeviation<> s15;
-    Vector2d<> s16;
+    Scalar s1;
+    Scalar s2;
+    Average s3;
+    Scalar s4;
+    Vector s5;
+    Distribution s6;
+    Vector s7;
+    AverageVector s8;
+    StandardDeviation s9;
+    AverageDeviation s10;
+    Scalar s11;
+    Distribution s12;
+    VectorDistribution s13;
+    VectorStandardDeviation s14;
+    VectorAverageDeviation s15;
+    Vector2d s16;
     Value s17;
     Value s18;
 
@@ -141,9 +141,9 @@ main(int argc, char *argv[])
     Formula f4;
     Formula f5;
 
-    cprintf("sizeof(Scalar<>) = %d\n", sizeof(Scalar<>));
-    cprintf("sizeof(Vector<>) = %d\n", sizeof(Vector<>));
-    cprintf("sizeof(Distribution<>) = %d\n", sizeof(Distribution<>));
+    cprintf("sizeof(Scalar) = %d\n", sizeof(Scalar));
+    cprintf("sizeof(Vector) = %d\n", sizeof(Vector));
+    cprintf("sizeof(Distribution) = %d\n", sizeof(Distribution));
 
     s1
         .name("Stat01")