h8300.md (div patterns): Rewrite.
authorJeff Law <law@gcc.gnu.org>
Wed, 22 May 1996 03:50:11 +0000 (21:50 -0600)
committerJeff Law <law@gcc.gnu.org>
Wed, 22 May 1996 03:50:11 +0000 (21:50 -0600)
        * h8300/h8300.md (div patterns): Rewrite.
        (mod patterns): Likewise.

From-SVN: r12072

gcc/config/h8300/h8300.md

index f714b84317d756357768aa62957a4197fa08a9b1..ae32c1e9cfcd3d0ef2dcd1d71d6bfa573c97290b 100644 (file)
 
 (define_insn "udivqi3"
   [(set (match_operand:QI 0 "register_operand" "=r")
-       (udiv:QI (match_operand:HI 1 "general_operand" "0")
-                (match_operand:QI 2 "register_operand" "r")))]
+       (truncate:QI
+         (udiv:HI
+           (match_operand:HI 1 "general_operand" "0")
+           (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
   ""
   "divxu       %X2,%T0"
   [(set_attr "length" "2")
 
 (define_insn "divqi3"
   [(set (match_operand:QI 0 "register_operand" "=r")
-       (div:QI (match_operand:HI 1 "general_operand" "0")
-               (match_operand:QI 2 "register_operand" "r")))]
+       (truncate:QI
+         (div:HI
+           (match_operand:HI 1 "general_operand" "0")
+           (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
   ""
   "divxu       %X2,%T0"
   [(set_attr "length" "2")
 
 (define_insn "udivhi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (udiv:HI (match_operand:SI 1 "general_operand" "0")
-                (match_operand:HI 2 "register_operand" "r")))]
+       (truncate:HI
+         (udiv:SI
+           (match_operand:SI 1 "general_operand" "0")
+           (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
   "TARGET_H8300H"
   "divxu.w     %T2,%S0"
   [(set_attr "length" "2")
 
 (define_insn "divhi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (div:HI (match_operand:SI 1 "general_operand" "0")
-               (match_operand:HI 2 "register_operand" "r")))]
+       (truncate:HI
+         (div:SI
+           (match_operand:SI 1 "general_operand" "0")
+           (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
   "TARGET_H8300H"
   "divxs.w     %T2,%S0"
   [(set_attr "length" "4")
 
 (define_insn "umodqi3"
   [(set (match_operand:QI 0 "register_operand" "=r")
-       (umod:QI (match_operand:HI 1 "general_operand" "0")
-                (match_operand:QI 2 "register_operand" "r")))]
+       (truncate:QI
+         (umod:HI
+           (match_operand:HI 1 "general_operand" "0")
+           (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
   ""
   "divxu       %X2,%T0\;mov %t0,%s0"
   [(set_attr "length" "4")
 
 (define_insn "modqi3"
   [(set (match_operand:QI 0 "register_operand" "=r")
-       (mod:QI (match_operand:HI 1 "general_operand" "0")
-               (match_operand:QI 2 "register_operand" "r")))]
+       (truncate:QI
+         (mod:HI
+           (match_operand:HI 1 "general_operand" "0")
+           (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
   "TARGET_H8300H"
   "divxs.b     %X2,%T0\;mov %t0,%s0"
   [(set_attr "length" "6")
 
 (define_insn "umodhi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (umod:HI (match_operand:SI 1 "general_operand" "0")
-                (match_operand:HI 2 "register_operand" "r")))]
+       (truncate:HI
+         (umod:SI
+           (match_operand:SI 1 "general_operand" "0")
+           (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
   "TARGET_H8300H"
   "divxu.w     %T2,%S0\;mov %e0,%f0"
   [(set_attr "length" "4")
 
 (define_insn "modhi3"
   [(set (match_operand:HI 0 "register_operand" "=r")
-       (mod:HI (match_operand:SI 1 "general_operand" "0")
-               (match_operand:HI 2 "register_operand" "r")))]
+       (truncate:HI
+         (mod:SI
+           (match_operand:SI 1 "general_operand" "0")
+           (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
   "TARGET_H8300H"
   "divxs.w     %T2,%S0\;mov %e0,%f0"
   [(set_attr "length" "6")