radv: add sample mask output support

This adds support to write to sample mask from the fragment shader.

We can optimise this later like radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 602164736421c962fa33ede86141a510020f00ac..9778581a1efbe261f0436b393963e364eb5a0040 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4753,13 +4753,17 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
                        ctx->shader_info->fs.writes_stencil = true;
                        stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
                                                              ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
+               } else if (i == FRAG_RESULT_SAMPLE_MASK) {
+                       ctx->shader_info->fs.writes_sample_mask = true;
+                       samplemask = to_float(ctx, LLVMBuildLoad(ctx->builder,
+                                                                 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
                } else {
                        bool last = false;
                        for (unsigned j = 0; j < 4; j++)
                                values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
                                                                        ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
 
-                       if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
+                       if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil && !ctx->shader_info->fs.writes_sample_mask)
                                last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
 
                        si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
@@ -4767,7 +4771,7 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
                }
        }
 
-       if (depth || stencil)
+       if (depth || stencil || samplemask)
                si_export_mrt_z(ctx, depth, stencil, samplemask);
        else if (!index)
                si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);

diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index c2662e2fe9caa4b528173d3462bdb226d4d10146..6c2b78b4e712287a5d7cde48dedc5dc767ad6b2e 100644 (file)
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -118,6 +118,7 @@ struct ac_shader_variant_info {
                        bool can_discard;
                        bool writes_z;
                        bool writes_stencil;
+                       bool writes_sample_mask;
                        bool early_fragment_test;
                        bool writes_memory;
                        bool force_persample;

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5b7564c63990cab1427d5a6c3ef1238fa8f490ce..1e38cbe125137daa4565e4f06e74b79957562893 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -674,6 +674,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
                               S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
                               S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
                               S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
+                              S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
                               S_02880C_Z_ORDER(z_order) |
                               S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
                               S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
@@ -694,6 +695,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
 
        radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
+                              ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
                               ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
                               ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
                               V_028710_SPI_SHADER_ZERO);