ppc: refactor assemling logic

diff --git a/gas/config/tc-ppc-svp64.c b/gas/config/tc-ppc-svp64.c
index b9a07c2f594de9c4f00856953b6d086e86a82daf..a87e71c203875e855c5924b2d120c81c891abfc5 100644 (file)
--- a/gas/config/tc-ppc-svp64.c
+++ b/gas/config/tc-ppc-svp64.c
@@ -720,7 +720,10 @@ svp64_decode (char *str, struct svp64_ctx *svp64)
 {
   char *opc;
   size_t opclen;
+  char *args;
+  size_t argslen;
   char *iter;
+  char *base = str;
 
   str += (sizeof ("sv.") - 1);
   if (! ISALPHA (*str))
@@ -745,10 +748,21 @@ svp64_decode (char *str, struct svp64_ctx *svp64)
 
   for (; (iter = svp64_decode_mode (str, svp64)) != NULL; str = iter)
     ;
+  args = str;
+  argslen = strlen (args);
 
   svp64->desc = (const struct svp64_desc *) str_hash_find (svp64_hash, opc);
   if (!svp64->desc)
     svp64_raise (_("unrecognized opcode: `%s'"), str);
+
+  iter = base;
+  memmove (iter, opc, opclen);
+  iter += opclen;
+  *iter++ = ' ';
+
+  memmove (iter, args, argslen);
+  iter += argslen;
+  *iter++ = '\0';
 }
 
 static void
@@ -1009,7 +1023,5 @@ svp64_assemble (char *str)
   svp64_decode (str, &svp64);
   svp64_validate_and_fix (&svp64);
 
-  as_warn (_("opcode ignored (desc=%p)"), svp64.desc);
-  memcpy (str, "nop", sizeof ("nop"));
-  md_assemble (str);
+  ppc_assemble (str, &svp64);
 }

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 1623f4fa5d362f302de4cc43f470a2a8f42e9b8d..25e4a7de2f851c29b8a24cd989da2266b74200a8 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -36,6 +36,11 @@
 #include "libxcoff.h"
 #endif
 
+struct svp64_ctx;
+
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED);
+
 #include "tc-ppc-svp64.c"
 
 /* This is the assembler for the PowerPC or POWER (RS/6000) chips.  */
@@ -3292,8 +3297,8 @@ is_svp64_insn (char *str)
 
 /* This routine is called for each instruction to be assembled.  */
 
-void
-md_assemble (char *str)
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED)
 {
   char *s;
   const struct powerpc_opcode *opcode;
@@ -3320,6 +3325,7 @@ md_assemble (char *str)
     {
       if (is_svp64_insn (str))
         {
+          *(s - 1) = ' '; /* restore the original string */
           svp64_assemble (str);
           return;
         }
@@ -4143,6 +4149,11 @@ md_assemble (char *str)
     }
 }
 
+void
+md_assemble (char *str)
+{
+  ppc_assemble (str, NULL);
+}
 \f
 #ifdef OBJ_ELF
 /* For ELF, add support for SHT_ORDERED.  */