lib.cdc: fix tests to actually run.

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index 462a422b07a589df1d41d97fd353fb59f1c5f420..7ee588d08d4b8cbd73c76838f74ad18ee04241a8 100644 (file)
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -860,7 +860,7 @@ class Delay(Statement):
 
 
 class Tick(Statement):
-    def __init__(self, domain):
+    def __init__(self, domain="sync"):
         self.domain = str(domain)
 
     def _rhs_signals(self):

diff --git a/nmigen/test/test_lib_cdc.py b/nmigen/test/test_lib_cdc.py
index b65c04e12e76f6c0881582da9dfca1aabb37ef9b..af68d2f925f917b19a7fe558eed312aa8923213e 100644 (file)
--- a/nmigen/test/test_lib_cdc.py
+++ b/nmigen/test/test_lib_cdc.py
@@ -21,6 +21,7 @@ class MultiRegTestCase(FHDLTestCase):
                 yield Tick()
                 self.assertEqual((yield o), 1)
             sim.add_process(process)
+            sim.run()
 
     def test_basic(self):
         i = Signal(reset=1)
@@ -38,3 +39,4 @@ class MultiRegTestCase(FHDLTestCase):
                 yield Tick()
                 self.assertEqual((yield o), 0)
             sim.add_process(process)
+            sim.run()