MIPS/opcodes: Free up redundant `g' operand code

In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154ba ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.

Later commit 351cdf24d223 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.

Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
	and "mtthc2" to using the `G' rather than `g' operand code for
	the coprocessor control register referred.

	include/
	* opcode/mips.h: Complement change made to opcodes and remove
	references to the `g' regular MIPS ISA operand code.

diff --git a/include/ChangeLog b/include/ChangeLog
index 19dc8e3db6f12821d3fce306b262b6ccec8b053c..b97775ec2141d7a4be6d1c58214d0ed707d4f395 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+       * opcode/mips.h: Complement change made to opcodes and remove
+       references to the `g' regular MIPS ISA operand code.
+
 2021-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/27905

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index f72c5db1fdd8642682eb195d19f5883597d436f3..9fa9fcbafde697911ceedef762a6dfd3d0a85e63 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -899,7 +899,6 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
    "$" 1 bit load high flag (OP_*_MT_H)
    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
-   "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 
    MCU ASE usage:
@@ -1001,7 +1000,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
    "1234567890"
    "%[]<>(),+-:'@!#$*&\~"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
-   "abcdefghijklopqrstuvwxz"
+   "abcdef hijkl  opqrstuvwx z"
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 48c62e8039d12873dce1f883345bb2569f30b842..f81b2f7cad383584b2d44d1a53a532c361f9a558 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
+
+       * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
+       and "mtthc2" to using the `G' rather than `g' operand code for
+       the coprocessor control register referred.
+
 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 
        * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 175f91a919e23305767f281441626f25213eb6c4..373c362ca8356ef168aee82d30fcee2873b7f14c 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -195,7 +195,6 @@ decode_mips_operand (const char *p)
     case 'c': HINT (10, 16);
     case 'd': REG (5, 11, GP);
     case 'e': UINT (3, 22)
-    case 'g': REG (5, 11, COPRO);
     case 'h': HINT (5, 11);
     case 'i': HINT (16, 0);
     case 'j': SINT (16, 0);
@@ -997,7 +996,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ctc3 is at the bottom of the table.  */
 {"cttc1",              "t,G",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
 {"cttc1",              "t,S",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
-{"cttc2",              "t,g",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"cttc2",              "t,G",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"cvt.d.l",            "D,S",          0x46a00021, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"cvt.d.s",            "D,S",          0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
 {"cvt.d.w",            "D,S",          0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
@@ -1556,14 +1555,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mttc0",              "t,G,H",        0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
 {"mttc1",              "t,S",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
 {"mttc1",              "t,G",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
-{"mttc2",              "t,g",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mttc2",              "t,G",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mttacx",             "t",            0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttacx",             "t,&",          0x41801021, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttdsp",             "t",            0x41808021, 0xffe0ffff, RD_1|TRAP,              0,              0,              MT32,   0 },
 {"mttgpr",             "t,d",          0x41800020, 0xffe007ff, RD_1|WR_2|TRAP,         0,              0,              MT32,   0 },
 {"mtthc1",             "t,S",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
 {"mtthc1",             "t,G",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
-{"mtthc2",             "t,g",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mtthc2",             "t,G",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mtthi",              "t",            0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mtthi",              "t,&",          0x41800821, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttlo",              "t",            0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },