clarify

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index aeae7e8ae546aa0892df747ea58ce6a227365214..babc49455d8b6797d4fc856896698e872ca859e4 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -118,8 +118,8 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
   currently named "SVP64-Single" [^likeext001]
 * A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**
   such that future unforeseen capability is needed.
-* To hold all Vector Context, five SPRs are needed for userspace
-  (MSR.PR=1 Problem State).  If Supervisor and Hypervisor mode are to
+* To hold all Vector Context, five SPRs are needed for userspace.
+  If Supervisor and Hypervisor mode are to
   also support Simple-V they will correspondingly need five SPRs each.
 * Five 6-bit XO (A-Form) "Management" instructions are needed.  These are
   Scalar 32-bit instructions and *may* be 64-bit-extended in future