arch-arm: Writes to DCCMVAC shouldn't flush pipeline

Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.

Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index aa3d93d6e25b0f6e19c2770c6b23cb649590bbb3..40e00accf1091537a59e3fab50b1930b654d81a7 100644 (file)
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -190,9 +190,6 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
     flags[IsNonSpeculative] = true;
     iss = _iss;
     miscReg = _miscReg;
-
-    if (miscReg == MISCREG_DCCMVAC)
-        flags[IsSquashAfter] = true;
 }
 
 Fault