add diagrams

diff --git a/simple_v_extension/padd9_alu4.png b/simple_v_extension/padd9_alu4.png
new file mode 100644 (file)
index 0000000..bd57ae5
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diff --git a/simple_v_extension/padd9_fifo.png b/simple_v_extension/padd9_fifo.png
new file mode 100644 (file)
index 0000000..81d9245
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diff --git a/simple_v_extension/padd9_simd.png b/simple_v_extension/padd9_simd.png
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index 0000000..46d0f0c
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diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 9d28b1ebc4c92277c22ab60d0b9ae18b4ed1e6a7..fc49acb64528f13088886d466b98a048d222cc65 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -170,6 +170,22 @@
 % but MODIFYING the remaining "vectorised" op, subtracting the now
 % scalar ops from it.
 
+\frame{\frametitle{Predicated 8-parallel ADD: optimised (not masked)}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_alu4.png}\\
+  {\bf \red Predicated adds are shuffled down: 4 in 1st cycle, 2 in 2nd}
+ \end{center}
+}
+
+
+\frame{\frametitle{Predicated 8-parallel ADD: 3 phase FIFO expansion}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_fifo.png}\\
+  {\bf \red First cycle takes first four 1s; second takes the rest}
+ \end{center}
+}
+
+
 \frame{\frametitle{How are SIMD Instructions Vectorised?}
 
  \begin{itemize}
@@ -189,6 +205,14 @@
 % or they can be used to cover several operations on totally different
 % vectors / registers.
 
+\frame{\frametitle{Predicated 9-parallel SIMD ADD}
+ \begin{center}
+  \includegraphics[height=2.5in]{padd9_simd.png}\\
+  {\bf \red 4-wide 8-bit SIMD, 4 bits of predicate passed to ALU}
+ \end{center}
+}
+
+
 \frame{\frametitle{What's the deal / juice / score?}
 
  \begin{itemize}