let InOperandList = ins;
let AsmString = asm;
let Pattern = pattern;
+ let Itinerary = NullALU;
let TSFlags{42-40} = Gen;
let TSFlags{63-48} = AMDILOp;
}
--- /dev/null
+//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//==-----------------------------------------------------------------------===//
+//
+// This file declares the AMDGPU specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _AMDGPUSUBTARGET_H_
+#define _AMDGPUSUBTARGET_H_
+#include "AMDILSubtarget.h"
+
+namespace llvm {
+
+class AMDGPUSubtarget : public AMDILSubtarget
+{
+ InstrItineraryData InstrItins;
+
+public:
+ AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
+ AMDILSubtarget(TT, CPU, FS)
+ {
+ InstrItins = getInstrItineraryForCPU(CPU);
+ }
+
+ const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
+};
+
+} // End namespace llvm
+
+#endif // AMDGPUSUBTARGET_H_
FrameLowering(TargetFrameLowering::StackGrowsUp,
Subtarget.device()->getStackAlignment(), 0),
IntrinsicInfo(this),
+ InstrItins(&Subtarget.getInstrItineraryData()),
mDump(false)
{
#define AMDGPU_TARGET_MACHINE_H
#include "AMDGPUInstrInfo.h"
+#include "AMDGPUSubtarget.h"
#include "AMDILFrameLowering.h"
#include "AMDILIntrinsicInfo.h"
-#include "AMDILSubtarget.h"
#include "R600ISelLowering.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/Target/TargetData.h"
class AMDGPUTargetMachine : public LLVMTargetMachine {
- AMDILSubtarget Subtarget;
+ AMDGPUSubtarget Subtarget;
const TargetData DataLayout;
AMDILFrameLowering FrameLowering;
AMDILIntrinsicInfo IntrinsicInfo;
const AMDGPUInstrInfo * InstrInfo;
AMDGPUTargetLowering * TLInfo;
+ const InstrItineraryData* InstrItins;
bool mDump;
public:
return &IntrinsicInfo;
}
virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;}
- virtual const AMDILSubtarget *getSubtargetImpl() const {return &Subtarget; }
+ virtual const AMDGPUSubtarget *getSubtargetImpl() const {return &Subtarget; }
virtual const AMDGPURegisterInfo *getRegisterInfo() const {
return &InstrInfo->getRegisterInfo();
}
virtual AMDGPUTargetLowering * getTargetLowering() const {
return TLInfo;
}
+ virtual const InstrItineraryData* getInstrItineraryData() const {
+ return InstrItins;
+ }
virtual const TargetData* getTargetData() const { return &DataLayout; }
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addPassesToEmitFile(PassManagerBase &PM,
include "llvm/Target/Target.td"
+// Dummy Instruction itineraries for pseudo instructions
+def ALU_NULL : FuncUnit;
+def NullALU : InstrItinClass;
+
//===----------------------------------------------------------------------===//
// AMDIL Subtarget features.
//===----------------------------------------------------------------------===//
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");
let isPseudo = 1;
+ let Itinerary = NullALU;
bit hasIEEEFlag = 0;
bit hasZeroOpFlag = 0;
}
AMDGPUGenCodeEmitter.inc: *.td
$(call tablegen, -gen-emitter, AMDGPU.td, $@)
+AMDGPUGenDFAPacketizer.inc: *.td
+ $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@)
+
LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
loader: loader.o libradeon.a
gcc -o loader -L/usr/local/lib $(LDFLAGS) loader.o libradeon.a $(LLVM_LIBS) $(LOADER_LIBS) -lpthread -ldl -lstdc++ -lm
AMDGPUGenSubtargetInfo.inc \
AMDGPUGenEDInfo.inc \
AMDGPUGenIntrinsics.inc \
- AMDGPUGenCodeEmitter.inc
+ AMDGPUGenCodeEmitter.inc \
+ AMDGPUGenDFAPacketizer.inc
CPP_SOURCES := \
AMDIL7XXDevice.cpp \
TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
{
setOperationAction(ISD::MUL, MVT::i64, Expand);
-// setSchedulingPreference(Sched::VLIW);
addRegisterClass(MVT::v4f32, &AMDIL::R600_Reg128RegClass);
addRegisterClass(MVT::f32, &AMDIL::R600_Reg32RegClass);
addRegisterClass(MVT::v4i32, &AMDIL::R600_Reg128RegClass);
setOperationAction(ISD::FSUB, MVT::f32, Expand);
+ setSchedulingPreference(Sched::VLIW);
}
MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
#include "R600InstrInfo.h"
#include "AMDGPUTargetMachine.h"
+#include "AMDILSubtarget.h"
#include "R600RegisterInfo.h"
+#define GET_INSTRINFO_CTOR
+#include "AMDGPUGenDFAPacketizer.inc"
+
using namespace llvm;
R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
return true;
}
}
+
+DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
+ const ScheduleDAG *DAG) const
+{
+ const InstrItineraryData *II = TM->getInstrItineraryData();
+ return TM->getSubtarget<AMDILSubtarget>().createDFAPacketizer(II);
+}
namespace llvm {
class AMDGPUTargetMachine;
+ class DFAPacketizer;
+ class ScheduleDAG;
class MachineFunction;
class MachineInstr;
class MachineInstrBuilder;
virtual unsigned getIEQOpcode() const;
virtual bool isMov(unsigned Opcode) const;
+
+ DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
+ const ScheduleDAG *DAG) const;
};
} // End llvm namespace
def ALU_W : FuncUnit;
def TRANS : FuncUnit;
-
def AnyALU : InstrItinClass;
def VecALU : InstrItinClass;
def TransALU : InstrItinClass;
def R600_EG_Itin : ProcessorItineraries <
- [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS],
+ [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
[],
[
InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>,
- InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>
+ InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
+ InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
]
>;
projects / mesa.git / commitdiff