;; complex forms. Basic data transfer is done later.
(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
+ (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
+ (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))]
""
"andil. %0,%1,255"
[(set_attr "type" "compare")])
(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "gen_reg_operand" "")
- (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
+ [(set (match_operand:HI 0 "gpc_reg_operand" "")
+ (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
- [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
""
"@
[(set_attr "type" "load,*")])
(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "r")
- (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "r")
+ (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+ (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+ (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))]
""
"andil. %0,%1,65535"
[(set_attr "type" "compare")])
(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+ (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+ (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_dup 1)))]
""
"exts. %0,%1"
\f
;; Fixed-point arithmetic insns.
(define_insn "addsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
(match_operand:SI 2 "add_operand" "rI,J")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"a%I2. %0,%1,%2"
;; add should be last in case the result gets used in an address.
(define_split
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "non_add_cint_operand" "")))]
""
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
}")
(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
""
"sfi %0,%1,-1")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
- (match_operand:SI 2 "gen_reg_operand" "r,r")))]
+ (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
""
"@
sf %0,%2,%1
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
""
"sf. %0,%2,%1"
[(set_attr "type" "compare")])
(define_expand "subsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
""
(define_expand "sminsi3"
[(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
+ (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))]
""
"
(define_expand "smaxsi3"
[(set (match_dup 3)
- (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
+ (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))]
""
"
{ operands[3] = gen_reg_rtx (SImode); }")
(define_expand "uminsi3"
- [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(const_int -2147483648)))
- (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
+ (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
(const_int -2147483648)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0)
(minus:SI (match_dup 4) (match_dup 3))))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))]
""
"
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
(define_expand "umaxsi3"
- [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(const_int -2147483648)))
- (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
+ (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
(const_int -2147483648)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0)
(minus:SI (match_dup 4) (match_dup 3))))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))]
""
"
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))]
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+ (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1)))
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC
- (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+ (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1)))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(if_then_else:SI (gt (match_dup 1) (match_dup 2))
(const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))]
;; We don't need abs with condition code because such comparisons should
;; never be done.
(define_insn "abssi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
""
"abs %0,%1")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
""
"nabs %0,%1")
(define_insn "negsi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
""
"neg %0,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (match_dup 1)))]
""
"neg. %0,%1"
[(set_attr "type" "compare")])
(define_insn "mulsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
(clobber (match_scratch:SI 3 "=q,q"))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))
(clobber (match_scratch:SI 4 "=q"))]
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(mult:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q"))]
""
;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
(define_insn "divmodsi4"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r")))
- (set (match_operand:SI 3 "gen_reg_operand" "=q")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
+ (set (match_operand:SI 3 "gpc_reg_operand" "=q")
(mod:SI (match_dup 1) (match_dup 2)))]
""
"divs %0,%1,%2")
;; For powers of two we can do srai/aze for divide and then adjust for
;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
(define_expand "divsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (div:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
""
"
(define_expand "modsi3"
[(set (match_dup 3)
- (div:SI (match_operand:SI 1 "gen_reg_operand" "")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))
(parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
(clobber (scratch:SI))])
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 1) (match_dup 4)))]
""
"
}")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))]
"exact_log2 (INTVAL (operands[2])) >= 0"
"srai %0,%1,%p2\;aze %0,%0")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))
(clobber (match_scratch:SI 3 "=r"))]
"exact_log2 (INTVAL (operands[2])) >= 0"
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_dup 1) (match_dup 2)))]
"exact_log2 (INTVAL (operands[2])) >= 0"
"srai %0,%1,%p2\;aze. %0,%0"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(udiv:SI
(plus:DI (lshift:DI
- (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 32))
(zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(set (match_operand:SI 4 "register_operand" "=*q")
(umod:SI
(plus:DI (lshift:DI
}")
(define_expand "udivmodsi4"
- [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
- (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))
- (set (match_operand:SI 3 "gen_reg_operand" "")
+ (set (match_operand:SI 3 "gpc_reg_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])]
""
"
}")
(define_insn "andsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
- (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:SI 2 "and_operand" "?r,L,K,J")))
(clobber (match_scratch:CC 3 "=X,X,x,x"))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
- (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:SI 2 "and_operand" "r,K,J,L"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r"))]
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
- (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+ (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
(match_operand:SI 2 "and_operand" "r,K,J,L"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_dup 1) (match_dup 2)))]
""
"@
;; since this need not be done as combine will do it.
(define_split
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (and:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "non_and_cint_operand" "")))]
""
[(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
}")
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
- (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+ (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
(match_operand:SI 2 "logical_operand" "r,K,J")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (match_dup 1) (match_dup 2)))]
""
"or. %0,%1,%2"
;; does one 16-bit part. This is used by combine.
(define_split
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (ior:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "non_logical_cint_operand" "")))]
""
[(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
}")
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
- (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+ (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
(match_operand:SI 2 "logical_operand" "r,K,J")))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(xor:SI (match_dup 1) (match_dup 2)))]
""
"xor. %0,%1,%2"
;; does one 16-bit part. This is used by combine.
(define_split
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "non_logical_cint_operand" "")))]
""
[(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
}")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
- (match_operand:SI 2 "gen_reg_operand" "r"))))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (match_operand:SI 2 "gpc_reg_operand" "r"))))]
""
"eqv %0,%1,%2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
- (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
- (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
""
"eqv. %0,%1,%2"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
""
"andc %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (not:SI (match_dup 1)) (match_dup 2)))]
""
"andc. %0,%2,%1"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r")))]
""
"orc %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
""
"orc. %0,%2,%1"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
""
"nand %0,%1,%2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
""
"nand. %0,%1,%2"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
""
"nor %0,%1,%2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+ (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
""
"nor. %0,%1,%2"
;; would modify an input register.
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))
(and:SI (match_dup 1)
- (match_operand:SI 3 "gen_reg_operand" "r"))))]
+ (match_operand:SI 3 "gpc_reg_operand" "r"))))]
""
"maskir %0,%3,%1")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
- (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))
- (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+ (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))
+ (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 1))))]
""
"maskir %0,%3,%1")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (match_dup 1)
- (match_operand:SI 3 "gen_reg_operand" "r"))
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))))]
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))))]
""
"maskir %0,%3,%1")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 1))
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))))]
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))))]
""
"maskir %0,%3,%1")
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))
+ (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))
(and:SI (match_dup 1)
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
(and:SI (match_dup 1) (match_dup 3))))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0"))
- (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+ (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0"))
+ (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 1)))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
(ior:SI (and:SI (match_dup 1)
- (match_operand:SI 3 "gen_reg_operand" "r"))
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0")))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (match_dup 1) (match_dup 3))
(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+ (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 1))
- (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
- (match_operand:SI 2 "gen_reg_operand" "0")))
+ (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "0")))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (match_dup 3) (match_dup 1))
(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
""
;; Rotate and shift insns, in all their variants. These support shifts,
;; field inserts and extracts, and various combinations thereof.
(define_insn "insv"
- [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "gen_reg_operand" "r"))]
+ (match_operand:SI 3 "gpc_reg_operand" "r"))]
""
"*
{
}")
(define_insn "extzv"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i")))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
(match_operand:SI 3 "const_int_operand" "i"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
""
"*
[(set_attr "type" "delayed_compare")])
(define_insn "rotlsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
""
"rl%I2nm %0,%1,%h2,0,31")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
- (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
- (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(rotate:SI (match_dup 1) (match_dup 2)))]
""
"rl%I2nm. %0,%1,%h2,0,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(match_operand:SI 3 "mask_operand" "L")))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (and:SI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC (and:SI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
""
"rl%I2nm. %0,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI
(subreg:QI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
""
"rl%I2nm %0,%1,%h2,24,31")
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (zero_extend:SI
(subreg:QI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (zero_extend:SI
(subreg:QI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
""
"rl%I2nm. %0,%1,%h2,24,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI
(subreg:HI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
""
"rl%I2nm %0,%1,%h2,16,31")
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (zero_extend:SI
(subreg:HI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (zero_extend:SI
(subreg:HI
- (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
""
"rl%I2nm. %0,%1,%h2,16,31"
;; SHIFT_COUNT_TRUNCATED.
(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
- (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
- (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashift:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))]
""
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))]
"includes_lshift_p (operands[2], operands[3])"
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands[2], operands[3])"
"rlinm. %0,%h1,%h2,%m3,%M3"
;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
;; "sli x,x,0".
(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
- (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))]
""
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))]
"includes_rshift_p (operands[2], operands[3])"
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_rshift_p (operands[2], operands[3])"
"rlinm. %0,%1,%s2,%m3,%M3"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI
(subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm %0,%1,%s2,24,31")
(compare:CC
(zero_extend:SI
(subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(compare:CC
(zero_extend:SI
(subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm. %0,%1,%s2,24,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI
(subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm %0,%1,%s2,16,31")
(compare:CC
(zero_extend:SI
(subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
(compare:CC
(zero_extend:SI
(subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm. %0,%1,%s2,16,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(const_int 1)
- (match_operand:SI 1 "gen_reg_operand" "r"))
- (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
+ (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 31)))]
""
"rrib %0,%1,%2")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(const_int 1)
- (match_operand:SI 1 "gen_reg_operand" "r"))
- (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
+ (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 31)))]
""
"rrib %0,%1,%2")
(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+ [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(const_int 1)
- (match_operand:SI 1 "gen_reg_operand" "r"))
- (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+ (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 1)
(const_int 0)))]
""
"rrib %0,%1,%2")
(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))]
""
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
- (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))]
""
(define_expand "extendqisi2"
[(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+ (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24)))
(clobber (scratch:SI))])
- (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
+ (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))
(clobber (scratch:SI))])]
(define_expand "extendqihi2"
[(parallel [(set (match_dup 2)
- (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+ (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24)))
(clobber (scratch:SI))])
- (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
+ (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))
(clobber (scratch:SI))])]
;; is not guaranteed. Perhaps this should be tightened up at some point.
(define_insn "extendsfdf2"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
""
"*
{
[(set_attr "type" "fp")])
(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
""
"*
{
[(set_attr "type" "fp")])
(define_insn "negsf2"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
""
"fneg %0,%1"
[(set_attr "type" "fp")])
(define_insn "abssf2"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
""
"fabs %0,%1"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
""
"fnabs %0,%1"
[(set_attr "type" "fp")])
(define_insn "addsf3"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fa %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "subsf3"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
- (match_operand:SF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
+ (match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fs %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "mulsf3"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fm %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "divsf3"
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (div:SF (match_operand:SF 1 "gen_reg_operand" "f")
- (match_operand:SF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
+ (match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fd %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f"))
- (match_operand:SF 3 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f"))
+ (match_operand:SF 3 "gpc_reg_operand" "f")))]
""
"fma %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f"))
- (match_operand:SF 3 "gen_reg_operand" "f")))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f"))
+ (match_operand:SF 3 "gpc_reg_operand" "f")))]
""
"fms %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f"))
- (match_operand:SF 3 "gen_reg_operand" "f"))))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f"))
+ (match_operand:SF 3 "gpc_reg_operand" "f"))))]
""
"fnma %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=f")
- (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
- (match_operand:SF 2 "gen_reg_operand" "f"))
- (match_operand:SF 3 "gen_reg_operand" "f"))))]
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+ (match_operand:SF 2 "gpc_reg_operand" "f"))
+ (match_operand:SF 3 "gpc_reg_operand" "f"))))]
""
"fnms %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "negdf2"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
""
"fneg %0,%1"
[(set_attr "type" "fp")])
(define_insn "absdf2"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
""
"fabs %0,%1"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
""
"fnabs %0,%1"
[(set_attr "type" "fp")])
(define_insn "adddf3"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fa %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "subdf3"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
- (match_operand:DF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
+ (match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fs %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "muldf3"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fm %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn "divdf3"
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (div:DF (match_operand:DF 1 "gen_reg_operand" "f")
- (match_operand:DF 2 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
+ (match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fd %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f"))
- (match_operand:DF 3 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f"))
+ (match_operand:DF 3 "gpc_reg_operand" "f")))]
""
"fma %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f"))
- (match_operand:DF 3 "gen_reg_operand" "f")))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f"))
+ (match_operand:DF 3 "gpc_reg_operand" "f")))]
""
"fms %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f"))
- (match_operand:DF 3 "gen_reg_operand" "f"))))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f"))
+ (match_operand:DF 3 "gpc_reg_operand" "f"))))]
""
"fnma %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=f")
- (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
- (match_operand:DF 2 "gen_reg_operand" "f"))
- (match_operand:DF 3 "gen_reg_operand" "f"))))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+ (match_operand:DF 2 "gpc_reg_operand" "f"))
+ (match_operand:DF 3 "gpc_reg_operand" "f"))))]
""
"fnms %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_expand "floatsidf2"
[(set (match_dup 2)
(plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+ (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_dup 3)))
(match_dup 4)))
- (set (match_operand:DF 0 "gen_reg_operand" "")
+ (set (match_operand:DF 0 "gpc_reg_operand" "")
(minus:DF (subreg:DF (match_dup 2) 0)
(match_dup 5)))]
""
(define_expand "floatunssidf2"
[(set (match_dup 2)
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
+ (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
(match_dup 3)))
- (set (match_operand:DF 0 "gen_reg_operand" "")
+ (set (match_operand:DF 0 "gpc_reg_operand" "")
(minus:DF (subreg:DF (match_dup 2) 0)
(match_dup 4)))]
""
;; For the above two cases, we always split.
(define_split
- [(set (match_operand:DI 0 "gen_reg_operand" "")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+ (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "logical_operand" "")))
(match_operand:DI 3 "immediate_operand" "")))]
"reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
}")
(define_insn ""
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (zero_extend:DI
- (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
+ (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "logical_operand" "rKJ")))
(match_operand:DI 3 "immediate_operand" "n")))]
"HOST_BITS_PER_INT == BITS_PER_WORD
"#")
(define_split
- [(set (match_operand:DI 0 "gen_reg_operand" "=")
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+ (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
(match_operand:DI 2 "immediate_operand" "")))]
"reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
&& GET_CODE (operands[2]) == CONST_DOUBLE
}")
(define_insn ""
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
- (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
(match_operand:DI 2 "immediate_operand" "n")))]
"HOST_BITS_PER_INT == BITS_PER_WORD
&& GET_CODE (operands[2]) == CONST_DOUBLE
"#")
(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
""
"
{
}")
(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
""
"
{
}")
(define_expand "trunc_call_rtl"
- [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
+ [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
(use (reg:DF 33))
(parallel [(set (reg:SI 3)
(call (mem:SI (match_operand 2 "" "")) (const_int 0)))
(clobber (scratch:SI))])
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(reg:SI 3))]
""
"
;; Define the DImode operations that can be done in a small number
;; of instructions.
(define_insn "adddi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
- (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
- (match_operand:DI 2 "gen_reg_operand" "r")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
""
"a %L0,%L1,%L2\;ae %0,%1,%2")
(define_insn "subdi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
- (minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
- (match_operand:DI 2 "gen_reg_operand" "r")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
""
"sf %L0,%L2,%L1\;sfe %0,%2,%1")
(define_insn "negdi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
- (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
""
"sfi %L0,%L1,0\;sfze %0,%1")
(define_insn "mulsidi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=r")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+ (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
(clobber (match_scratch:SI 3 "=q"))]
""
"mul %0,%1,%2\;mfmq %L0")
;; operands 0 and 1 (the usual case) can be in the same register. That's
;; why we have the strange constraints below.
(define_insn "ashldi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
- (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
+ (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
(match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
(clobber (match_scratch:SI 3 "=X,q,q,q"))]
""
sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
(define_insn "lshrdi3"
- [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r")
- (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
+ (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
(match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
(clobber (match_scratch:SI 3 "=X,q,q,q"))]
""
;; just handle shifts by constants.
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
- (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
+ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_scratch:SI 3 ""))])]
""
}")
(define_insn ""
- [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
- (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "M,i")))
(clobber (match_scratch:SI 3 "=X,q"))]
""
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
- "gen_reg_operand (operands[0], SImode)
- || gen_reg_operand (operands[1], SImode)"
+ "gpc_reg_operand (operands[0], SImode)
+ || gpc_reg_operand (operands[1], SImode)"
"@
ai %0,%1,0
l%U1%X1 %0,%1
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
""
"ai. %0,%1,0"
[(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
- "gen_reg_operand (operands[0], HImode)
- || gen_reg_operand (operands[1], HImode)"
+ "gpc_reg_operand (operands[0], HImode)
+ || gpc_reg_operand (operands[1], HImode)"
"@
oril %0,%1,0
lhz%U1%X1 %0,%1
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
- "gen_reg_operand (operands[0], QImode)
- || gen_reg_operand (operands[1], QImode)"
+ "gpc_reg_operand (operands[0], QImode)
+ || gpc_reg_operand (operands[1], QImode)"
"@
oril %0,%1,0
lbz%U1%X1 %0,%1
}")
(define_insn ""
- [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
(match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
"REGNO (operands[0]) <= 31"
"@
[(set_attr "type" "*,load")])
(define_split
- [(set (match_operand:SF 0 "gen_reg_operand" "")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 1 "easy_fp_constant" ""))]
"reload_completed && REGNO (operands[0]) <= 31"
[(set (match_dup 2) (match_dup 3))]
(define_insn ""
[(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
(match_operand:SF 1 "input_operand" "f,m,f"))]
- "gen_reg_operand (operands[0], SFmode)
- || gen_reg_operand (operands[1], SFmode)"
+ "gpc_reg_operand (operands[0], SFmode)
+ || gpc_reg_operand (operands[1], SFmode)"
"@
fmr %0,%1
lfs%U1%X1 %0,%1
}")
(define_insn ""
- [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r")
(match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
"REGNO (operands[0]) <= 31"
"@
[(set_attr "type" "*,load")])
(define_split
- [(set (match_operand:DF 0 "gen_reg_operand" "")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "")
(match_operand:DF 1 "easy_fp_constant" ""))]
"reload_completed && REGNO (operands[0]) <= 31"
[(set (match_dup 2) (match_dup 3))
(define_insn ""
[(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
(match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
- "gen_reg_operand (operands[0], DFmode)
- || gen_reg_operand (operands[1], DFmode)"
+ "gpc_reg_operand (operands[0], DFmode)
+ || gpc_reg_operand (operands[1], DFmode)"
"@
fmr %0,%1
lfd%U1%X1 %0,%1
(define_insn ""
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
(match_operand:DI 1 "input_operand" "r,m,r"))]
- "gen_reg_operand (operands[0], DImode)
- || gen_reg_operand (operands[1], DImode)"
+ "gpc_reg_operand (operands[0], DImode)
+ || gpc_reg_operand (operands[1], DImode)"
"*
{
switch (which_alternative)
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
- "gen_reg_operand (operands[0], TImode)
- || gen_reg_operand (operands[1], TImode)"
+ "gpc_reg_operand (operands[0], TImode)
+ || gpc_reg_operand (operands[1], TImode)"
"*
{
switch (which_alternative)
(define_insn ""
[(match_parallel 0 "load_multiple_operation"
- [(set (match_operand:SI 1 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "indirect_operand" "Q"))])]
""
"*
(define_insn ""
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "indirect_operand" "=Q")
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "=q"))])]
""
"stsi %2,%P1,%O0")
;; that will benefit the most).
(define_insn ""
- [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
- (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
+ (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
stu %3,%2(%1)")
(define_insn ""
- [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
- (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
+ (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
(zero_extend:SI
- (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
(sign_extend:SI
- (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (match_operand:HI 3 "gen_reg_operand" "r,r"))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (match_operand:HI 3 "gpc_reg_operand" "r,r"))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
- (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
+ (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
(zero_extend:SI
- (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (match_operand:QI 3 "gen_reg_operand" "r,r"))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (match_operand:QI 3 "gpc_reg_operand" "r,r"))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
stbu %3,%2(%1)")
(define_insn ""
- [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
- (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
+ (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (match_operand:SF 3 "gen_reg_operand" "f,f"))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (match_operand:SF 3 "gpc_reg_operand" "f,f"))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
frsp %3,%3\;stfsu %3,%2(%1)")
(define_insn ""
- [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
- (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
+ (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "load,load")])
(define_insn ""
- [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+ [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))
- (match_operand:DF 3 "gen_reg_operand" "f,f"))
- (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+ (match_operand:DF 3 "gpc_reg_operand" "f,f"))
+ (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
""
"@
;; operands[1] is the address of data area of the function to call
(define_expand "call_via_ptr"
- [(set (match_operand:SI 0 "gen_reg_operand" "")
- (mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
+ [(set (match_operand:SI 0 "gpc_reg_operand" "")
+ (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
(set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
(reg:SI 2))
(set (reg:SI 2)
;; how it is used.
(define_expand "cmpsi"
[(set (cc0)
- (compare (match_operand:SI 0 "gen_reg_operand" "")
+ (compare (match_operand:SI 0 "gpc_reg_operand" "")
(match_operand:SI 1 "reg_or_short_operand" "")))]
""
"
}")
(define_expand "cmpsf"
- [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
- (match_operand:SF 1 "gen_reg_operand" "")))]
+ [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
+ (match_operand:SF 1 "gpc_reg_operand" "")))]
""
"
{
}")
(define_expand "cmpdf"
- [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
- (match_operand:DF 1 "gen_reg_operand" "")))]
+ [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
+ (match_operand:DF 1 "gpc_reg_operand" "")))]
""
"
{
;; the cases we don't want to handle.
(define_expand "seq"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(eq:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sne"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(ne:SI (match_dup 2) (const_int 0)))]
""
"
;; A > 0 is best done using the portable sequence, so fail in that case.
(define_expand "sgt"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(gt:SI (match_dup 2) (const_int 0)))]
""
"
;; A < 0 is best done in the portable way for A an integer.
(define_expand "slt"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(lt:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sge"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(ge:SI (match_dup 2) (const_int 0)))]
""
"
;; A <= 0 is best done the portable way for A an integer.
(define_expand "sle"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(le:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sgtu"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(gtu:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sltu"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(ltu:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sgeu"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(geu:SI (match_dup 2) (const_int 0)))]
""
"
(define_expand "sleu"
[(set (match_dup 2) (match_dup 1))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(leu:SI (match_dup 2) (const_int 0)))]
""
"
;; Here are the actual compare insns.
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
- (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
""
"cmp%I2 %0,%1,%2"
(define_split
[(set (match_operand:CC 0 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "non_short_cint_operand" "")))
- (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
+ (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
"find_single_use (operands[0], insn, 0)
&& (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
|| GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
(define_insn ""
[(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
- (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
""
"cmpl%I2 %0,%1,%W2"
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=y")
- (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "short_cint_operand" "i")))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
""
"#")
(define_insn ""
[(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
- (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
+ (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "u_short_cint_operand" "i")))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
""
"#")
(define_split
[(set (match_operand:CC 3 "cc_reg_operand" "")
- (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
+ (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "short_cint_operand" "")))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
""
[(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
(define_split
[(set (match_operand:CCUNS 3 "cc_reg_operand" "")
- (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
+ (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "u_short_cint_operand" "")))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
""
[(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
(define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
- (match_operand:SF 2 "gen_reg_operand" "f")))]
+ (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
+ (match_operand:SF 2 "gpc_reg_operand" "f")))]
""
"fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")])
(define_insn ""
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
- (match_operand:DF 2 "gen_reg_operand" "f")))]
+ (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
+ (match_operand:DF 2 "gpc_reg_operand" "f")))]
""
"fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")])
;; cases the insns below which don't use an intermediate CR field will
;; be used instead.
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(match_operator:SI 1 "scc_comparison_operator"
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))]
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)])
(const_int 0)))
- (set (match_operand:SI 3 "gen_reg_operand" "=r")
+ (set (match_operand:SI 3 "gpc_reg_operand" "=r")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
""
"%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)])
(const_int 0)])
(match_operand:SI 3 "const_int_operand" "n"))
(const_int 0)))
- (set (match_operand:SI 4 "gen_reg_operand" "=r")
+ (set (match_operand:SI 4 "gpc_reg_operand" "=r")
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
""
;; so it is useful to combine 2 scc instructions to use only one mfcr.
(define_peephole
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(match_operator:SI 1 "scc_comparison_operator"
[(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))
- (set (match_operand:SI 3 "gen_reg_operand" "=r")
+ (set (match_operand:SI 3 "gpc_reg_operand" "=r")
(match_operator:SI 4 "scc_comparison_operator"
[(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))]
;; the cmp/mfcr sequence we would otherwise generate.
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
- (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+ (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
(compare:CC
- (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+ (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(eq:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
- (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+ (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
- (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
""
"@
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
(compare:CC
(plus:SI
- (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+ (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
- (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
(compare:CC
(plus:SI
- (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+ (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
- (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
- (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+ (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
""
"@
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31))
- (match_operand:SI 2 "gen_reg_operand" "r")))
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))]
""
"ai %3,%1,-1\;aze %0,%2")
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
(plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))]
""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
(plus:SI (lshiftrt:SI
- (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
(match_dup 2)))
(clobber (match_scratch:SI 3 "=&r"))]
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O")))
(clobber (match_scratch:SI 3 "=r,X"))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
(compare:CC
- (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(le:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r,X"))]
""
[(set_attr "type" "delayed_compare,compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))
- (match_operand:SI 3 "gen_reg_operand" "r,r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r")))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
""
"@
ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
""
"sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC
- (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(leu:SI (match_dup 1) (match_dup 2)))]
""
"sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))]
""
"sf%I2 %4,%1,%2\;aze %0,%3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))]
""
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))]
""
"sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
(and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set (match_operand:CC 5 "cc_reg_operand" "=x")
(compare:CC
(and:SI (neg:SI
- (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
""
"doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
(define_insn ""
[(set (match_operand:SI 3 "cc_reg_operand" "=x")
(compare:CC
- (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lt:SI (match_dup 1) (match_dup 2)))]
""
"doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))]
""
"doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
(define_insn ""
[(set (match_operand:SI 0 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))]
""
(define_insn ""
[(set (match_operand:SI 5 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
""
"doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
""
"@
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC
- (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
- (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+ (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
(match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
(clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
(compare:CC
- (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+ (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
(match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
(compare:CC
- (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+ (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
(match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
""
"@
ai %0,%1,%n2\;sfe %0,%0,%0")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
(clobber (match_scratch:SI 3 "=r"))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ge:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))]
""
"doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))]
""
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
""
"doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
;; This is (and (neg (ge X (const_int 0))) Y).
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (neg:SI
(lshiftrt:SI
- (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 31)))
- (match_operand:SI 2 "gen_reg_operand" "r")))
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))]
""
"srai %3,%1,31\;andc %0,%2,%3")
(compare:CC
(and:SI (neg:SI
(lshiftrt:SI
- (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 31)))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))]
""
(compare:CC
(and:SI (neg:SI
(lshiftrt:SI
- (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+ (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 31)))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
(const_int 31)))
(match_dup 2)))
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
""
"@
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC
- (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(geu:SI (match_dup 1) (match_dup 2)))]
""
"@
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
- (match_operand:SI 3 "gen_reg_operand" "r,r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r")))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
"@
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
""
"@
sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (neg:SI
- (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
- (match_operand:SI 3 "gen_reg_operand" "r,r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r")))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
"@
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC
(and:SI (neg:SI
- (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
(compare:CC
(and:SI (neg:SI
- (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
- (match_operand:SI 3 "gen_reg_operand" "r,r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))]
""
"sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC
- (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_dup 1) (const_int 0)))]
""
"sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r")))]
""
"doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC
- (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_dup 1) (match_dup 2)))]
""
"doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
[(set_attr "type" "delayed_compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))
- (match_operand:SI 2 "gen_reg_operand" "r")))
+ (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))]
""
"a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))]
""
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))
- (match_operand:SI 2 "gen_reg_operand" "r"))
+ (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
(clobber (match_scratch:SI 3 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))
- (match_operand:SI 3 "gen_reg_operand" "r")))
+ (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))]
""
"doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))]
""
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x")
(compare:CC
- (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))
- (match_operand:SI 3 "gen_reg_operand" "r"))
+ (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))]
""
"sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))))]
""
"doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC
- (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gtu:SI (match_dup 1) (match_dup 2)))]
""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
- (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+ (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
(match_operand:SI 3 "reg_or_short_operand" "r,I")))
(clobber (match_scratch:SI 4 "=&r,&r"))]
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
(match_operand:SI 3 "reg_or_short_operand" "r,I"))
(const_int 0)))
(define_insn ""
[(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
(compare:CC
- (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+ (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
(match_operand:SI 3 "reg_or_short_operand" "r,I"))
(const_int 0)))
- (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+ (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r"))]
""
[(set_attr "type" "compare")])
(define_insn ""
- [(set (match_operand:SI 0 "gen_reg_operand" "=r")
- (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0")
(define_split
[(set (pc)
(if_then_else (match_operator 2 "comparison_operator"
- [(match_operand:SI 1 "gen_reg_operand" "")
+ [(match_operand:SI 1 "gpc_reg_operand" "")
(const_int 1)])
(match_operand 5 "" "")
(match_operand 6 "" "")))
- (set (match_operand:SI 0 "gen_reg_operand" "")
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:SI 4 ""))]
(define_split
[(set (pc)
(if_then_else (match_operator 2 "comparison_operator"
- [(match_operand:SI 1 "gen_reg_operand" "")
+ [(match_operand:SI 1 "gpc_reg_operand" "")
(const_int 1)])
(match_operand 5 "" "")
(match_operand 6 "" "")))
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 ""))
(clobber (match_scratch:SI 4 ""))]
- "reload_completed && ! gen_reg_operand (operands[0], SImode)"
+ "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
[(parallel [(set (match_dup 3)
(compare:CC (plus:SI (match_dup 1) (const_int -1))
(const_int 0)))