arm.md (generic_sched): Specify xgene1 in 'no' list.

2015-01-15  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>

        * config/arm/arm.md (generic_sched): Specify xgene1 in 'no' list.
        Include xgene1.md.
        * config/arm/arm.c (arm_issue_rate): Specify 4 for xgene1.
        * config/arm/arm-cores.def (xgene1): New entry.
        * config/arm/arm-tables.opt: Regenerate.
        * config/arm/arm-tune.md: Regenerate.
        * config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=xgene1.

From-SVN: r219661

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7b7caf766956e061dc9eb677be757c3df675ccac..21d6a8809f1b598a8b291c3dab6b1ac78eb4458b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2015-01-15  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+       * config/arm/arm.md (generic_sched): Specify xgene1 in 'no' list.
+       Include xgene1.md.
+       * config/arm/arm.c (arm_issue_rate): Specify 4 for xgene1.
+       * config/arm/arm-cores.def (xgene1): New entry.
+       * config/arm/arm-tables.opt: Regenerate.
+       * config/arm/arm-tune.md: Regenerate.
+       * config/arm/bpabi.h (BE8_LINK_SPEC): Specify mcpu=xgene1.
+
 2015-01-15  Yuri Rumyantsev  <ysrumyan@gmail.com>
 
        * tree-if-conv.c: Include hash-map.h.

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index be125ac1aafc9c041af473896e2ffa8cb9707413..fa13eb9d916f17a0b8ac9adbd6936cfaad04f46c 100644 (file)
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -167,6 +167,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,       7A,  FL_LDSCHED |
 /* V8 Architecture Processors */
 ARM_CORE("cortex-a53", cortexa53, cortexa53,   8A, FL_LDSCHED | FL_CRC32, cortex_a53)
 ARM_CORE("cortex-a57", cortexa57, cortexa15,   8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("xgene1",      xgene1,    xgene1,      8A, FL_LDSCHED,            xgene1)
 
 /* V8 big.LITTLE implementations */
 ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_CRC32, cortex_a57)

diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index ece9d5e372353a7df19df6c9e81d8c2ba8690ed8..1392429d74fb92bf3e80f12436834f35e0428bf7 100644 (file)
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -309,6 +309,9 @@ Enum(processor_type) String(cortex-a53) Value(cortexa53)
 EnumValue
 Enum(processor_type) String(cortex-a57) Value(cortexa57)
 
+EnumValue
+Enum(processor_type) String(xgene1) Value(xgene1)
+
 EnumValue
 Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53)
 

diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 452820ab7a334b0f5c5927744e298d8295cd9cf5..dcd505423f68e531f8ff2eaf361a39b8dbf7fa97 100644 (file)
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -32,5 +32,6 @@
        cortexr4f,cortexr5,cortexr7,
        cortexm7,cortexm4,cortexm3,
        marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
-       cortexa53,cortexa57,cortexa57cortexa53"
+       cortexa53,cortexa57,xgene1,
+       cortexa57cortexa53"
        (const (symbol_ref "((enum attr_tune) arm_tune)")))

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a92b0080669f0cb4cf4b89a9cd5638cc28613ee5..a2cce8e36920abbdf048e94e70476071427cccc8 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1912,6 +1912,25 @@ const struct tune_params arm_cortex_a57_tune =
   ARM_FUSE_MOVW_MOVT                           /* Fuseable pairs of instructions.  */
 };
 
+const struct tune_params arm_xgene1_tune =
+{
+  arm_9e_rtx_costs,
+  &xgene1_extra_costs,
+  NULL,                                        /* Scheduler cost adjustment.  */
+  1,                                           /* Constant limit.  */
+  2,                                           /* Max cond insns.  */
+  ARM_PREFETCH_NOT_BENEFICIAL,
+  false,                                       /* Prefer constant pool.  */
+  arm_default_branch_cost,
+  true,                                        /* Prefer LDRD/STRD.  */
+  {true, true},                                /* Prefer non short circuit.  */
+  &arm_default_vec_cost,                       /* Vectorizer costs.  */
+  false,                                       /* Prefer Neon for 64-bits bitops.  */
+  true, true,                                  /* Prefer 32-bit encodings.  */
+  false,                                      /* Prefer Neon for stringops.  */
+  32                                          /* Maximum insns to inline memset.  */
+};
+
 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
    less appealing.  Set max_insns_skipped to a low value.  */
 
@@ -27090,6 +27109,9 @@ arm_issue_rate (void)
 {
   switch (arm_tune)
     {
+    case xgene1:
+      return 4;
+
     case cortexa15:
     case cortexa57:
       return 3;

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index bbefb93a46cd6bf02f723d3de971e916bc4343b5..5e6649a5dd39c58fac66bb26e0ffae32d2b4a6b8 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -109,6 +109,11 @@
 ;; given instruction does not shift one of its input operands.
 (define_attr "shift" "" (const_int 0))
 
+;; [For compatibility with AArch64 in pipeline models]
+;; Attribute that specifies whether or not the instruction touches fp
+;; registers.
+(define_attr "fp" "no,yes" (const_string "no"))
+
 ; Floating Point Unit.  If we only have floating point emulation, then there
 ; is no point in scheduling the floating point insns.  (Well, for best
 ; performance we should try and group them together).
@@ -386,7 +391,8 @@
                                 arm926ejs,arm1020e,arm1026ejs,arm1136js,\
                                 arm1136jfs,cortexa5,cortexa7,cortexa8,\
                                 cortexa9,cortexa12,cortexa15,cortexa17,\
-                                cortexa53,cortexm4,cortexm7,marvell_pj4")
+                                cortexa53,cortexm4,cortexm7,marvell_pj4,\
+                               xgene1")
               (eq_attr "tune_cortexr4" "yes"))
           (const_string "no")
           (const_string "yes"))))
@@ -396,7 +402,7 @@
          (and (eq_attr "fpu" "vfp")
               (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,\
                                 cortexa8,cortexa9,cortexa53,cortexm4,\
-                                cortexm7,marvell_pj4")
+                                cortexm7,marvell_pj4,xgene1")
               (eq_attr "tune_cortexr4" "no"))
          (const_string "yes")
          (const_string "no"))))
@@ -426,6 +432,7 @@
 (include "cortex-m4-fpu.md")
 (include "vfp11.md")
 (include "marvell-pj4.md")
+(include "xgene1.md")
 
 \f
 ;;---------------------------------------------------------------------------

diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 6e69b8149f1d89702eaec9e49c0b6d845e6dc18a..8e164340ac7540c8a4ccc6611e24ea156577c423 100644 (file)
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -71,6 +71,7 @@
    |mcpu=cortex-a53                                    \
    |mcpu=cortex-a57                                    \
    |mcpu=cortex-a57.cortex-a53                         \
+   |mcpu=xgene1                                         \
    |mcpu=cortex-m1.small-multiply                       \
    |mcpu=cortex-m0.small-multiply                       \
    |mcpu=cortex-m0plus.small-multiply                  \
@@ -92,6 +93,7 @@
    |mcpu=cortex-a53                                    \
    |mcpu=cortex-a57                                    \
    |mcpu=cortex-a57.cortex-a53                         \
+   |mcpu=xgene1                                         \
    |mcpu=cortex-m1.small-multiply                       \
    |mcpu=cortex-m0.small-multiply                       \
    |mcpu=cortex-m0plus.small-multiply                   \

diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm
index df97a13d73cc7967d8542ebdb6d737206bdf779b..4ef38a87f013a0bc3e4b41bc3eda8dcd573caa3b 100644 (file)
--- a/gcc/config/arm/t-arm
+++ b/gcc/config/arm/t-arm
@@ -40,6 +40,7 @@ MD_INCLUDES=  $(srcdir)/config/arm/arm1020e.md \
                $(srcdir)/config/arm/cortex-a9.md \
                $(srcdir)/config/arm/cortex-a9-neon.md \
                $(srcdir)/config/arm/cortex-a53.md \
+               $(srcdir)/config/arm/xgene1.md \
                $(srcdir)/config/arm/cortex-m4-fpu.md \
                $(srcdir)/config/arm/cortex-m4.md \
                $(srcdir)/config/arm/cortex-r4f.md \

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0f3ce8ecc3e73d69a54cb9e81bbda65ae648496a..96faf0fd5b0971c0466982fa9f5ffd9db8973144 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12979,7 +12979,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{marvell-pj4},
 @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
 @samp{fa526}, @samp{fa626},
-@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
+@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
+@samp{xgene1}.
 
 Additionally, this option can specify that GCC should tune the performance
 of the code for a big.LITTLE system.  Permissible names are: