radv: move vgt_gs_mode value to pipeline.

No need to recalculate this everytime.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ce34204b8ac6943a5b221c904f10ad95a871f593..195a82fef575d155e23e70d3b0907ecde74ce6a1 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -599,27 +599,6 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
 }
 
-static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
-{
-       unsigned gs_max_vert_out = gs->info.gs.vertices_out;
-       unsigned cut_mode;
-
-       if (gs_max_vert_out <= 128) {
-               cut_mode = V_028A40_GS_CUT_128;
-       } else if (gs_max_vert_out <= 256) {
-               cut_mode = V_028A40_GS_CUT_256;
-       } else if (gs_max_vert_out <= 512) {
-               cut_mode = V_028A40_GS_CUT_512;
-       } else {
-               assert(gs_max_vert_out <= 1024);
-               cut_mode = V_028A40_GS_CUT_1024;
-       }
-
-       return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
-              S_028A40_CUT_MODE(cut_mode)|
-              S_028A40_ES_WRITE_OPTIMIZE(1) |
-              S_028A40_GS_WRITE_OPTIMIZE(1);
-}
 
 static void
 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
@@ -629,13 +608,11 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
        struct radv_shader_variant *gs;
        uint64_t va;
 
+       radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
+
        gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
-       if (!gs) {
-               radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, 0);
+       if (!gs)
                return;
-       }
-
-       radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
 
        uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
 

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2c710f4eb8faf5191eddbb4ac7880ca6ebc8137f..752986a9c598dc203b07a3202a814475b5d47df6 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1505,6 +1505,28 @@ static const struct radv_prim_vertex_count prim_size_table[] = {
        [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
 };
 
+static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
+{
+       unsigned gs_max_vert_out = gs->info.gs.vertices_out;
+       unsigned cut_mode;
+
+       if (gs_max_vert_out <= 128) {
+               cut_mode = V_028A40_GS_CUT_128;
+       } else if (gs_max_vert_out <= 256) {
+               cut_mode = V_028A40_GS_CUT_256;
+       } else if (gs_max_vert_out <= 512) {
+               cut_mode = V_028A40_GS_CUT_512;
+       } else {
+               assert(gs_max_vert_out <= 1024);
+               cut_mode = V_028A40_GS_CUT_1024;
+       }
+
+       return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
+              S_028A40_CUT_MODE(cut_mode)|
+              S_028A40_ES_WRITE_OPTIMIZE(1) |
+              S_028A40_GS_WRITE_OPTIMIZE(1);
+}
+
 VkResult
 radv_pipeline_init(struct radv_pipeline *pipeline,
                   struct radv_device *device,
@@ -1559,7 +1581,10 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 
                pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
                calculate_gs_ring_sizes(pipeline);
-       }
+
+               pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
+       } else
+               pipeline->graphics.vgt_gs_mode = 0;
 
        if (!modules[MESA_SHADER_FRAGMENT]) {
                nir_builder fs_b;

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 433cba7d2826ea6dacc2d8902347b7ed61b89eb9..dcd738a54f49c9c3569909c3e5e6d3d2e3b9235d 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -957,6 +957,7 @@ struct radv_pipeline {
                        struct radv_multisample_state ms;
                        unsigned prim;
                        unsigned gs_out;
+                       uint32_t vgt_gs_mode;
                        bool prim_restart_enable;
                        unsigned esgs_ring_size;
                        unsigned gsvs_ring_size;