add 3-way bridge phy

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index d3825489f2da2ab306c7443ee3a4130bbfe9009c..a4a11cae69176cfaced6f155d97aca319a29931d 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -808,10 +808,23 @@ execute the exact same ISA (or a subset of it). If however the
 concept of Hybrid PE-Memory Processing were to become a JEDEC Standard,
 which would increase adoption and reduce cost, a bit more thought
 is required here because ARM or Intel or MIPS might not necessarily
-be happy that a Processing Element has to execute Power ISA binaries.
+be happy that a Processing Element (PE) has to execute Power ISA binaries.
 At least the Power ISA is much richer, more powerful, still RISC,
 and is an Open Standard, as discussed in a earlier sections.
 
+A reasonable compromise in this regard however is illustrated with
+the following diagram: a 3-way Bridge PHY that allows for full
+direct interaction between DRAM ICs, PEs, and one or more main CPUs
+(* a variant of the Northbridge and/or IBM POWER10 OMI-to-DDR5 PHY concept*).
+It is also the ideal location for a "Management Core"
+There is also no reason why this type of arrangement should not be deployed
+in Multi-Chip-Module (aka "Chiplet") form, giving all the advantages of
+the performance boost that goes with smaller line-drivers.
+
+Draft Image (placeholder):
+
+<img src="/openpower/sv/bridge_phy.jpg" width=800 />
+
 # Transparently-Distributed Vector Processing
 
 It is very strange to the author to be describing what amounts to a

diff --git a/openpower/sv/bridge_phy.jpg b/openpower/sv/bridge_phy.jpg
new file mode 100644 (file)
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