+2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
+ * testsuite/gas/mips/r6-reg-constraints.s: this and add test
+ case for DAUI.
+ * testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
+ * testsuite/gas/mips/r6-reg-constraints.l: this and add test
+ for DAUI.
+ * testsuite/gas/mips/mips.exp: Rename test from
+ r6-branch-constraints to r6-reg-constraints.
+
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24559
run_list_test_arches "r6-removed" "-32" [mips_arch_list_matching mips32r6]
run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6]
- run_list_test_arches "r6-branch-constraints" "-32" \
+ run_list_test_arches "r6-reg-constraints" "-32" \
[mips_arch_list_matching mips32r6]
run_dump_test_arches "crc" [mips_arch_list_matching mips32r6]
+++ /dev/null
-.*: Assembler messages:
-.*:2: Error: the source register must not be \$0 `blezc \$0,.'
-.*:3: Error: the source register must not be \$0 `bgezc \$0,.'
-.*:4: Error: the source register must not be \$0 `bgtzc \$0,.'
-.*:5: Error: the source register must not be \$0 `bltzc \$0,.'
-.*:6: Error: the source register must not be \$0 `beqzc \$0,.'
-.*:7: Error: the source register must not be \$0 `bnezc \$0,.'
-.*:8: Error: the source register must not be \$0 `bgec \$0,\$2,.'
-.*:9: Error: invalid operands `bgec \$2,\$0,.'
-.*:10: Error: invalid operands `bgec \$2,\$2,.'
-.*:11: Error: the source register must not be \$0 `bgeuc \$0,\$2,.'
-.*:12: Error: invalid operands `bgeuc \$2,\$0,.'
-.*:13: Error: invalid operands `bgeuc \$2,\$2,.'
-.*:14: Error: the source register must not be \$0 `bltc \$0,\$2,.'
-.*:15: Error: invalid operands `bltc \$2,\$0,.'
-.*:16: Error: invalid operands `bltc \$2,\$2,.'
-.*:17: Error: the source register must not be \$0 `bltuc \$0,\$2,.'
-.*:18: Error: invalid operands `bltuc \$2,\$0,.'
-.*:19: Error: invalid operands `bltuc \$2,\$2,.'
-.*:20: Error: the source register must not be \$0 `beqc \$0,\$2,.'
-.*:21: Error: invalid operands `beqc \$2,\$0,.'
-.*:22: Error: invalid operands `beqc \$2,\$2,.'
-.*:23: Error: the source register must not be \$0 `bnec \$0,\$2,.'
-.*:24: Error: invalid operands `bnec \$2,\$0,.'
-.*:25: Error: invalid operands `bnec \$2,\$2,.'
+++ /dev/null
- .text
- blezc $0,.
- bgezc $0,.
- bgtzc $0,.
- bltzc $0,.
- beqzc $0,.
- bnezc $0,.
- bgec $0,$2,.
- bgec $2,$0,.
- bgec $2,$2,.
- bgeuc $0,$2,.
- bgeuc $2,$0,.
- bgeuc $2,$2,.
- bltc $0,$2,.
- bltc $2,$0,.
- bltc $2,$2,.
- bltuc $0,$2,.
- bltuc $2,$0,.
- bltuc $2,$2,.
- beqc $0,$2,.
- beqc $2,$0,.
- beqc $2,$2,.
- bnec $0,$2,.
- bnec $2,$0,.
- bnec $2,$2,.
--- /dev/null
+.*: Assembler messages:
+.*:2: Error: the source register must not be \$0 `blezc \$0,.'
+.*:3: Error: the source register must not be \$0 `bgezc \$0,.'
+.*:4: Error: the source register must not be \$0 `bgtzc \$0,.'
+.*:5: Error: the source register must not be \$0 `bltzc \$0,.'
+.*:6: Error: the source register must not be \$0 `beqzc \$0,.'
+.*:7: Error: the source register must not be \$0 `bnezc \$0,.'
+.*:8: Error: the source register must not be \$0 `bgec \$0,\$2,.'
+.*:9: Error: invalid operands `bgec \$2,\$0,.'
+.*:10: Error: invalid operands `bgec \$2,\$2,.'
+.*:11: Error: the source register must not be \$0 `bgeuc \$0,\$2,.'
+.*:12: Error: invalid operands `bgeuc \$2,\$0,.'
+.*:13: Error: invalid operands `bgeuc \$2,\$2,.'
+.*:14: Error: the source register must not be \$0 `bltc \$0,\$2,.'
+.*:15: Error: invalid operands `bltc \$2,\$0,.'
+.*:16: Error: invalid operands `bltc \$2,\$2,.'
+.*:17: Error: the source register must not be \$0 `bltuc \$0,\$2,.'
+.*:18: Error: invalid operands `bltuc \$2,\$0,.'
+.*:19: Error: invalid operands `bltuc \$2,\$2,.'
+.*:20: Error: the source register must not be \$0 `beqc \$0,\$2,.'
+.*:21: Error: invalid operands `beqc \$2,\$0,.'
+.*:22: Error: invalid operands `beqc \$2,\$2,.'
+.*:23: Error: the source register must not be \$0 `bnec \$0,\$2,.'
+.*:24: Error: invalid operands `bnec \$2,\$0,.'
+.*:25: Error: invalid operands `bnec \$2,\$2,.'
+.*:26: Error: the source register must not be \$0 `daui \$2,\$0,1'
--- /dev/null
+ .text
+ blezc $0,.
+ bgezc $0,.
+ bgtzc $0,.
+ bltzc $0,.
+ beqzc $0,.
+ bnezc $0,.
+ bgec $0,$2,.
+ bgec $2,$0,.
+ bgec $2,$2,.
+ bgeuc $0,$2,.
+ bgeuc $2,$0,.
+ bgeuc $2,$2,.
+ bltc $0,$2,.
+ bltc $2,$0,.
+ bltc $2,$2,.
+ bltuc $0,$2,.
+ bltuc $2,$0,.
+ bltuc $2,$2,.
+ beqc $0,$2,.
+ beqc $2,$0,.
+ beqc $2,$2,.
+ bnec $0,$2,.
+ bnec $2,$0,.
+ bnec $2,$2,.
+ daui $2,$0,1
+2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Change source register
+ constraint for DAUI.
+
2019-05-20 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
/* MIPS r6. */
{"aui", "t,s,u", 0x3c000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 },
{"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 },
-{"daui", "t,s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 },
+{"daui", "t,-s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 },
{"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 },
{"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 },