[binutils][aarch64] New sve_size_013 iclass.

Add sve_size_013 instruction class

This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
	sve_size_013 iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_size_013 iclass decode.

diff --git a/include/ChangeLog b/include/ChangeLog
index 28e00bfcec8b4c102fbb4d77e6dff129ffb8153a..600e753f060e9dbc31a3d96c00ff18f30d2eed5a 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 0df8bddfd1ce9c8d71f9491f3d7db70066e510ce..9cc73cad223c09a1af074abbe0603db7774bd322 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -596,6 +596,7 @@ enum aarch64_insn_class
   sve_size_sd,
   sve_size_bh,
   sve_size_sd2,
+  sve_size_013,
   testbranch,
   cryptosm3,
   cryptosm4,

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0f28ced24dbfda00e23ca5ac880700b68574067..a8051cd500228fc5e15f57dbf8ad1e8fdb92ed13 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+       sve_size_013 iclass encode.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+       sve_size_013 iclass decode.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
        * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 674eba5e9d31e9004ad1e71320ee2788e8c791ce..0ec27b24928fac0b3325c9d4817152236d0bf698 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1613,6 +1613,7 @@ do_special_encoding (struct aarch64_inst *inst)
 static void
 aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
 {
+  int variant = 0;
   switch (inst->opcode->iclass)
     {
     case sve_cpy:
@@ -1669,6 +1670,13 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
                    aarch64_get_variant (inst) + 1, 0);
       break;
 
+    case sve_size_013:
+      variant = aarch64_get_variant (inst);
+      if (variant == 2)
+         variant = 3;
+      insert_field (FLD_size, &inst->value, variant, 0);
+      break;
+
     default:
       break;
     }

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index bfc47b4c1b80f672e12ead2fe89f2d33bfe8ca47..1a727a4ba848965113debe6b488ecba59733605a 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2822,6 +2822,16 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = i - 1;
       break;
 
+    case sve_size_013:
+      i = extract_field (FLD_size, inst->value, 0);
+      if (i == 2)
+       return FALSE;
+      if (i == 3)
+       variant = 2;
+      else
+       variant = i;
+      break;
+
     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;