Update scripts for testing ALPHA_FS and MIPS_SE.

Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.

configs/test/fs.py:
    Port to new script interface/model.
configs/test/test.py:
    Add support for running MIPS test(s) too via
    command-line option.
src/arch/alpha/ev5.cc:
    Fix include file.
src/arch/sparc/regfile.hh:
    Make Bit64 a ULL constant to avoid compiler error.

--HG--
extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624

diff --git a/configs/test/fs.py b/configs/test/fs.py
index fdbf86abef1f69c6a4820bd1bd9a5404fba9a0c3..05b38991c03a6a0b72968fce8449ce4247f77019 100644 (file)
--- a/configs/test/fs.py
+++ b/configs/test/fs.py
@@ -1,7 +1,18 @@
-from m5 import *
+import m5
+from m5.objects import *
 import os
 from SysPaths import *
 
+parser = optparse.OptionParser(option_list=m5.standardOptions)
+
+parser.add_option("-t", "--timing", action="store_true")
+
+(options, args) = parser.parse_args()
+
+if args:
+    print "Error: script doesn't take any positional arguments"
+    sys.exit(1)
+
 # Base for tests is directory containing this file.
 test_base = os.path.dirname(__file__)
 
@@ -181,7 +192,11 @@ class LinuxAlphaSystem(LinuxAlphaSystem):
                              read_only=True)
     simple_disk = SimpleDisk(disk=Parent.raw_image)
     intrctrl = IntrControl()
-    cpu = AtomicSimpleCPU(mem=Parent.magicbus2)
+    if options.timing:
+        cpu = TimingSimpleCPU()
+    else:
+        cpu = AtomicSimpleCPU()
+    cpu.mem = Parent.magicbus2
     sim_console = SimConsole(listener=ConsoleListener(port=3456))
     kernel = binary('vmlinux')
     pal = binary('ts_osfpal')
@@ -213,3 +228,8 @@ def DualRoot(ClientSystem, ServerSystem):
 root = DualRoot(ClientSystem = LinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
                 ServerSystem = LinuxAlphaSystem(readfile=script('netperf-server.rcS')))
 
+m5.instantiate(root)
+
+exit_event = m5.simulate()
+
+print 'Exiting @', m5.curTick(), 'because', exit_event.getCause()

diff --git a/configs/test/test.py b/configs/test/test.py
index 0c6359148696ff666a290e1381a11ba1492b1032..8bdea16ac6eb2b4b8c76dbd964c048c8c8c6a426 100644 (file)
--- a/configs/test/test.py
+++ b/configs/test/test.py
@@ -1,9 +1,17 @@
+# Simple test script
+#
+# Alpha: "m5 test.py"
+# MIPS: "m5 test.py -a Mips -c hello_mips"
+
 import os, optparse, sys
 import m5
 from m5.objects import *
 
+# parse command-line arguments
 parser = optparse.OptionParser(option_list=m5.standardOptions)
 
+parser.add_option("-c", "--cmd", default="hello")
+parser.add_option("-a", "--arch", choices=["Alpha", "Mips"], default="Alpha")
 parser.add_option("-t", "--timing", action="store_true")
 
 (options, args) = parser.parse_args()
@@ -12,11 +20,15 @@ if args:
     print "Error: script doesn't take any positional arguments"
     sys.exit(1)
 
+# build configuration
 this_dir = os.path.dirname(__file__)
 
-process = AlphaLiveProcess()
-process.executable = os.path.join(this_dir, 'hello')
-process.cmd = 'hello'
+print "arch =", options.arch
+process_class = eval(options.arch + "LiveProcess")
+
+process = process_class()
+process.executable = os.path.join(this_dir, options.cmd)
+process.cmd = options.cmd
 
 magicbus = Bus()
 mem = PhysicalMemory()
@@ -32,8 +44,10 @@ system = System(physmem = mem, cpu = cpu)
 system.c1 =  Connector(side_a = mem, side_b = magicbus)
 root = Root(system = system)
 
+# instantiate configuration
 m5.instantiate(root)
 
+# simulate until program terminates
 exit_event = m5.simulate()
 
 print 'Exiting @', m5.curTick(), 'because', exit_event.getCause()

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index dddefeb282ce84312eba365d10c005797bfea815..7d68947332fc12f077e9f9b27fad7c22cb07ca4f 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -41,7 +41,7 @@
 #include "cpu/thread_context.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/debug.hh"
-#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
 
 #if FULL_SYSTEM
 

diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index aaf1fcf2432437541ef5bb5ee0df0c043c8bcaff..760edc41ebb9c1aa59d27a96eab3b32a039aa417 100644 (file)
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -61,8 +61,7 @@ namespace SparcISA
     const int HprStart = 64;
     const int MiscStart = 96;
 
-
-    const uint64_t Bit64 = 0x8000000000000000;
+    const uint64_t Bit64 = (1ULL << 63);
 
     class IntRegFile
     {