cpu/lm32: add missing buses

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index f41345bbc5ac7384af17e2e900784299596274f3..522a0377fffd1d6d4b913c2701265f46cb7b1c22 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -40,6 +40,7 @@ class LM32(CPU):
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
         self.interrupt = Signal(32)
+        self.buses     = [i, d]
 
         # # #