Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes...

src/arch/x86/predecoder.cc:
    Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.

--HG--
extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0

diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index 650f2bfa27f1732240327cb2a663d27cb8a15053..0407ce99b4e02b66c3e086bf3db38f8a97fc635e 100644 (file)
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -69,9 +69,9 @@ namespace AlphaISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst)
         {
-            fetchPC = pc;
+            fetchPC = _fetchPC;
             assert(off == 0);
             ext_inst = inst;
 #if FULL_SYSTEM
@@ -80,13 +80,6 @@ namespace AlphaISA
 #endif
         }
 
-        //Use this to give data to the predecoder. This should be used
-        //when instructions are executed in order.
-        void moreBytes(MachInst machInst)
-        {
-            moreBytes(fetchPC + sizeof(machInst), 0, machInst);
-        }
-
         bool needMoreBytes()
         {
             return true;

diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index a25cce8a736fbfde002ee7650be2217a8d256219..90f768d7355f3e236c828ac694b901c29ffe82ad 100644 (file)
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -66,19 +66,12 @@ namespace MipsISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr currPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
         {
             assert(off == 0);
             emi = inst;
         }
 
-        //Use this to give data to the predecoder. This should be used
-        //when instructions are executed in order.
-        void moreBytes(MachInst machInst)
-        {
-            moreBytes(0, 0, machInst);
-        }
-
         bool needMoreBytes()
         {
             return true;

diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 4a8c9dc4ad3d19b5189386e917d0ecc7d388cf53..38d8fd1a2bb24a9c2e05dbef111c7de309315c17 100644 (file)
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -67,7 +67,7 @@ namespace SparcISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr currPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
         {
             assert(off == 0);
 
@@ -85,13 +85,6 @@ namespace SparcISA
                         << (sizeof(MachInst) * 8));
         }
 
-        //Use this to give data to the predecoder. This should be used
-        //when instructions are executed in order.
-        void moreBytes(MachInst machInst)
-        {
-            moreBytes(0, 0, machInst);
-        }
-
         bool needMoreBytes()
         {
             return true;

diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index c99b0cfb06662d7cec35b527a090bdcb792c46bd..5c98a1831664d183f1fd6919849ac5eac21ce2c6 100644 (file)
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -209,34 +209,38 @@ namespace X86ISA
 
             //Figure out the effective operand size. This can be overriden to
             //a fixed value at the decoder level.
+            int logOpSize;
             if(/*FIXME long mode*/1)
             {
-                if(emi.rex && emi.rex.w)
-                    emi.opSize = 3; // 64 bit operand size
+                if(emi.rex.w)
+                    logOpSize = 3; // 64 bit operand size
                 else if(emi.legacy.op)
-                    emi.opSize = 1; // 16 bit operand size
+                    logOpSize = 1; // 16 bit operand size
                 else
-                    emi.opSize = 2; // 32 bit operand size
+                    logOpSize = 2; // 32 bit operand size
             }
             else if(/*FIXME default 32*/1)
             {
                 if(emi.legacy.op)
-                    emi.opSize = 1; // 16 bit operand size
+                    logOpSize = 1; // 16 bit operand size
                 else
-                    emi.opSize = 2; // 32 bit operand size
+                    logOpSize = 2; // 32 bit operand size
             }
             else // 16 bit default operand size
             {
                 if(emi.legacy.op)
-                    emi.opSize = 2; // 32 bit operand size
+                    logOpSize = 2; // 32 bit operand size
                 else
-                    emi.opSize = 1; // 16 bit operand size
+                    logOpSize = 1; // 16 bit operand size
             }
 
             //Figure out how big of an immediate we'll retreive based
             //on the opcode.
             int immType = ImmediateType[emi.opcode.num - 1][nextByte];
-            immediateSize = SizeTypeToSize[emi.opSize - 1][immType];
+            immediateSize = SizeTypeToSize[logOpSize - 1][immType];
+
+            //Set the actual op size
+            emi.opSize = 1 << logOpSize;
 
             //Determine what to expect next
             if (UsesModRM[emi.opcode.num - 1][nextByte]) {

diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 9b4d36d4ae64e932c65c985766c0cda74ae358f0..0708875c15459a394c3faee9faa2db9b7ed45bcb 100644 (file)
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -192,9 +192,9 @@ namespace X86ISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr currPC, Addr off, MachInst data)
+        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data)
         {
-            basePC = currPC;
+            basePC = fetchPC;
             offset = off;
             fetchChunk = data;
             assert(off < sizeof(MachInst));
@@ -202,13 +202,6 @@ namespace X86ISA
             process();
         }
 
-        //Use this to give data to the predecoder. This should be used
-        //when instructions are executed in order.
-        void moreBytes(MachInst machInst)
-        {
-            moreBytes(basePC + sizeof(machInst), 0, machInst);
-        }
-
         bool needMoreBytes()
         {
             return outOfBytes;

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index ff4617fcc8a40e4a250b80fc08245e3a90783da3..ab55ec7444e9ce5ea46f074e98981c472223ac3f 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                         (&cacheData[tid][offset]));
 
             predecoder.setTC(cpu->thread[tid]->getTC());
-            predecoder.moreBytes(fetch_PC, 0, inst);
+            predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
 
             ext_inst = predecoder.getExtMachInst();
 

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b4371b2c46023d7c231a5f10039d95c18e6de060..b97eabf3341ef290842d50c19f2cfe8b039b9789 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -336,13 +336,12 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
             thread->readNextPC(),thread->readNextNPC());
 #else
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
             thread->readNextPC());
 #endif
 
-    const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
-    Addr fetchPC = threadPC + fetchOffset;
-    req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
+    Addr fetchPC = (threadPC & PCMask) + fetchOffset;
+    req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 
     Fault fault = thread->translateInstReq(req);
 
@@ -381,7 +380,8 @@ BaseSimpleCPU::preExecute()
         predecoder.setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
         if(predecoder.needMoreBytes())
-            predecoder.moreBytes(thread->readPC() + fetchOffset, 0, inst);
+            predecoder.moreBytes(thread->readPC(),
+                    (thread->readPC() & PCMask) + fetchOffset, 0, inst);
         else
             predecoder.process();
 

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b25790e9234ce8e3940d3c277c3de06466e78f4d..d221baca85717ad606f57c777e79479279037867 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -166,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU
         return numInst - startNumInst;
     }
 
+    // Mask to align PCs to MachInst sized boundaries
+    static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
+
     // number of simulated memory references
     Stats::Scalar<> numMemRefs;