re PR target/62120 ([ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be...

Fix PR 62120.

gcc/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * varasm.c (decode_reg_name_and_count): Check availability for
       registers from ADDITIONAL_REGISTER_NAMES.

testsuite/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
       in 32-bit mode.
       * gcc.target/i386/pr62120.c: New.

From-SVN: r215729

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8795f320cde6e732a0d6d52b20d7cd4c288b1449..c2840ae0f21ecf3d63576bdb20853570f0a4649a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR middle-end/62120
+       * varasm.c (decode_reg_name_and_count): Check availability for
+       registers from ADDITIONAL_REGISTER_NAMES.
+
 2014-09-30  David Malcolm  <dmalcolm@redhat.com>
 
        PR plugins/63410

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e2963e19fb7094dd83e243f35f3ff64448100c0a..858df23c8ee1f5a6f1ba17334bff8648c412fbf6 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>
+
+       PR middle-end/62120
+       * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
+       in 32-bit mode.
+       * gcc.target/i386/pr62120.c: New. 
+
 2014-09-30  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: New.

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
index 164a1deb08eca152e461bb9886b30540deb30b87..e5ee08bcbd2deb768d4cb88bbf3da71df20f50a8 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
@@ -3,7 +3,7 @@
 
 void foo ()
 {
-  register int zmm_var asm ("zmm9") __attribute__((unused));
+  register int zmm_var asm ("zmm6") __attribute__((unused));
 
   __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" );
 }

diff --git a/gcc/testsuite/gcc.target/i386/pr62120.c b/gcc/testsuite/gcc.target/i386/pr62120.c
new file mode 100644 (file)
index 0000000..bfb8c47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr62120.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+
+void foo ()
+{
+  register int zmm_var asm ("ymm9");/* { dg-error "invalid register name" } */
+  register int zmm_var2 asm ("23");/* { dg-error "invalid register name" } */
+}

diff --git a/gcc/varasm.c b/gcc/varasm.c
index dd3211a2c5c37ae6a8de546e949decd921e90c24..0b99b39c1b87f5b518fe562e7a57e2f1d91e343a 100644 (file)
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -888,7 +888,7 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs)
       if (asmspec[0] != 0 && i < 0)
        {
          i = atoi (asmspec);
-         if (i < FIRST_PSEUDO_REGISTER && i >= 0)
+         if (i < FIRST_PSEUDO_REGISTER && i >= 0 && reg_names[i][0])
            return i;
          else
            return -2;
@@ -925,7 +925,8 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs)
 
        for (i = 0; i < (int) ARRAY_SIZE (table); i++)
          if (table[i].name[0]
-             && ! strcmp (asmspec, table[i].name))
+             && ! strcmp (asmspec, table[i].name)
+             && reg_names[table[i].number][0])
            return table[i].number;
       }
 #endif /* ADDITIONAL_REGISTER_NAMES */