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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 5b34179a1e238dca4afcd04fdab2586c650fb42a..a7f3a0bc24635521b6d2ff1b89915f0072edd037 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -22,9 +22,10 @@ This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
 Vectorisation Concept that may be applied to **all and any** suitable
 Scalar instructions, present and future, in the Scalar Power ISA.
 **It is not a Traditional Vector ISA and therefore does not add Vector opcodes of any kind**.
-A variant of Simple-V was originally invented in 1994 by Peter Hsu
+
+An ISA Concept similar to Simple-V was originally invented in 1994 by Peter Hsu
 (Architect of the MIPS R8000) but was dropped as MIPS did not have an
-Out-of-Order Microarchitecture.
+Out-of-Order Microarchitecture on which to best exploit it.
 
 Simple-V is designed for Embedded Scenarios right the way through
 Audio/Visual DSPs to 3D GPUs and Supercomputing.  As it does **not**
@@ -59,6 +60,33 @@ to not overburden implementors with features that they do not need.
 The resources below therefore are not all required for all SV Compliancy Levels but
 they are all required to be reserved.
 
+# Hardware Implementations
+
+The fundamental principle of Simple-V is that it sits between Issue and Decode,
+pausing the Program-Counter to service a "Sub-Program-Counter" hardware for-loop.
+In practical terms for many first-iteration implementations this is sufficient.
+
+**Considerable** effort has been expended to ensure that Simple-V is practical
+to implement on an extremely wide range of Industry-wide common **Scalar**
+micro-architectures.
+Finite State Machine (for ultra-low-resource and Mission-Critical), In-order
+single-issue, all the way through to Great-Big Out-of-Order Superscalar Multi-Issue,
+and the SV Compliancy Levels specifically recognise these differing scenarios.the
+
+SIMD back-end ALUs particularly those with element-level predicate masks may be
+exploited to good effect with very little additional complexity to achieve high
+throughput, even on a single-issue in-order microarchitecture. As usually becomes
+apparent with in-order, its limitations extend also to when Simple-V is deployed,
+which is why Multi-Issue Out-of-Order is the recommended (but not mandatory)
+Micro-architecture.
+
+The only major concern is in the upper SV Compliancy Levels:
+the Hazard Management for increased number of Scalar Registers
+to 128 (in current versions) but given that IBM POWER9/10 has VSX register numbering 64,
+and modern GPUs have 128, 256 amd even 512 registers this was deemed acceptable. Strategies
+do exist in hardware for Hazard Management of such large numbers of registers,
+even for Multi-Issue microarchitectures.
+
 # Simple-V Architectural Resources
 
 * No new Interrupt types are required.