add LD-half-swap for i-DCT which does not work. redesign needed
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 1 Aug 2021 09:30:53 +0000 (10:30 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 1 Aug 2021 09:30:53 +0000 (10:30 +0100)
openpower/isa/simplev.mdwn
src/openpower/decoder/isa/remap_dct_yield.py
src/openpower/decoder/isa/test_caller_svp64_ldst.py

index 56b67d22eee600992e4e3481ebb5c92f150488a8..0ad1da1bd5a5bcb07fb4f9c0548c45535f4425b9 100644 (file)
@@ -244,11 +244,13 @@ Pseudo-code:
         # for cos coefficient
         SVSHAPE1[28:29] <- 0b10           # ci schedule
         SVSHAPE2[28:29] <- 0b11           # size schedule
-    # set schedule up for DCT inverse of half-swapped ordering
-    if (SVRM = 0b0110) then
+    # set schedule up for iDCT / DCT inverse of half-swapped ordering
+    if (SVRM = 0b0110) | (SVRM = 0b1110) then
         vlen[0:6] <- (0b00 || SVxd) + 0b0000001
         # set up template in SVSHAPE0
         SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
+        if (SVRM = 0b1110) then
+            SVSHAPE0[18:20] <- 0b001     # DCT opposite half-swap
         SVSHAPE0[30:31] <- 0b01          # DCT/FFT mode
         SVSHAPE0[6:11] <- 0b000101       # DCT "half-swap" mode
     # set VL, MVL and Vertical-First
index f46d9871b142e425cb18565b0e450b99b55663f2..e97f2ec60760b38fc4066b8f7207750480535126 100644 (file)
@@ -48,7 +48,8 @@ def iterate_dct_inner_halfswap_loadstore(SVSHAPE):
     # get indices to iterate over, in the required order
     n = SVSHAPE.lims[0]
     mode = SVSHAPE.lims[1]
-    print ("inner halfswap loadstore", n, mode, SVSHAPE.skip)
+    print ("inner halfswap loadstore", n, mode, SVSHAPE.skip,
+            "submode", SVSHAPE.submode2)
 
     # reference list for not needing to do data-swaps, just swap what
     # *indices* are referenced (two levels of indirection at the moment)
@@ -56,12 +57,15 @@ def iterate_dct_inner_halfswap_loadstore(SVSHAPE):
     ji = list(range(n))
 
     levels = n.bit_length() - 1
-    ji = halfrev2(ji, False)
+    if SVSHAPE.submode2 == 0b001:
+        ji = halfrev2(ji, True)
+    else:
+        ji = halfrev2(ji, False)
+
     if False: # swap: TODO, add extra bit-reverse mode
         ri = [reverse_bits(i, levels) for i in range(n)]
         ji = [ji[ri[i]] for i in range(n)]
 
-
     # invert order if requested
     if SVSHAPE.invxyz[0]:
         ji.reverse()
index 25ae698655142e7999e95b890bfca20d7fc521bc..eee4d51f1fadec110dd7b9b6444c8b8328f377ed 100644 (file)
@@ -483,18 +483,100 @@ class DecoderTestCase(FHDLTestCase):
             # from STs
             for i in range(len(avi)):
                 print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
+            for i in range(len(avi)):
+                self.assertEqual(sim.gpr(i+4), avi[i])
+            # combination of bit-reversed load with a DCT half-swap REMAP
+            # schedule
+            for i in range(len(avi)):
+                print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
+            for i in range(len(avi)):
+                self.assertEqual(sim.gpr(i+12), av[i])
+
+    def test_sv_load_store_bitreverse_remap_halfswap_idct(self):
+        """>>> lst = ["addi 1, 0, 0x0010",
+                        "addi 2, 0, 0x0000",
+                        "addi 4, 0, 0x101",
+                        "addi 5, 0, 0x202",
+                        "addi 6, 0, 0x303",
+                        "addi 7, 0, 0x404",
+                        "addi 8, 0, 0x505",
+                        "addi 9, 0, 0x606",
+                        "addi 10, 0, 0x707",
+                        "addi 11, 0, 0x808",
+                        "sv.stw 5.v, 0(1)",
+                        "svshape 8, 1, 1, 6, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
+                        "sv.lwzbr 12.v, 4(1), 2"]
+
+        bitreverse LD is computed as:
+        for i in range(VL):
+            EA = (RA|0) + (EXTS(D) * LDSTsize * bitreverse(i, VL)) << RC
+
+        bitreversal of 0 1 2 3 in binary 0b00 0b01 0b10 0b11
+        produces       0 2 1 3 in binary 0b00 0b10 0b01 0b11
+
+        and thus creates the butterfly needed for one iteration of FFT.
+        the RC (shift) is to be able to offset the LDs by Radix-2 spans
+
+        on top of the bit-reversal is a REMAP for half-swaps for DCT
+        in-place.
+        """
+        lst = SVP64Asm(["addi 1, 0, 0x0010",
+                        "addi 2, 0, 0x0000",
+                        "addi 4, 0, 0x001",
+                        "addi 5, 0, 0x102",
+                        "addi 6, 0, 0x203",
+                        "addi 7, 0, 0x304",
+                        "addi 8, 0, 0x405",
+                        "addi 9, 0, 0x506",
+                        "addi 10, 0, 0x607",
+                        "addi 11, 0, 0x708",
+                        "sv.stw 4.v, 0(1)",  # scalar r1 + 0 + wordlen*offs
+                        "svshape 8, 1, 1, 14, 0",
+                        "svremap 16, 0, 0, 0, 0, 0, 0, 1",
+                        #"setvl 0, 0, 8, 0, 1, 1",
+                        "sv.lwzbr 12.v, 4(1), 2",  # bit-reversed
+                        #"sv.lwz 12.v, 0(1)"
+                        ])
+        lst = list(lst)
+
+        # SVSTATE (in this case, VL=4)
+        svstate = SVP64State()
+        svstate.vl = 8 # VL
+        svstate.maxvl = 8 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        regs = [0] * 64
+
+        avi = [0x001, 0x102, 0x203, 0x304, 0x405, 0x506, 0x607, 0x708]
+        n = len(avi)
+        levels = n.bit_length() - 1
+        ri = list(range(n))
+        ri = [ri[reverse_bits(i, levels)] for i in range(n)]
+        av = [avi[ri[i]] for i in range(n)]
+        av = halfrev2(av, True)
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate,
+                                                initial_regs=regs)
+            mem = sim.mem.dump(printout=False)
+            print ("Mem")
+            print (mem)
+
+            self.assertEqual(mem, [(16, 0x010200000001),
+                                   (24, 0x030400000203),
+                                   (32, 0x050600000405),
+                                   (40, 0x070800000607)])
+            # from STs
+            for i in range(len(avi)):
+                print ("st gpr", i, sim.gpr(i+4), hex(avi[i]))
+            for i in range(len(avi)):
                 self.assertEqual(sim.gpr(i+4), avi[i])
-            self.assertEqual(sim.gpr(5), SelectableInt(0x102, 64))
-            self.assertEqual(sim.gpr(6), SelectableInt(0x203, 64))
-            self.assertEqual(sim.gpr(7), SelectableInt(0x304, 64))
-            self.assertEqual(sim.gpr(8), SelectableInt(0x405, 64))
-            self.assertEqual(sim.gpr(9), SelectableInt(0x506, 64))
-            self.assertEqual(sim.gpr(10), SelectableInt(0x607, 64))
-            self.assertEqual(sim.gpr(11), SelectableInt(0x708, 64))
             # combination of bit-reversed load with a DCT half-swap REMAP
             # schedule
             for i in range(len(avi)):
                 print ("ld gpr", i, sim.gpr(i+12), hex(av[i]))
+            for i in range(len(avi)):
                 self.assertEqual(sim.gpr(i+12), av[i])
 
     def run_tst_program(self, prog, initial_regs=None,