add sv vectorised predicated beq test

diff --git a/isa/rv64ui/sv_beq.S b/isa/rv64ui/sv_beq.S
new file mode 100644 (file)
index 0000000..2c38e22
--- /dev/null
+++ b/isa/rv64ui/sv_beq.S
@@ -0,0 +1,65 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+
+# SV test: vector-vector add different rd and rs1
+#
+# sets up x6 and x7 with data, sets VL to 2, and carries out
+# an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        li          a3, 0x3
+        li          a4, 0x0
+
+        SET_SV_MVL(2)
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
+       SET_SV_2PREDCSRS(                              \
+                      SV_PRED_CSR(1, 3, 0, 0, 13, 0),  \
+                      SV_PRED_CSR(1, 6, 0, 0, 14, 0) );\
+
+        li          x6, 1
+        li          x7, 1
+
+        li          x3, 1 
+        li          x4, 1
+
+        SET_SV_VL(2)
+
+        beq    x3,x6,here
+here:
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_IMM(a4, 0x3) 
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 41
+        .dword 42
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+