Get rid of unused lock code.

--HG--
extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c1373944d7fbda204e5499ffa2a51a5f4154481e..0da446c9c64bf733b8d55ba4ed702e62d1c54afe 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
     }
 #endif
 
-    /** Old CPU read from memory function. No longer used. */
-    template <class T>
-    Fault read(Request *req, T &data)
-    {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-        if (req->isLocked()) {
-            req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-            req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-        }
-#endif
-        if (req->isLocked()) {
-            lockAddrList.insert(req->paddr);
-            lockFlag = true;
-        }
-#endif
-        Fault error;
-
-        error = this->mem->read(req, data);
-        data = gtoh(data);
-        return error;
-    }
-
-
     /** CPU read function, forwards read to LSQ. */
     template <class T>
     Fault read(Request *req, T &data, int load_idx)
@@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
         return backEnd->read(req, data, load_idx);
     }
 
-    /** Old CPU write to memory function. No longer used. */
-    template <class T>
-    Fault write(Request *req, T &data)
-    {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-        ExecContext *xc;
-
-        // If this is a store conditional, act appropriately
-        if (req->isLocked()) {
-            xc = req->xc;
-
-            if (req->isUncacheable()) {
-                // Don't update result register (see stq_c in isa_desc)
-                req->result = 2;
-                xc->setStCondFailures(0);//Needed? [RGD]
-            } else {
-                bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-                Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-                req->result = lock_flag;
-                if (!lock_flag ||
-                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                    xc->setStCondFailures(xc->readStCondFailures() + 1);
-                    if (((xc->readStCondFailures()) % 100000) == 0) {
-                        std::cerr << "Warning: "
-                                  << xc->readStCondFailures()
-                                  << " consecutive store conditional failures "
-                                  << "on cpu " << req->xc->readCpuId()
-                                  << std::endl;
-                    }
-                    return NoFault;
-                }
-                else xc->setStCondFailures(0);
-            }
-        }
-
-        // Need to clear any locked flags on other proccessors for
-        // this address.  Only do this for succsful Store Conditionals
-        // and all other stores (WH64?).  Unsuccessful Store
-        // Conditionals would have returned above, and wouldn't fall
-        // through.
-        for (int i = 0; i < this->system->threadContexts.size(); i++){
-            xc = this->system->threadContexts[i];
-            if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-                (req->paddr & ~0xf)) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-            }
-        }
-
-#endif
-
-        if (req->isLocked()) {
-            if (req->isUncacheable()) {
-                req->result = 2;
-            } else {
-                if (this->lockFlag) {
-                    if (lockAddrList.find(req->paddr) !=
-                        lockAddrList.end()) {
-                        req->result = 1;
-                    } else {
-                        req->result = 0;
-                        return NoFault;
-                    }
-                } else {
-                    req->result = 0;
-                    return NoFault;
-                }
-            }
-        }
-#endif
-
-        return this->mem->write(req, (T)htog(data));
-    }
-
     /** CPU write function, forwards write to LSQ. */
     template <class T>
     Fault write(Request *req, T &data, int store_idx)

diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8cfc52937ac1d90105919b74a9c9391b..4fd8e02f81e14810b3186ca93b7e6b1b177bf31f 100644 (file)
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
 */
     return fault;
 }
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-    if (req->isLocked()) {
-        req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-        req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-    }
-#endif
-
-    Fault error;
-    error = thread->mem->read(req, data);
-    data = LittleEndianGuest::gtoh(data);
-    return error;
-}
-#endif
 
 template <class Impl>
 template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 */
     return fault;
 }
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
-    ExecContext *xc;
-
-    // If this is a store conditional, act appropriately
-    if (req->isLocked()) {
-        xc = req->xc;
-
-        if (req->isUncacheable()) {
-            // Don't update result register (see stq_c in isa_desc)
-            req->result = 2;
-            xc->setStCondFailures(0);//Needed? [RGD]
-        } else {
-            bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-            Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-            req->result = lock_flag;
-            if (!lock_flag ||
-                ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                xc->setStCondFailures(xc->readStCondFailures() + 1);
-                if (((xc->readStCondFailures()) % 100000) == 0) {
-                    std::cerr << "Warning: "
-                              << xc->readStCondFailures()
-                              << " consecutive store conditional failures "
-                              << "on cpu " << req->xc->readCpuId()
-                              << std::endl;
-                }
-                return NoFault;
-            }
-            else xc->setStCondFailures(0);
-        }
-    }
-
-    // Need to clear any locked flags on other proccessors for
-    // this address.  Only do this for succsful Store Conditionals
-    // and all other stores (WH64?).  Unsuccessful Store
-    // Conditionals would have returned above, and wouldn't fall
-    // through.
-    for (int i = 0; i < cpu->system->execContexts.size(); i++){
-        xc = cpu->system->execContexts[i];
-        if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-            (req->paddr & ~0xf)) {
-            xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-        }
-    }
-
-#endif
-    return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
 
 template <class Impl>
 template <class T>

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e8757c8c20b67e56de3f5f7953c83b7459f884cf..10bbe292c9167b8bc1e2a10e9e589c4dab2a4e02 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -232,75 +232,6 @@ class SimpleThread : public ThreadState
     /// Set the status to Halted.
     void halt();
 
-/*
-    template <class T>
-    Fault read(RequestPtr &req, T &data)
-    {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
-        if (req->isLocked()) {
-            req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
-            req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
-        }
-#endif
-
-        Fault error;
-        error = mem->prot_read(req->paddr, data, req->size);
-        data = LittleEndianGuest::gtoh(data);
-        return error;
-    }
-
-    template <class T>
-    Fault write(RequestPtr &req, T &data)
-    {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
-        ExecContext *xc;
-
-        // If this is a store conditional, act appropriately
-        if (req->isLocked()) {
-            xc = req->xc;
-
-            if (req->isUncacheable()) {
-                // Don't update result register (see stq_c in isa_desc)
-                req->result = 2;
-                xc->setStCondFailures(0);//Needed? [RGD]
-            } else {
-                bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
-                Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
-                req->result = lock_flag;
-                if (!lock_flag ||
-                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-                    xc->setStCondFailures(xc->readStCondFailures() + 1);
-                    if (((xc->readStCondFailures()) % 100000) == 0) {
-                        std::cerr << "Warning: "
-                                  << xc->readStCondFailures()
-                                  << " consecutive store conditional failures "
-                                  << "on cpu " << req->xc->readCpuId()
-                                  << std::endl;
-                    }
-                    return NoFault;
-                }
-                else xc->setStCondFailures(0);
-            }
-        }
-
-        // Need to clear any locked flags on other proccessors for
-        // this address.  Only do this for succsful Store Conditionals
-        // and all other stores (WH64?).  Unsuccessful Store
-        // Conditionals would have returned above, and wouldn't fall
-        // through.
-        for (int i = 0; i < system->execContexts.size(); i++){
-            xc = system->execContexts[i];
-            if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
-                (req->paddr & ~0xf)) {
-                xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
-            }
-        }
-
-#endif
-        return mem->prot_write(req->paddr, (T)htog(data), req->size);
-    }
-*/
     virtual bool misspeculating();
 
     Fault instRead(RequestPtr &req)