from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
from m5.objects.BaseTLB import BaseTLB
+from m5.objects.ClockedObject import ClockedObject
# Basic stage 1 translation objects
-class ArmTableWalker(MemObject):
+class ArmTableWalker(ClockedObject):
type = 'ArmTableWalker'
cxx_class = 'ArmISA::TableWalker'
cxx_header = "arch/arm/table_walker.hh"
using namespace ArmISA;
TableWalker::TableWalker(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId),
isStage2(p->is_stage2), tlb(NULL),
currState(NULL), pending(false),
fatal("Cannot access table walker port through stage-two walker\n");
}
}
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
TableWalker::WalkerState::WalkerState() :
#include "arch/arm/tlb.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
class ThreadContext;
class TLB;
class Stage2MMU;
-class TableWalker : public MemObject
+class TableWalker : public ClockedObject
{
public:
class WalkerState;
# Ivan Pizarro
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
-class BaseTLB(MemObject):
+class BaseTLB(SimObject):
type = 'BaseTLB'
abstract = True
cxx_header = "arch/generic/tlb.hh"
#define __ARCH_GENERIC_TLB_HH__
#include "base/logging.hh"
-#include "mem/mem_object.hh"
#include "mem/request.hh"
+#include "sim/sim_object.hh"
class ThreadContext;
class BaseMasterPort;
-class BaseTLB : public MemObject
+class BaseTLB : public SimObject
{
protected:
- BaseTLB(const Params *p)
- : MemObject(p)
- {}
+ BaseTLB(const Params *p) : SimObject(p) {}
public:
from m5.proxy import *
from m5.objects.BaseTLB import BaseTLB
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class X86PagetableWalker(MemObject):
+class X86PagetableWalker(ClockedObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
cxx_header = 'arch/x86/pagetable_walker.hh'
if (if_name == "port")
return port;
else
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "base/types.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "params/X86PagetableWalker.hh"
+#include "sim/clocked_object.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
namespace X86ISA
{
- class Walker : public MemObject
+ class Walker : public ClockedObject
{
protected:
// Port for accessing memory
}
Walker(const Params *params) :
- MemObject(params), port(name() + ".port", this),
+ ClockedObject(params), port(name() + ".port", this),
funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
masterId(sys->getMasterId(this)),
numSquashable(params->num_squash_per_cycle),
from m5.proxy import *
from m5.util.fdthelper import *
+from m5.objects.ClockedObject import ClockedObject
from m5.objects.XBar import L2XBar
from m5.objects.InstTracer import InstTracer
from m5.objects.CPUTracers import ExeTracer
-from m5.objects.MemObject import MemObject
from m5.objects.SubSystem import SubSystem
from m5.objects.ClockDomain import *
from m5.objects.Platform import Platform
from m5.objects.RiscvISA import RiscvISA
default_isa_class = RiscvISA
-class BaseCPU(MemObject):
+class BaseCPU(ClockedObject):
type = 'BaseCPU'
abstract = True
cxx_header = "cpu/base.hh"
}
BaseCPU::BaseCPU(Params *p, bool is_checker)
- : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
+ : ClockedObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
_instMasterId(p->system->getMasterId(this, "inst")),
_dataMasterId(p->system->getMasterId(this, "data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
void
BaseCPU::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
using namespace Stats;
else if (if_name == "icache_port")
return getInstPort();
else
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
#include "arch/isa_traits.hh"
#include "arch/microcode_rom.hh"
#include "base/statistics.hh"
-#include "mem/mem_object.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/insttracer.hh"
virtual const char *description() const;
};
-class BaseCPU : public MemObject
+class BaseCPU : public ClockedObject
{
protected:
#include "cpu/checker/cpu_impl.hh"
#include "params/O3Checker.hh"
-class MemObject;
-
template
class Checker<O3CPUImpl>;
class O3ThreadContext;
class Checkpoint;
-class MemObject;
class Process;
struct BaseCPUParams;
#include "debug/Decode.hh"
#include "debug/Fetch.hh"
#include "debug/Quiesce.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/sim_exit.hh"
RubyDirectedTester::RubyDirectedTester(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
directedStartEvent([this]{ wakeup(); }, "Directed tick",
false, Event::CPU_Tick_Pri),
m_requests_to_complete(p->requests_to_complete),
{
if (if_name != "cpuPort") {
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
} else {
if (idx >= static_cast<int>(ports.size())) {
panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
#include <string>
#include <vector>
+#include "mem/packet.hh"
+#include "mem/port.hh"
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/mem_object.hh"
-#include "mem/packet.hh"
#include "params/RubyDirectedTester.hh"
+#include "sim/clocked_object.hh"
class DirectedGenerator;
-class RubyDirectedTester : public MemObject
+class RubyDirectedTester : public ClockedObject
{
public:
class CpuPort : public MasterPort
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
class DirectedGenerator(SimObject):
type = 'DirectedGenerator'
cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
-class RubyDirectedTester(MemObject):
+class RubyDirectedTester(ClockedObject):
type = 'RubyDirectedTester'
cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
cpuPort = VectorMasterPort("the cpu ports")
#include "base/random.hh"
#include "base/statistics.hh"
#include "debug/GarnetSyntheticTraffic.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/request.hh"
}
GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick",
false, Event::CPU_Tick_Pri),
cachePort("GarnetSyntheticTraffic", this),
if (if_name == "test")
return cachePort;
else
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
#include <set>
#include "base/statistics.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "params/GarnetSyntheticTraffic.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
NUM_TRAFFIC_PATTERNS_};
class Packet;
-class GarnetSyntheticTraffic : public MemObject
+class GarnetSyntheticTraffic : public ClockedObject
{
public:
typedef GarnetSyntheticTrafficParams Params;
#
# Authors: Tushar Krishna
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
from m5.params import *
from m5.proxy import *
-class GarnetSyntheticTraffic(MemObject):
+class GarnetSyntheticTraffic(ClockedObject):
type = 'GarnetSyntheticTraffic'
cxx_header = \
"cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh"
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class MemTest(MemObject):
+class MemTest(ClockedObject):
type = 'MemTest'
cxx_header = "cpu/testers/memtest/memtest.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "debug/MemTest.hh"
-#include "mem/mem_object.hh"
#include "sim/sim_exit.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
}
MemTest::MemTest(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
tickEvent([this]{ tick(); }, name()),
noRequestEvent([this]{ noRequest(); }, name()),
noResponseEvent([this]{ noResponse(); }, name()),
if (if_name == "port")
return port;
else
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
void
MemTest::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
using namespace Stats;
#include <unordered_map>
#include "base/statistics.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/MemTest.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/stats.hh"
* both requests and responses, thus checking that the memory-system
* is making progress.
*/
-class MemTest : public MemObject
+class MemTest : public ClockedObject
{
public:
#include "sim/system.hh"
RubyTester::RubyTester(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
checkStartEvent([this]{ wakeup(); }, "RubyTester tick",
false, Event::CPU_Tick_Pri),
_masterId(p->system->getMasterId(this)),
if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
if_name != "cpuDataPort") {
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
} else {
if (if_name == "cpuInstPort") {
if (idx > m_num_inst_only_ports) {
#include <vector>
#include "cpu/testers/rubytest/CheckTable.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
+#include "mem/port.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "params/RubyTester.hh"
+#include "sim/clocked_object.hh"
-class RubyTester : public MemObject
+class RubyTester : public ClockedObject
{
public:
class CpuPort : public MasterPort
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class RubyTester(MemObject):
+class RubyTester(ClockedObject):
type = 'RubyTester'
cxx_header = "cpu/testers/rubytest/RubyTester.hh"
num_cpus = Param.Int("number of cpus / RubyPorts")
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
# Types of Stream Generators.
# Those are orthogonal to the other generators in the TrafficGen
# controllers, or function as a black-box replacement for system
# components that are not yet modelled in detail, e.g. a video engine
# or baseband subsystem in an SoC.
-class BaseTrafficGen(MemObject):
+class BaseTrafficGen(ClockedObject):
type = 'BaseTrafficGen'
abstract = True
cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
using namespace std;
BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams* p)
- : MemObject(p),
+ : ClockedObject(p),
system(p->system),
elasticReq(p->elastic_req),
progressCheck(p->progress_check),
if (if_name == "port") {
return port;
} else {
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
}
void
BaseTrafficGen::init()
{
- MemObject::init();
+ ClockedObject::init();
if (!port.isConnected())
fatal("The port of %s is not connected!\n", name());
#include <tuple>
#include "base/statistics.hh"
-#include "mem/mem_object.hh"
#include "mem/qport.hh"
+#include "sim/clocked_object.hh"
class BaseGen;
class StreamGen;
* system components that are not yet modelled in detail, e.g. a video
* engine or baseband subsystem.
*/
-class BaseTrafficGen : public MemObject
+class BaseTrafficGen : public ClockedObject
{
friend class BaseGen;
#include "cpu/base.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
-#include "mem/mem_object.hh"
#include "sim/process.hh"
class EndQuiesceEvent;
from m5.proxy import *
from m5.util.fdthelper import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class PioDevice(MemObject):
+class PioDevice(ClockedObject):
type = 'PioDevice'
cxx_header = "dev/io_device.hh"
abstract = True
#include "debug/DMA.hh"
#include "debug/Drain.hh"
#include "mem/port_proxy.hh"
+#include "sim/clocked_object.hh"
#include "sim/system.hh"
-DmaPort::DmaPort(MemObject *dev, System *s)
+DmaPort::DmaPort(ClockedObject *dev, System *s)
: MasterPort(dev->name() + ".dma", dev),
device(dev), sys(s), masterId(s->getMasterId(dev)),
sendEvent([this]{ sendDma(); }, dev->name()),
#include "sim/drain.hh"
#include "sim/system.hh"
+class ClockedObject;
+
class DmaPort : public MasterPort, public Drainable
{
private:
public:
/** The device that owns this port. */
- MemObject *const device;
+ ClockedObject *const device;
/** The system that device/port are in. This is used to select which mode
* we are currently operating in. */
public:
- DmaPort(MemObject *dev, System *s);
+ DmaPort(ClockedObject *dev, System *s);
RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag = 0);
}
PioDevice::PioDevice(const Params *p)
- : MemObject(p), sys(p->system), pioPort(this)
+ : ClockedObject(p), sys(p->system), pioPort(this)
{}
PioDevice::~PioDevice()
if (if_name == "pio") {
return pioPort;
}
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
BasicPioDevice::BasicPioDevice(const Params *p, Addr size)
#ifndef __DEV_IO_DEVICE_HH__
#define __DEV_IO_DEVICE_HH__
-#include "mem/mem_object.hh"
#include "mem/tport.hh"
#include "params/BasicPioDevice.hh"
#include "params/PioDevice.hh"
+#include "sim/clocked_object.hh"
class PioDevice;
class System;
* mode we are in, etc is handled by the PioPort so the device doesn't have to
* bother.
*/
-class PioDevice : public MemObject
+class PioDevice : public ClockedObject
{
protected:
System *sys;
#include "arch/x86/intmessage.hh"
#include "arch/x86/x86_traits.hh"
-#include "mem/mem_object.hh"
#include "mem/mport.hh"
#include "params/X86IntLine.hh"
#include "params/X86IntSinkPin.hh"
IntDevice * device;
public:
- IntSlavePort(const std::string& _name, MemObject* _parent,
+ IntSlavePort(const std::string& _name, SimObject* _parent,
IntDevice* dev) :
MessageSlavePort(_name, _parent), device(dev)
{
IntDevice* device;
Tick latency;
public:
- IntMasterPort(const std::string& _name, MemObject* _parent,
+ IntMasterPort(const std::string& _name, SimObject* _parent,
IntDevice* dev, Tick _latency) :
MessageMasterPort(_name, _parent), device(dev), latency(_latency)
{
IntMasterPort intMasterPort;
public:
- IntDevice(MemObject * parent, Tick latency = 0) :
+ IntDevice(SimObject * parent, Tick latency = 0) :
intMasterPort(parent->name() + ".int_master", parent, this, latency)
{
}
configs/example/fs.py --caches --cpu-type=arm_detailed --num-cpus=2
- Gem5 uses Memory Objects (MemObject) derived objects as basic blocks for
+ Gem5 uses Simulation Objects (SimObject) derived objects as basic blocks for
building memory system. They are connected via ports with established
master/slave hierarchy. Data flow is initiated on master port while the
response messages and snoop queries appear on the slave port. The following
- figure shows the hierarchy of Memory Objects used in this document:
+ figure shows the hierarchy of Simulation Objects used in this document:
- \image html "gem5_MS_Fig1.PNG" "Memory Object hierarchy of the model" width=3cm
+ \image html "gem5_MS_Fig1.PNG" "Simulation Object hierarchy of the model" width=3cm
\section gem5_CPU CPU
Load & store buffers (for read and write access) don’t impose any
restriction on the number of active memory accesses. Therefore, the maximum
number of outstanding CPU’s memory access requests is not limited by CPU
- Memory Object but by underlying memory system model.
+ Simulation Object but by underlying memory system model.
<b>Split memory access</b> is implemented.
Data Cache object implements a standard cache structure:
- \image html "gem5_MS_Fig2.PNG" "DCache Memory Object" width=3cm
+ \image html "gem5_MS_Fig2.PNG" "DCache Simulation Object" width=3cm
<b>Cached memory reads</b> that match particular cache tag (with Valid & Read
flags) will be completed (by sending ReadResp to CPU) after a configurable time.
from m5.objects.ClockedObject import ClockedObject
from m5.objects.Device import DmaDevice
-from m5.objects.MemObject import MemObject
from m5.objects.Process import EmulatedDriver
from m5.objects.Bridge import Bridge
from m5.objects.LdsState import LdsState
wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)')
wfSize = Param.Int(64, 'Wavefront size (in work items)')
-class ComputeUnit(MemObject):
+class ComputeUnit(ClockedObject):
type = 'ComputeUnit'
cxx_class = 'ComputeUnit'
cxx_header = 'gpu-compute/compute_unit.hh'
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class LdsState(MemObject):
+class LdsState(ClockedObject):
type = 'LdsState'
cxx_class = 'LdsState'
cxx_header = 'gpu-compute/lds_state.hh'
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import SimObject
if buildEnv['FULL_SYSTEM']:
- class X86PagetableWalker(MemObject):
+ class X86PagetableWalker(SimObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = SlavePort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
-class X86GPUTLB(MemObject):
+class X86GPUTLB(ClockedObject):
type = 'X86GPUTLB'
cxx_class = 'X86ISA::GpuTLB'
cxx_header = 'gpu-compute/gpu_tlb.hh'
allocationPolicy = Param.Bool(True, "Allocate on an access")
accessDistance = Param.Bool(False, "print accessDistance stats")
-class TLBCoalescer(MemObject):
+class TLBCoalescer(ClockedObject):
type = 'TLBCoalescer'
cxx_class = 'TLBCoalescer'
cxx_header = 'gpu-compute/tlb_coalescer.hh'
#include "mem/page_table.hh"
#include "sim/process.hh"
-ComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p),
+ComputeUnit::ComputeUnit(const Params *p) : ClockedObject(p), fetchStage(p),
scoreboardCheckStage(p), scheduleStage(p), execStage(p),
globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0),
cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs),
void
ComputeUnit::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
vALUInsts
.name(name() + ".valu_insts")
#include "gpu-compute/qstruct.hh"
#include "gpu-compute/schedule_stage.hh"
#include "gpu-compute/scoreboard_check_stage.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
+#include "sim/clocked_object.hh"
static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1;
static const int MAX_WIDTH_FOR_MEM_INST = 32;
TLB_HIT_CACHE_HIT
};
-class ComputeUnit : public MemObject
+class ComputeUnit : public ClockedObject
{
public:
FetchStage fetchStage;
{
GpuTLB::GpuTLB(const Params *p)
- : MemObject(p), configAddress(0), size(p->size),
+ : ClockedObject(p), configAddress(0), size(p->size),
cleanupEvent([this]{ cleanup(); }, name(), false,
Event::Maximum_Pri),
exitEvent([this]{ exitCallback(); }, name())
void
GpuTLB::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
localNumTLBAccesses
.name(name() + ".local_TLB_accesses")
#include "base/logging.hh"
#include "base/statistics.hh"
#include "gpu-compute/compute_unit.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/X86GPUTLB.hh"
+#include "sim/clocked_object.hh"
#include "sim/sim_object.hh"
class BaseTLB;
namespace X86ISA
{
- class GpuTLB : public MemObject
+ class GpuTLB : public ClockedObject
{
protected:
friend class Walker;
* the default constructor that works with SWIG
*/
LdsState::LdsState(const Params *params) :
- MemObject(params),
+ ClockedObject(params),
tickEvent(this),
cuPort(name() + ".port", this),
maximumSize(params->size),
#include "enums/MemType.hh"
#include "gpu-compute/misc.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "params/LdsState.hh"
+#include "sim/clocked_object.hh"
class ComputeUnit;
// Local Data Share (LDS) State per Wavefront (contents of the LDS region
// allocated to the WorkGroup of this Wavefront)
-class LdsState: public MemObject
+class LdsState: public ClockedObject
{
protected:
#include "sim/process.hh"
TLBCoalescer::TLBCoalescer(const Params *p)
- : MemObject(p),
+ : ClockedObject(p),
clock(p->clk_domain->clockPeriod()),
TLBProbesPerCycle(p->probesPerCycle),
coalescingWindow(p->coalescingWindow),
void
TLBCoalescer::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
uncoalescedAccesses
.name(name() + ".uncoalesced_accesses")
#include "base/logging.hh"
#include "base/statistics.hh"
#include "gpu-compute/gpu_tlb.hh"
-#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "params/TLBCoalescer.hh"
+#include "sim/clocked_object.hh"
class BaseTLB;
class Packet;
class ThreadContext;
/**
- * The TLBCoalescer is a MemObject sitting on the front side (CPUSide) of
+ * The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of
* each TLB. It receives packets and issues coalesced requests to the
* TLB below it. It controls how requests are coalesced (the rules)
* and the permitted number of TLB probes per cycle (i.e., how many
* coalesced requests it feeds the TLB per cycle).
*/
-class TLBCoalescer : public MemObject
+class TLBCoalescer : public ClockedObject
{
protected:
// TLB clock: will inherit clock from shader's clock period in terms
# Andreas Hansson
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class AbstractMemory(MemObject):
+class AbstractMemory(ClockedObject):
type = 'AbstractMemory'
abstract = True
cxx_header = "mem/abstract_mem.hh"
# Authors: Andreas Hansson
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
# An address mapper changes the packet addresses in going from the
# slave port side of the mapper to the master port side. When the
# necessary range updates. Note that snoop requests that travel from
# the master port (i.e. the memory side) to the slave port are
# currently not modified.
-class AddrMapper(MemObject):
+class AddrMapper(SimObject):
type = 'AddrMapper'
cxx_header = 'mem/addr_mapper.hh'
abstract = True
# Andreas Hansson
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class Bridge(MemObject):
+class Bridge(ClockedObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
from m5.objects.System import System
+from m5.SimObject import SimObject
# The communication monitor will most typically be used in combination
# with periodic dumping and resetting of stats using schedStatEvent
-class CommMonitor(MemObject):
+class CommMonitor(SimObject):
type = 'CommMonitor'
cxx_header = "mem/comm_monitor.hh"
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
-class ExternalMaster(MemObject):
+class ExternalMaster(SimObject):
type = 'ExternalMaster'
cxx_header = "mem/external_master.hh"
# Authors: Andrew Bardsley
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
-class ExternalSlave(MemObject):
+class ExternalSlave(SimObject):
type = 'ExternalSlave'
cxx_header = "mem/external_slave.hh"
#
# Authors: Marco Elver
-from m5.objects.MemObject import MemObject
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
type = 'MemChecker'
cxx_header = "mem/mem_checker.hh"
-class MemCheckerMonitor(MemObject):
+class MemCheckerMonitor(SimObject):
type = 'MemCheckerMonitor'
cxx_header = "mem/mem_checker_monitor.hh"
# Authors: Andreas Sandberg
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class MemDelay(MemObject):
+class MemDelay(ClockedObject):
type = 'MemDelay'
cxx_header = 'mem/mem_delay.hh'
abstract = True
# Erfan Azarkhish
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
# SerialLink is a simple variation of the Bridge class, with the ability to
# account for the latency of packet serialization.
-class SerialLink(MemObject):
+class SerialLink(ClockedObject):
type = 'SerialLink'
cxx_header = "mem/serial_link.hh"
slave = SlavePort('Slave port')
from m5.proxy import *
from m5.SimObject import SimObject
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class BaseXBar(MemObject):
+class BaseXBar(ClockedObject):
type = 'BaseXBar'
abstract = True
cxx_header = "mem/xbar.hh"
using namespace std;
AbstractMemory::AbstractMemory(const Params *p) :
- MemObject(p), range(params()->range), pmemAddr(NULL),
+ ClockedObject(p), range(params()->range), pmemAddr(NULL),
backdoor(params()->range, nullptr,
(MemBackdoor::Flags)(MemBackdoor::Readable |
MemBackdoor::Writeable)),
void
AbstractMemory::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
using namespace Stats;
#define __MEM_ABSTRACT_MEMORY_HH__
#include "mem/backdoor.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/AbstractMemory.hh"
+#include "sim/clocked_object.hh"
#include "sim/stats.hh"
* An abstract memory represents a contiguous block of physical
* memory, with an associated address range, and also provides basic
* functionality for reading and writing this memory without any
- * timing information. It is a MemObject since any subclass must have
- * at least one slave port.
+ * timing information. It is a ClockedObject since subclasses may need timing
+ * information.
*/
-class AbstractMemory : public MemObject
+class AbstractMemory : public ClockedObject
{
protected:
#include "mem/addr_mapper.hh"
AddrMapper::AddrMapper(const AddrMapperParams* p)
- : MemObject(p),
+ : SimObject(p),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this)
{
} else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
#ifndef __MEM_ADDR_MAPPER_HH__
#define __MEM_ADDR_MAPPER_HH__
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/AddrMapper.hh"
#include "params/RangeAddrMapper.hh"
+#include "sim/sim_object.hh"
/**
* An address mapper changes the packet addresses in going from the
* currently not modified.
*/
-class AddrMapper : public MemObject
+class AddrMapper : public SimObject
{
public:
}
Bridge::Bridge(Params *p)
- : MemObject(p),
+ : ClockedObject(p),
slavePort(p->name + ".slave", *this, masterPort,
ticksToCycles(p->delay), p->resp_size, p->ranges),
masterPort(p->name + ".master", *this, slavePort,
return slavePort;
else
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
#include <deque>
#include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/Bridge.hh"
+#include "sim/clocked_object.hh"
/**
* A bridge is used to interface two different crossbars (or in general a
* the bridge will delay accepting the packet until space becomes
* available.
*/
-class Bridge : public MemObject
+class Bridge : public ClockedObject
{
protected:
from m5.proxy import *
from m5.SimObject import SimObject
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
from m5.objects.Prefetcher import BasePrefetcher
from m5.objects.ReplacementPolicies import *
from m5.objects.Tags import *
block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
-class BaseCache(MemObject):
+class BaseCache(ClockedObject):
type = 'BaseCache'
abstract = True
cxx_header = "mem/cache/base.hh"
}
BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
- : MemObject(p),
+ : ClockedObject(p),
cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
memSidePort(p->name + ".mem_side", this, "MemSidePort"),
mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
} else if (if_name == "cpu_side") {
return cpuSidePort;
} else {
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
}
void
BaseCache::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
using namespace Stats;
#include "mem/cache/tags/base.hh"
#include "mem/cache/write_queue.hh"
#include "mem/cache/write_queue_entry.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/packet_queue.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
#include "params/WriteAllocator.hh"
+#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
#include "sim/serialize.hh"
/**
* A basic cache interface. Implements some common functions for speed.
*/
-class BaseCache : public MemObject
+class BaseCache : public ClockedObject
{
protected:
/**
#include "sim/stats.hh"
CommMonitor::CommMonitor(Params* params)
- : MemObject(params),
+ : SimObject(params),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this),
samplePeriodicEvent([this]{ samplePeriodic(); }, name()),
} else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
void
CommMonitor::regStats()
{
- MemObject::regStats();
+ SimObject::regStats();
// Initialise all the monitor stats
using namespace Stats;
#define __MEM_COMM_MONITOR_HH__
#include "base/statistics.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/CommMonitor.hh"
#include "sim/probe/mem.hh"
+#include "sim/sim_object.hh"
/**
- * The communication monitor is a MemObject which can monitor statistics of
+ * The communication monitor is a SimObject which can monitor statistics of
* the communication happening between two ports in the memory system.
*
* Currently the following stats are implemented: Histograms of read/write
* to capture the number of accesses to an address over time ("heat map").
* All stats can be disabled from Python.
*/
-class CommMonitor : public MemObject
+class CommMonitor : public SimObject
{
public: // Construction & SimObject interfaces
void startup() override;
void regProbePoints() override;
- public: // MemObject interfaces
+ public: // SimObject interfaces
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
DRAMCtrl::getPort(const string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getPort(if_name, idx);
+ return QoS::MemCtrl::getPort(if_name, idx);
} else {
return port;
}
DRAMSim2::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getPort(if_name, idx);
+ return AbstractMemory::getPort(if_name, idx);
} else {
return port;
}
ExternalMaster::portHandlers;
ExternalMaster::ExternalMaster(ExternalMasterParams *params) :
- MemObject(params),
+ SimObject(params),
externalPort(NULL),
portName(params->name + ".port"),
portType(params->port_type),
}
return *externalPort;
} else {
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
#ifndef __MEM_EXTERNAL_MASTER_HH__
#define __MEM_EXTERNAL_MASTER_HH__
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/ExternalMaster.hh"
+#include "sim/sim_object.hh"
-class ExternalMaster : public MemObject
+class ExternalMaster : public SimObject
{
public:
/** Derive from this class to create an external port interface */
}
ExternalSlave::ExternalSlave(ExternalSlaveParams *params) :
- MemObject(params),
+ SimObject(params),
externalPort(NULL),
portName(params->name + ".port"),
portType(params->port_type),
}
return *externalPort;
} else {
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
#ifndef __MEM_EXTERNAL_SLAVE_HH__
#define __MEM_EXTERNAL_SLAVE_HH__
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/ExternalSlave.hh"
+#include "sim/sim_object.hh"
-class ExternalSlave : public MemObject
+class ExternalSlave : public SimObject
{
public:
/** Derive from this class to create an external port interface */
#include "debug/MemCheckerMonitor.hh"
MemCheckerMonitor::MemCheckerMonitor(Params* params)
- : MemObject(params),
+ : SimObject(params),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this),
warnOnly(params->warn_only),
} else if (if_name == "slave" || if_name == "cpu_side") {
return slavePort;
} else {
- return MemObject::getPort(if_name, idx);
+ return SimObject::getPort(if_name, idx);
}
}
#include "base/statistics.hh"
#include "mem/mem_checker.hh"
-#include "mem/mem_object.hh"
#include "params/MemCheckerMonitor.hh"
+#include "sim/sim_object.hh"
#include "sim/system.hh"
/**
* Implements a MemChecker monitor, to be inserted between two ports.
*/
-class MemCheckerMonitor : public MemObject
+class MemCheckerMonitor : public SimObject
{
public:
#include "params/SimpleMemDelay.hh"
MemDelay::MemDelay(const MemDelayParams *p)
- : MemObject(p),
+ : ClockedObject(p),
masterPort(name() + "-master", *this),
slavePort(name() + "-slave", *this),
reqQueue(*this, masterPort),
} else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
}
#ifndef __MEM_MEM_DELAY_HH__
#define __MEM_MEM_DELAY_HH__
-#include "mem/mem_object.hh"
#include "mem/qport.hh"
+#include "sim/clocked_object.hh"
struct MemDelayParams;
struct SimpleMemDelayParams;
*
* NOTE: Packets may be reordered if the delays aren't constant.
*/
-class MemDelay : public MemObject
+class MemDelay : public ClockedObject
{
public:
#ifndef __MEM_MPORT_HH__
#define __MEM_MPORT_HH__
-#include "mem/mem_object.hh"
#include "mem/tport.hh"
+#include "sim/sim_object.hh"
/*
* This file defines a port class which is used for sending and receiving
{
public:
- MessageSlavePort(const std::string &name, MemObject *owner) :
+ MessageSlavePort(const std::string &name, SimObject *owner) :
SimpleTimingPort(name, owner)
{}
{
public:
- MessageMasterPort(const std::string &name, MemObject *owner) :
+ MessageMasterPort(const std::string &name, SimObject *owner) :
QueuedMasterPort(name, owner, reqQueue, snoopRespQueue),
reqQueue(*owner, *this), snoopRespQueue(*owner, *this)
{}
/**
* A virtual base opaque structure used to hold state associated
- * with the packet (e.g., an MSHR), specific to a MemObject that
+ * with the packet (e.g., an MSHR), specific to a SimObject that
* sees the packet. A pointer to this state is returned in the
- * packet's response so that the MemObject in question can quickly
+ * packet's response so that the SimObject in question can quickly
* look up the state needed to process it. A specific subclass
* would be derived from this to carry state specific to a
* particular sending device.
*
- * As multiple MemObjects may add their SenderState throughout the
+ * As multiple SimObjects may add their SenderState throughout the
* memory system, the SenderStates create a stack, where a
- * MemObject can add a new Senderstate, as long as the
+ * SimObject can add a new Senderstate, as long as the
* predecessing SenderState is restored when the response comes
* back. For this reason, the predecessor should always be
* populated with the current SenderState of a packet before
#include "mem/port.hh"
#include "base/trace.hh"
-#include "mem/mem_object.hh"
+#include "sim/sim_object.hh"
BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
: Port(name, _id), _baseSlavePort(NULL)
/**
* Master port
*/
-MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id)
+MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
: BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
{
}
/**
* Slave port
*/
-SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id)
+SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
: BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
owner(*_owner)
{
#include "mem/packet.hh"
#include "sim/port.hh"
-class MemObject;
+class SimObject;
/** Forward declaration */
class BaseSlavePort;
protected:
- MemObject& owner;
+ SimObject& owner;
public:
- MasterPort(const std::string& name, MemObject* _owner,
+ MasterPort(const std::string& name, SimObject* _owner,
PortID id=InvalidPortID);
virtual ~MasterPort();
protected:
- MemObject& owner;
+ SimObject& owner;
public:
- SlavePort(const std::string& name, MemObject* _owner,
+ SlavePort(const std::string& name, SimObject* _owner,
PortID id=InvalidPortID);
virtual ~SlavePort();
MemSinkCtrl::getPort(const std::string &interface, PortID idx)
{
if (interface != "port") {
- return MemObject::getPort(interface, idx);
+ return MemCtrl::getPort(interface, idx);
} else {
return port;
}
#include "mem/packet_queue.hh"
#include "mem/port.hh"
+#include "sim/sim_object.hh"
/**
* A queued port is a port that has an infinite queue for outgoing
* behaviuor in a subclass, and provide the latter to the
* QueuePort constructor.
*/
- QueuedSlavePort(const std::string& name, MemObject* owner,
+ QueuedSlavePort(const std::string& name, SimObject* owner,
RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
SlavePort(name, owner, id), respQueue(resp_queue)
{ }
* behaviuor in a subclass, and provide the latter to the
* QueuePort constructor.
*/
- QueuedMasterPort(const std::string& name, MemObject* owner,
+ QueuedMasterPort(const std::string& name, SimObject* owner,
ReqPacketQueue &req_queue,
SnoopRespPacketQueue &snoop_resp_queue,
PortID id = InvalidPortID) :
// No need to connect anything here currently. MessageBuffer
// port connections only serve to print the connections in
// the config output.
- // TODO: Add real ports to MessageBuffers and use MemObject connect
+ // TODO: Add real ports to MessageBuffers and use SimObject connect
// code below to bind MessageBuffer senders and receivers
}
void unbind() override {}
#include "sim/system.hh"
AbstractController::AbstractController(const Params *p)
- : MemObject(p), Consumer(this), m_version(p->version),
+ : ClockedObject(p), Consumer(this), m_version(p->version),
m_clusterID(p->cluster_id),
m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
m_number_of_TBEs(p->number_of_TBEs),
void
AbstractController::regStats()
{
- MemObject::regStats();
+ ClockedObject::regStats();
m_fully_busy_cycles
.name(name() + ".fully_busy_cycles")
#include "base/addr_range.hh"
#include "base/callback.hh"
-#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/qport.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "params/RubyController.hh"
+#include "sim/clocked_object.hh"
class Network;
class GPUCoalescer;
{ return "Port rejected message based on type"; }
};
-class AbstractController : public MemObject, public Consumer
+class AbstractController : public ClockedObject, public Consumer
{
public:
typedef RubyControllerParams Params;
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class RubyController(MemObject):
+class RubyController(ClockedObject):
type = 'RubyController'
cxx_class = 'AbstractController'
cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
#include "sim/system.hh"
RubyPort::RubyPort(const Params *p)
- : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
+ : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
m_controller(NULL), m_mandatory_q_ptr(NULL),
m_usingRubyTester(p->using_ruby_tester), system(p->system),
pioMasterPort(csprintf("%s.pio-master-port", name()), this),
}
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/system/RubySystem.hh"
-#include "mem/mem_object.hh"
#include "mem/tport.hh"
#include "params/RubyPort.hh"
+#include "sim/clocked_object.hh"
class AbstractController;
-class RubyPort : public MemObject
+class RubyPort : public ClockedObject
{
public:
class MemMasterPort : public QueuedMasterPort
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class RubyPort(MemObject):
+class RubyPort(ClockedObject):
type = 'RubyPort'
abstract = True
cxx_header = "mem/ruby/system/RubyPort.hh"
from m5.params import *
from m5.proxy import *
-from m5.objects.MemObject import MemObject
from m5.objects.ReplacementPolicy import ReplacementPolicy
class WeightedLRUReplacementPolicy(ReplacementPolicy):
}
SerialLink::SerialLink(SerialLinkParams *p)
- : MemObject(p),
+ : ClockedObject(p),
slavePort(p->name + ".slave", *this, masterPort,
ticksToCycles(p->delay), p->resp_size, p->ranges),
masterPort(p->name + ".master", *this, slavePort,
return slavePort;
else
// pass it along to our super class
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
void
#include <deque>
#include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
#include "params/SerialLink.hh"
+#include "sim/clocked_object.hh"
/**
* SerialLink is a simple variation of the Bridge class, with the ability to
* whole packet to start the serialization. But the deserializer waits for the
* complete packet to check its integrity first.
*/
-class SerialLink : public MemObject
+class SerialLink : public ClockedObject
{
protected:
SimpleMemory::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getPort(if_name, idx);
+ return AbstractMemory::getPort(if_name, idx);
} else {
return port;
}
*/
#include "mem/tport.hh"
-
-#include "mem/mem_object.hh"
+#include "sim/sim_object.hh"
SimpleTimingPort::SimpleTimingPort(const std::string& _name,
- MemObject* _owner) :
+ SimObject* _owner) :
QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
{
}
#include "mem/qport.hh"
+class SimObject;
+
/**
* The simple timing port uses a queued port to implement
* recvFunctional and recvTimingReq through recvAtomic. It is always a
* @param name port name
* @param owner structural owner
*/
- SimpleTimingPort(const std::string& name, MemObject* owner);
+ SimpleTimingPort(const std::string& name, SimObject* owner);
virtual ~SimpleTimingPort() { }
#include "debug/XBar.hh"
BaseXBar::BaseXBar(const BaseXBarParams *p)
- : MemObject(p),
+ : ClockedObject(p),
frontendLatency(p->frontend_latency),
forwardLatency(p->forward_latency),
responseLatency(p->response_latency),
// the slave port index translates directly to the vector position
return *slavePorts[idx];
} else {
- return MemObject::getPort(if_name, idx);
+ return ClockedObject::getPort(if_name, idx);
}
}
#include "base/addr_range_map.hh"
#include "base/types.hh"
-#include "mem/mem_object.hh"
#include "mem/qport.hh"
#include "params/BaseXBar.hh"
+#include "sim/clocked_object.hh"
#include "sim/stats.hh"
/**
* The BaseXBar is responsible for the basic flow control (busy or
* not), the administration of retries, and the address decoding.
*/
-class BaseXBar : public MemObject
+class BaseXBar : public ClockedObject
{
protected:
code('#include "base/str.hh"')
code('#include "cxx_config/${name}.hh"')
- if simobj._ports:
- code('#include "mem/mem_object.hh"')
- code('#include "mem/port.hh"')
-
code()
code('${member_prefix}DirectoryEntry::DirectoryEntry()');
code('{')
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
'atomic_noncaching']
-class System(MemObject):
+class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
system_port = MasterPort("System port")
#include "base/str.hh"
#include "base/trace.hh"
#include "debug/CxxConfig.hh"
-#include "mem/mem_object.hh"
#include "sim/serialize.hh"
+#include "sim/sim_object.hh"
CxxConfigManager::CxxConfigManager(CxxConfigFileBase &configFile_) :
configFile(configFile_), flags(configFile_.getFlags()),
SimObject *slave_object, const std::string &slave_port_name,
PortID slave_port_index)
{
- MemObject *master_mem_object = dynamic_cast<MemObject *>(master_object);
- MemObject *slave_mem_object = dynamic_cast<MemObject *>(slave_object);
-
- if (!master_mem_object) {
- throw Exception(master_object->name(), csprintf(
- "Object isn't a mem object and so can have master port:"
- " %s[%d]", master_port_name, master_port_index));
- }
-
- if (!slave_mem_object) {
- throw Exception(slave_object->name(), csprintf(
- "Object isn't a mem object and so can have slave port:"
- " %s[%d]", slave_port_name, slave_port_index));
- }
-
/* FIXME, check slave_port_index against connection_count
* defined for port, need getPortConnectionCount and a
* getCxxConfigDirectoryEntry for each object. */
/* It would be nice to be able to catch the errors from these calls. */
- Port &master_port = master_mem_object->getPort(
+ Port &master_port = master_object->getPort(
master_port_name, master_port_index);
- Port &slave_port = slave_mem_object->getPort(
+ Port &slave_port = slave_object->getPort(
slave_port_name, slave_port_index);
if (master_port.isConnected()) {
int System::numSystemsRunning = 0;
System::System(Params *p)
- : MemObject(p), _systemPort("system_port", this),
+ : SimObject(p), _systemPort("system_port", this),
multiThread(p->multi_thread),
pagePtr(0),
init_param(p->init_param),
void
System::regStats()
{
- MemObject::regStats();
+ SimObject::regStats();
for (uint32_t j = 0; j < numWorkIds ; j++) {
workItemStats[j] = new Stats::Histogram();
#include "config/the_isa.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_master.hh"
-#include "mem/mem_object.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "sim/futex_map.hh"
#include "sim/redirect_path.hh"
#include "sim/se_signal.hh"
+#include "sim/sim_object.hh"
/**
* To avoid linking errors with LTO, only include the header if we
class ObjectFile;
class ThreadContext;
-class System : public MemObject
+class System : public SimObject
{
private:
/**
* Create a system port with a name and an owner.
*/
- SystemPort(const std::string &_name, MemObject *_owner)
+ SystemPort(const std::string &_name, SimObject *_owner)
: MasterPort(_name, _owner)
{ }
bool recvTimingResp(PacketPtr pkt) override
projects / gem5.git / commitdiff