intel: Clean up chipset name and gen num for Ironlake

Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index d3275c7a89d0cd500d6b74dbe5be12a74bdcc463..029a16500b54cb7ee7c3470fd212e04e099cf554 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -72,7 +72,7 @@ static void compile_clip_prog( struct brw_context *brw,
     */
    c.header_position_offset = ATTR_SIZE;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        delta = 3 * REG_SIZE;
    else
        delta = REG_SIZE;
@@ -85,7 +85,7 @@ static void compile_clip_prog( struct brw_context *brw,
 
    c.nr_attrs = brw_count_bits(c.key.attrs);
    
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        c.nr_regs = (c.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
    else
        c.nr_regs = (c.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
@@ -162,7 +162,7 @@ static void upload_clip_prog(struct brw_context *brw)
    /* _NEW_TRANSFORM */
    key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP;
    else
        key.clip_mode = BRW_CLIPMODE_NORMAL;

diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 424c9a1f1985afc6cc71fe0e22037f54ac2ea7cb..d78f3616d6fff79e6148ed8bef3a239eca2c97e6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -102,10 +102,10 @@ clip_unit_create_from_key(struct brw_context *brw,
        */
       assert(key->nr_urb_entries % 2 == 0);
       
-      /* Although up to 16 concurrent Clip threads are allowed on IGDNG, 
+      /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
        * only 2 threads can output VUEs at a time.
        */
-      if (intel->is_ironlake)
+      if (intel->gen == 5)
          clip.thread4.max_threads = 16 - 1;        
       else
          clip.thread4.max_threads = 2 - 1;

diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 815211acc21dd9046c7c464c354fa693721d8982..b27fe654ca9e6ccb3dbeffdb3e59c7da456cd911 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -78,7 +78,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
       for (j = 0; j < 3; j++) {
         GLuint delta = c->nr_attrs*16 + 32;
 
-         if (intel->is_ironlake)
+         if (intel->gen == 5)
              delta = c->nr_attrs * 16 + 32 * 3;
 
         brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));

diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 14bc889b0f8e9260b741d87d45b131a23e2a1094..34a966a47a224d4f751a1eb754190f171dcf6115 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -151,7 +151,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
    for (i = 0; i < c->nr_attrs; i++) {
       GLuint delta = i*16 + 32;
 
-      if (intel->is_ironlake)
+      if (intel->gen == 5)
           delta = i * 16 + 32 * 3;
 
       if (delta == c->offset[VERT_RESULT_EDGE]) {
@@ -185,7 +185,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
    if (i & 1) {
       GLuint delta = i*16 + 32;
 
-      if (intel->is_ironlake)
+      if (intel->gen == 5)
           delta = i * 16 + 32 * 3;
 
       brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 241193c3579f5ae4903c66b9b622d8098ca959cd..360fc12621adfef2d94148bb22322f76c6c28742 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -150,7 +150,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
       MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
           ctx->Const.FragmentProgram.MaxEnvParams);
 
-   if (intel->is_ironlake || intel->is_g4x || intel->gen >= 6) {
+   if (intel->is_g4x || intel->gen >= 5) {
       brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45;
       brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
       brw->has_surface_tile_offset = GL_TRUE;
@@ -163,7 +163,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
    }
 
    /* WM maximum threads is number of EUs times number of threads per EU. */
-   if (intel->is_ironlake) {
+   if (intel->gen == 5) {
       brw->urb.size = 1024;
       brw->vs_max_threads = 72;
       brw->wm_max_threads = 12 * 6;

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 6fe574b22e2a7c7bd6202d7f1c69d3142de233e2..f26a13fc3c37aaaf19c21a2f23a35411b4f9851d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -675,12 +675,12 @@
 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
 
-#define BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG            0
-#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG       1
-#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_IGDNG        2
-#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG    3
+#define BRW_SAMPLER_MESSAGE_SAMPLE_GEN5            0
+#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5       1
+#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5        2
+#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5    3
 
-/* for IGDNG only */
+/* for GEN5 only */
 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 71a43577bfde8f3566b54ef041147739e6b934d9..8247faa36d8d082e891b91d57895ce3446433d58 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -522,7 +522,7 @@ static void brw_emit_vertices(struct brw_context *brw)
       OUT_RELOC(input->bo,
                I915_GEM_DOMAIN_VERTEX, 0,
                input->offset);
-      if (intel->is_ironlake || intel->gen >= 6) {
+      if (intel->gen >= 5) {
         OUT_RELOC(input->bo,
                   I915_GEM_DOMAIN_VERTEX, 0,
                   input->bo->size - 1);
@@ -565,7 +565,7 @@ static void brw_emit_vertices(struct brw_context *brw)
                   (0 << BRW_VE0_SRC_OFFSET_SHIFT));
       }
 
-      if (intel->is_ironlake || intel->gen >= 6)
+      if (intel->gen >= 5)
           OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
                     (comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
                     (comp2 << BRW_VE1_COMPONENT_2_SHIFT) |

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c33c3def30413bcccfafb4f29c62deb1afd0c044..785d382a009d8f7e772ba6106cf8a790e8bbe057 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -253,19 +253,19 @@ static void brw_set_math_message( struct brw_context *brw,
    struct intel_context *intel = &brw->intel;
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (intel->is_ironlake) {
-       insn->bits3.math_igdng.function = function;
-       insn->bits3.math_igdng.int_type = integer_type;
-       insn->bits3.math_igdng.precision = low_precision;
-       insn->bits3.math_igdng.saturate = saturate;
-       insn->bits3.math_igdng.data_type = dataType;
-       insn->bits3.math_igdng.snapshot = 0;
-       insn->bits3.math_igdng.header_present = 0;
-       insn->bits3.math_igdng.response_length = response_length;
-       insn->bits3.math_igdng.msg_length = msg_length;
-       insn->bits3.math_igdng.end_of_thread = 0;
-       insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_MATH;
-       insn->bits2.send_igdng.end_of_thread = 0;
+   if (intel->gen == 5) {
+       insn->bits3.math_gen5.function = function;
+       insn->bits3.math_gen5.int_type = integer_type;
+       insn->bits3.math_gen5.precision = low_precision;
+       insn->bits3.math_gen5.saturate = saturate;
+       insn->bits3.math_gen5.data_type = dataType;
+       insn->bits3.math_gen5.snapshot = 0;
+       insn->bits3.math_gen5.header_present = 0;
+       insn->bits3.math_gen5.response_length = response_length;
+       insn->bits3.math_gen5.msg_length = msg_length;
+       insn->bits3.math_gen5.end_of_thread = 0;
+       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH;
+       insn->bits2.send_gen5.end_of_thread = 0;
    } else {
        insn->bits3.math.function = function;
        insn->bits3.math.int_type = integer_type;
@@ -293,18 +293,18 @@ static void brw_set_ff_sync_message( struct brw_context *brw,
 {
        brw_set_src1(insn, brw_imm_d(0));
 
-       insn->bits3.urb_igdng.opcode = 1;
-       insn->bits3.urb_igdng.offset = offset;
-       insn->bits3.urb_igdng.swizzle_control = swizzle_control;
-       insn->bits3.urb_igdng.allocate = allocate;
-       insn->bits3.urb_igdng.used = used;
-       insn->bits3.urb_igdng.complete = complete;
-       insn->bits3.urb_igdng.header_present = 1;
-       insn->bits3.urb_igdng.response_length = response_length;
-       insn->bits3.urb_igdng.msg_length = msg_length;
-       insn->bits3.urb_igdng.end_of_thread = end_of_thread;
-       insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
-       insn->bits2.send_igdng.end_of_thread = end_of_thread;
+       insn->bits3.urb_gen5.opcode = 1;
+       insn->bits3.urb_gen5.offset = offset;
+       insn->bits3.urb_gen5.swizzle_control = swizzle_control;
+       insn->bits3.urb_gen5.allocate = allocate;
+       insn->bits3.urb_gen5.used = used;
+       insn->bits3.urb_gen5.complete = complete;
+       insn->bits3.urb_gen5.header_present = 1;
+       insn->bits3.urb_gen5.response_length = response_length;
+       insn->bits3.urb_gen5.msg_length = msg_length;
+       insn->bits3.urb_gen5.end_of_thread = end_of_thread;
+       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
+       insn->bits2.send_gen5.end_of_thread = end_of_thread;
 }
 
 static void brw_set_urb_message( struct brw_context *brw,
@@ -321,17 +321,17 @@ static void brw_set_urb_message( struct brw_context *brw,
     struct intel_context *intel = &brw->intel;
     brw_set_src1(insn, brw_imm_d(0));
 
-    if (intel->is_ironlake || intel->gen >= 6) {
-        insn->bits3.urb_igdng.opcode = 0;      /* ? */
-        insn->bits3.urb_igdng.offset = offset;
-        insn->bits3.urb_igdng.swizzle_control = swizzle_control;
-        insn->bits3.urb_igdng.allocate = allocate;
-        insn->bits3.urb_igdng.used = used;     /* ? */
-        insn->bits3.urb_igdng.complete = complete;
-        insn->bits3.urb_igdng.header_present = 1;
-        insn->bits3.urb_igdng.response_length = response_length;
-        insn->bits3.urb_igdng.msg_length = msg_length;
-        insn->bits3.urb_igdng.end_of_thread = end_of_thread;
+    if (intel->gen >= 5) {
+        insn->bits3.urb_gen5.opcode = 0;       /* ? */
+        insn->bits3.urb_gen5.offset = offset;
+        insn->bits3.urb_gen5.swizzle_control = swizzle_control;
+        insn->bits3.urb_gen5.allocate = allocate;
+        insn->bits3.urb_gen5.used = used;      /* ? */
+        insn->bits3.urb_gen5.complete = complete;
+        insn->bits3.urb_gen5.header_present = 1;
+        insn->bits3.urb_gen5.response_length = response_length;
+        insn->bits3.urb_gen5.msg_length = msg_length;
+        insn->bits3.urb_gen5.end_of_thread = end_of_thread;
        if (intel->gen >= 6) {
           /* For SNB, the SFID bits moved to the condmod bits, and
            * EOT stayed in bits3 above.  Does the EOT bit setting
@@ -339,8 +339,8 @@ static void brw_set_urb_message( struct brw_context *brw,
            */
           insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
        } else {
-          insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
-          insn->bits2.send_igdng.end_of_thread = end_of_thread;
+          insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
+          insn->bits2.send_gen5.end_of_thread = end_of_thread;
        }
     } else {
         insn->bits3.urb.opcode = 0;    /* ? */
@@ -369,18 +369,18 @@ static void brw_set_dp_write_message( struct brw_context *brw,
    struct intel_context *intel = &brw->intel;
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (intel->is_ironlake) {
-       insn->bits3.dp_write_igdng.binding_table_index = binding_table_index;
-       insn->bits3.dp_write_igdng.msg_control = msg_control;
-       insn->bits3.dp_write_igdng.pixel_scoreboard_clear = pixel_scoreboard_clear;
-       insn->bits3.dp_write_igdng.msg_type = msg_type;
-       insn->bits3.dp_write_igdng.send_commit_msg = 0;
-       insn->bits3.dp_write_igdng.header_present = 1;
-       insn->bits3.dp_write_igdng.response_length = response_length;
-       insn->bits3.dp_write_igdng.msg_length = msg_length;
-       insn->bits3.dp_write_igdng.end_of_thread = end_of_thread;
-       insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
-       insn->bits2.send_igdng.end_of_thread = end_of_thread;
+   if (intel->gen == 5) {
+       insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
+       insn->bits3.dp_write_gen5.msg_control = msg_control;
+       insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear;
+       insn->bits3.dp_write_gen5.msg_type = msg_type;
+       insn->bits3.dp_write_gen5.send_commit_msg = 0;
+       insn->bits3.dp_write_gen5.header_present = 1;
+       insn->bits3.dp_write_gen5.response_length = response_length;
+       insn->bits3.dp_write_gen5.msg_length = msg_length;
+       insn->bits3.dp_write_gen5.end_of_thread = end_of_thread;
+       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
+       insn->bits2.send_gen5.end_of_thread = end_of_thread;
    } else {
        insn->bits3.dp_write.binding_table_index = binding_table_index;
        insn->bits3.dp_write.msg_control = msg_control;
@@ -407,18 +407,18 @@ static void brw_set_dp_read_message( struct brw_context *brw,
    struct intel_context *intel = &brw->intel;
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (intel->is_ironlake) {
-       insn->bits3.dp_read_igdng.binding_table_index = binding_table_index;
-       insn->bits3.dp_read_igdng.msg_control = msg_control;
-       insn->bits3.dp_read_igdng.msg_type = msg_type;
-       insn->bits3.dp_read_igdng.target_cache = target_cache;
-       insn->bits3.dp_read_igdng.header_present = 1;
-       insn->bits3.dp_read_igdng.response_length = response_length;
-       insn->bits3.dp_read_igdng.msg_length = msg_length;
-       insn->bits3.dp_read_igdng.pad1 = 0;
-       insn->bits3.dp_read_igdng.end_of_thread = end_of_thread;
-       insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
-       insn->bits2.send_igdng.end_of_thread = end_of_thread;
+   if (intel->gen == 5) {
+       insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
+       insn->bits3.dp_read_gen5.msg_control = msg_control;
+       insn->bits3.dp_read_gen5.msg_type = msg_type;
+       insn->bits3.dp_read_gen5.target_cache = target_cache;
+       insn->bits3.dp_read_gen5.header_present = 1;
+       insn->bits3.dp_read_gen5.response_length = response_length;
+       insn->bits3.dp_read_gen5.msg_length = msg_length;
+       insn->bits3.dp_read_gen5.pad1 = 0;
+       insn->bits3.dp_read_gen5.end_of_thread = end_of_thread;
+       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
+       insn->bits2.send_gen5.end_of_thread = end_of_thread;
    } else {
        insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
        insn->bits3.dp_read.msg_control = msg_control;  /*8:11*/
@@ -447,17 +447,17 @@ static void brw_set_sampler_message(struct brw_context *brw,
    assert(eot == 0);
    brw_set_src1(insn, brw_imm_d(0));
 
-   if (intel->is_ironlake) {
-      insn->bits3.sampler_igdng.binding_table_index = binding_table_index;
-      insn->bits3.sampler_igdng.sampler = sampler;
-      insn->bits3.sampler_igdng.msg_type = msg_type;
-      insn->bits3.sampler_igdng.simd_mode = simd_mode;
-      insn->bits3.sampler_igdng.header_present = header_present;
-      insn->bits3.sampler_igdng.response_length = response_length;
-      insn->bits3.sampler_igdng.msg_length = msg_length;
-      insn->bits3.sampler_igdng.end_of_thread = eot;
-      insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER;
-      insn->bits2.send_igdng.end_of_thread = eot;
+   if (intel->gen == 5) {
+      insn->bits3.sampler_gen5.binding_table_index = binding_table_index;
+      insn->bits3.sampler_gen5.sampler = sampler;
+      insn->bits3.sampler_gen5.msg_type = msg_type;
+      insn->bits3.sampler_gen5.simd_mode = simd_mode;
+      insn->bits3.sampler_gen5.header_present = header_present;
+      insn->bits3.sampler_gen5.response_length = response_length;
+      insn->bits3.sampler_gen5.msg_length = msg_length;
+      insn->bits3.sampler_gen5.end_of_thread = eot;
+      insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER;
+      insn->bits2.send_gen5.end_of_thread = eot;
    } else if (intel->is_g4x) {
       insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
       insn->bits3.sampler_g4x.sampler = sampler;
@@ -663,7 +663,7 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
    struct brw_instruction *insn;
    GLuint br = 1;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       br = 2;
 
    if (p->single_program_flow) {
@@ -705,7 +705,7 @@ void brw_ENDIF(struct brw_compile *p,
    struct intel_context *intel = &p->brw->intel;
    GLuint br = 1;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       br = 2; 
  
    if (p->single_program_flow) {
@@ -820,7 +820,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
    struct brw_instruction *insn;
    GLuint br = 1;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       br = 2;
 
    if (p->single_program_flow)
@@ -864,7 +864,7 @@ void brw_land_fwd_jump(struct brw_compile *p,
    struct brw_instruction *landing = &p->store[p->nr_insn];
    GLuint jmpi = 1;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        jmpi = 2;
 
    assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 7261b316c100e7088650a44918af928f5e573bda..4b13494ecf901ac0ad1ca71f2b56ddafa8dbe60c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -60,7 +60,7 @@ static void compile_gs_prog( struct brw_context *brw,
     */
    c.nr_attrs = brw_count_bits(c.key.attrs);
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        c.nr_regs = (c.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
    else
        c.nr_regs = (c.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */

diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index d8ad5cecf3fe422fc0ffec9932ef39dfab7f60ef..d16b9f6ff340a6479435359343b336afb6a31020 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -98,7 +98,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
    else
       gs.thread4.max_threads = 0;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       gs.thread4.rendering_enable = 1;
 
    if (INTEL_DEBUG & DEBUG_STATS)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index d030ed41f4a4552a2e7ebb74e4f3ca6e2871863e..3b3cb5a0e9ff73d8cba5efe86a53f2be9cc045d3 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -248,7 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
 
    if (intel->gen >= 6)
       len = 7;
-   else if (intel->is_g4x || intel->is_ironlake)
+   else if (intel->is_g4x || intel->gen == 5)
       len = 6;
    else
       len = 5;
@@ -262,7 +262,7 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_BATCH(0);
       OUT_BATCH(0);
 
-      if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
+      if (intel->is_g4x || intel->gen >= 5)
          OUT_BATCH(0);
 
       if (intel->gen >= 6)
@@ -306,7 +306,7 @@ static void emit_depthbuffer(struct brw_context *brw)
                ((region->height - 1) << 19));
       OUT_BATCH(0);
 
-      if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
+      if (intel->is_g4x || intel->gen >= 5)
          OUT_BATCH(0);
 
       if (intel->gen >= 6)
@@ -608,7 +608,7 @@ static void upload_state_base_address( struct brw_context *brw )
        OUT_BATCH(1); /* Indirect object upper bound */
        OUT_BATCH(1); /* Instruction access upper bound */
        ADVANCE_BATCH();
-   } else if (intel->is_ironlake) {
+   } else if (intel->gen == 5) {
        BEGIN_BATCH(8);
        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
        OUT_BATCH(1); /* General state base address */

diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index 56f7c986e7844c4dd58d66a109b7d8e9513f1bc9..d3c975690ceb170bde4a4d61d2492176860ba21c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -162,7 +162,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
    if (c->key.primitive == SF_UNFILLED_TRIS)
       return;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        jmpi = 2;
 
    brw_push_insn_state(p);
@@ -201,7 +201,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
    if (c->key.primitive == SF_UNFILLED_TRIS)
       return;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        jmpi = 2;
 
    brw_push_insn_state(p);

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 847c886279d0914879266a7afe457ea708859eb2..9712c31afeadda8864ab980424ac0e013d075ae0 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -177,7 +177,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
 
    sf.thread3.dispatch_grf_start_reg = 3;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
        sf.thread3.urb_entry_read_offset = 3;
    else
        sf.thread3.urb_entry_read_offset = 1;
@@ -190,7 +190,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
    /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
     * 48 (Ironlake) threads.
     */
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       chipset_max_threads = 48;
    else
       chipset_max_threads = 24;

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 3c2adfc87d4175e3bfff9c52ff8162bbb6560719..f17fe485306a14c49b21a18fffa1dbe1b4628742 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -925,7 +925,7 @@ struct brw_gs_unit_state
    struct
    {
       GLuint pad0:8;
-      GLuint rendering_enable:1; /* for IGDNG */
+      GLuint rendering_enable:1; /* for Ironlake */
       GLuint pad4:1;
       GLuint stats_enable:1; 
       GLuint nr_urb_entries:7; 
@@ -1035,7 +1035,7 @@ struct brw_wm_unit_state
    GLfloat global_depth_offset_constant;  
    GLfloat global_depth_offset_scale;   
    
-   /* for IGDNG only */
+   /* for Ironlake only */
    struct {
       GLuint pad0:1;
       GLuint grf_reg_count_1:3; 
@@ -1448,7 +1448,7 @@ struct brw_instruction
            GLuint end_of_thread:1;
            GLuint pad1:1;
            GLuint sfid:4;
-       } send_igdng;  /* for IGDNG only */
+       } send_gen5;  /* for Ironlake only */
 
    } bits2;
 
@@ -1549,7 +1549,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } math_igdng;
+      } math_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1585,7 +1585,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } sampler_igdng;
+      } sampler_gen5;
 
       struct brw_urb_immediate urb;
 
@@ -1603,7 +1603,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } urb_igdng;
+      } urb_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1628,7 +1628,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } dp_read_igdng;
+      } dp_read_gen5;
 
       struct {
         GLuint binding_table_index:8;
@@ -1655,7 +1655,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } dp_write_igdng;
+      } dp_write_gen5;
 
       struct {
         GLuint pad:16;
@@ -1673,7 +1673,7 @@ struct brw_instruction
         GLuint msg_length:4;
         GLuint pad1:2;
         GLuint end_of_thread:1;
-      } generic_igdng;
+      } generic_gen5;
 
       GLint d;
       GLuint ud;

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index b1f56a8e6488c179b5a6684f0a66e51fb4ac1317..9a215ab8a4da63597948233ac4f3c8b50b0fdc3b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -48,7 +48,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
 
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
-      if (intel->is_ironlake) {
+      if (intel->gen == 5) {
           GLuint align_h = 2, align_w = 4;
           GLuint level;
           GLuint x = 0;

diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c
index 4f6b9002ad5a78207a35c74753d7068b8629967c..0f597184b42839763285843dcc9fc194201b9604 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_urb.c
+++ b/src/mesa/drivers/dri/i965/brw_urb.c
@@ -148,7 +148,7 @@ static void recalculate_urb_fence( struct brw_context *brw )
 
       brw->urb.constrained = 0;
 
-      if (intel->is_ironlake) {
+      if (intel->gen == 5) {
          brw->urb.nr_vs_entries = 128;
          brw->urb.nr_sf_entries = 48;
          if (check_urb_layout(brw)) {

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 7adb7956c72a68fc36335d212ba25ce244e8486f..eeb3f366a414c33d8c0fbb0e52f77745b16a4de5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -182,7 +182,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 
    if (intel->gen >= 6)
       mrf = 6;
-   else if (intel->is_ironlake)
+   else if (intel->gen == 5)
       mrf = 8;
    else
       mrf = 4;
@@ -283,7 +283,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 
    if (intel->gen >= 6)
       c->prog_data.urb_entry_size = (attributes_in_vue + 4 + 7) / 8;
-   else if (intel->is_ironlake)
+   else if (intel->gen == 5)
       c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
    else
       c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@@ -1288,7 +1288,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
       brw_MOV(p, offset(m0, 2), pos);
       brw_MOV(p, offset(m0, 5), pos);
       len_vertex_header = 4;
-   } else if (intel->is_ironlake) {
+   } else if (intel->gen == 5) {
       /* There are 20 DWs (D0-D19) in VUE header on Ironlake:
        * dword 0-3 (m1) of the header is indices, point width, clip flags.
        * dword 4-7 (m2) is the ndc position (set above)
@@ -1684,7 +1684,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 
             loop_depth--;
 
-           if (intel->is_ironlake)
+           if (intel->gen == 5)
               br = 2;
 
             inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);

diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index fd9f2fee423a347df0b6284279093905f2d2198a..0ba81977dfa09bd31df0dfda1030cb6b2c5005f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -98,7 +98,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
     */
    vs.thread1.single_program_flow = 0;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
    else
       vs.thread1.binding_table_entry_count = key->nr_surfaces;
@@ -109,7 +109,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
    vs.thread3.urb_entry_read_offset = 0;
    vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 
-   if (intel->is_ironlake) {
+   if (intel->gen == 5) {
       switch (key->nr_urb_entries) {
       case 8:
       case 12:
@@ -150,7 +150,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
 
    /* No samplers for ARB_vp programs:
     */
-   /* It has to be set to 0 for IGDNG
+   /* It has to be set to 0 for Ironlake
     */
    vs.vs5.sampler_count = 0;
 

diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index f79de5dbffc8c62c58aeb93220efbdd2c588e2ce..375e7953912389ab580249d86295278ee2b7d284 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -967,7 +967,7 @@ void emit_tex(struct brw_wm_compile *c,
    }
 
    /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
-   if (!intel->is_ironlake && c->dispatch_width == 8)
+   if (intel->gen < 5 && c->dispatch_width == 8)
       nr_texcoords = 3;
 
    /* For shadow comparisons, we have to supply u,v,r. */
@@ -985,7 +985,7 @@ void emit_tex(struct brw_wm_compile *c,
 
    /* Fill in the shadow comparison reference value. */
    if (shadow) {
-      if (intel->is_ironlake) {
+      if (intel->gen == 5) {
         /* Fill in the cube map array index value. */
         brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0));
         cur_mrf += mrf_per_channel;
@@ -998,11 +998,11 @@ void emit_tex(struct brw_wm_compile *c,
       cur_mrf += mrf_per_channel;
    }
 
-   if (intel->is_ironlake) {
+   if (intel->gen == 5) {
       if (shadow)
-        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG;
+        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
       else
-        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG;
+        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
    } else {
       /* Note that G45 and older determines shadow compare and dispatch width
        * from message length for most messages.
@@ -1050,16 +1050,16 @@ void emit_txb(struct brw_wm_compile *c,
     * undefined, and trust the execution mask to keep the undefined pixels
     * from mattering.
     */
-   if (c->dispatch_width == 16 || !intel->is_ironlake) {
-      if (intel->is_ironlake)
-        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG;
+   if (c->dispatch_width == 16 || intel->gen < 5) {
+      if (intel->gen == 5)
+        msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
       else
         msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
       mrf_per_channel = 2;
       dst_retyped = retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW);
       response_length = 8;
    } else {
-      msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG;
+      msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
       mrf_per_channel = 1;
       dst_retyped = retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW);
       response_length = 4;

diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
index 3b7e421b16ad7a5fedbee389d3076ce6936b1eb7..88b885cb94147bc981e4f66ffc471a1c943f3052 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
@@ -2070,7 +2070,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
                   struct brw_instruction *inst0, *inst1;
                   GLuint br = 1;
 
-                  if (intel->is_ironlake)
+                  if (intel->gen == 5)
                      br = 2;
 
                  assert(loop_depth > 0);

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index a7f80db554a90a894f37844384518657ad925a14..073a1c52aaac6d469841597dea03c2b9aaf92214 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -137,7 +137,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
    wm.thread1.depth_coef_urb_read_offset = 1;
    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
    else
       wm.thread1.binding_table_entry_count = key->nr_surfaces;
@@ -157,7 +157,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
    wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
    wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 
-   if (intel->is_ironlake)
+   if (intel->gen == 5)
       wm.wm4.sampler_count = 0; /* hardware requirement */
    else
       wm.wm4.sampler_count = (key->sampler_count + 1) / 4;

diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index a0b2266925317c3b3e739c5e8c4bef44befa3ea6..dbc08c872b9e545dd40be256a33b2f1184c82c0b 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -93,7 +93,7 @@
 
 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
-#define IS_IGDNG(devid)           (IS_ILD(devid) || IS_ILM(devid))
+#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
 
 #define IS_915(devid)          (devid == PCI_CHIP_I915_G || \
                                 devid == PCI_CHIP_E7221_G || \
@@ -118,7 +118,7 @@
 
 #define IS_965(devid)          (IS_GEN4(devid) || \
                                 IS_G4X(devid) || \
-                                IS_IGDNG(devid) || \
+                                IS_GEN5(devid) || \
                                 IS_GEN6(devid))
 
 #define IS_9XX(devid)          (IS_915(devid) || \

diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 9077a611328e75c6fb003d37b1b9d410e4ed2290..2ccc12010eda4ae422bba6331305159fd79449df 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -159,10 +159,10 @@ intelGetString(GLcontext * ctx, GLenum name)
          chipset = "Intel(R) B43";
          break;
       case PCI_CHIP_ILD_G:
-         chipset = "Intel(R) IGDNG_D";
+         chipset = "Intel(R) Ironlake Desktop";
          break;
       case PCI_CHIP_ILM_G:
-         chipset = "Intel(R) IGDNG_M";
+         chipset = "Intel(R) Ironlake Mobile";
          break;
       default:
          chipset = "Unknown Intel Chipset";
@@ -616,8 +616,16 @@ intelInitContext(struct intel_context *intel,
       intel->gen = 6;
       intel->needs_ff_sync = GL_TRUE;
       intel->has_luminance_srgb = GL_TRUE;
+   } else if (IS_GEN5(intel->intelScreen->deviceID)) {
+      intel->gen = 5;
+      intel->needs_ff_sync = GL_TRUE;
+      intel->has_luminance_srgb = GL_TRUE;
    } else if (IS_965(intel->intelScreen->deviceID)) {
       intel->gen = 4;
+      if (IS_G4X(intel->intelScreen->deviceID)) {
+         intel->has_luminance_srgb = GL_TRUE;
+         intel->is_g4x = GL_TRUE;
+      }
    } else if (IS_9XX(intel->intelScreen->deviceID)) {
       intel->gen = 3;
       if (IS_945(intel->intelScreen->deviceID)) {
@@ -627,15 +635,6 @@ intelInitContext(struct intel_context *intel,
       intel->gen = 2;
    }
 
-   if (IS_IGDNG(intel->intelScreen->deviceID)) {
-      intel->is_ironlake = GL_TRUE;
-      intel->needs_ff_sync = GL_TRUE;
-      intel->has_luminance_srgb = GL_TRUE;
-   } else if (IS_G4X(intel->intelScreen->deviceID)) {
-      intel->has_luminance_srgb = GL_TRUE;
-      intel->is_g4x = GL_TRUE;
-   }
-
    driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
                        sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
    if (intelScreen->deviceID == PCI_CHIP_I865_G)

diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index c4bb2bed8e0a72cbba4c58be4280f8e95875309c..75dabc554c671c4717f2c628638a8349a02dcf17 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -142,7 +142,6 @@ struct intel_context
     */
    int gen;
    GLboolean needs_ff_sync;
-   GLboolean is_ironlake;
    GLboolean is_g4x;
    GLboolean is_945;
    GLboolean has_luminance_srgb;