Added another mem2reg test case

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 23094c10a7f94583398f6bd06cd2738f2b475572..9839fd4a89743ba2c1490d905156c3d22efcbe4e 100644 (file)
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -81,3 +81,14 @@ module mem2reg_test4(result1, result2, result3);
        assign result3 = intermediate[depth2Index(3)];
 endmodule
 
+// ------------------------------------------------------
+
+module mem2reg_test5(input ctrl, output out);
+       wire [0:0] foo[0:0];
+       wire [0:0] bar[0:1];
+
+       assign foo[0] = ctrl;
+       assign bar[0] = 0, bar[1] = 1;
+       assign out = bar[foo[0]];
+endmodule
+