Merge branch 'master' into orangecrab-merge

diff --cc Makefile
index 4ef104c69757a937193f733ecaefb9f9a292b3d1,2830603501d71f0e250c891e7cf29350da7dc185..eb46c5b3fc1ea19b6c419965ce2837dc1f945b3e
--- 1/Makefile
--- 2/Makefile
+++ b/Makefile
@@@ -175,15 -175,15 +180,18 @@@ endi
  ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21)
  RESET_LOW=true
  CLK_INPUT=48000000
 -CLK_FREQUENCY=40000000
 -LPF=constraints/orange-crab.lpf
 +CLK_FREQUENCY=48000000
 +LPF=constraints/orange-crab-0.2.lpf
  PACKAGE=CSFBGA285
 -NEXTPNR_FLAGS=--85k --speed 8 --freq 40
 +NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops
  OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
  OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
+ DFU_VENDOR=1209
+ DFU_PRODUCT=5af0
+ ECP_FLASH_OFFSET=0x80000
 +toplevel=fpga/top-orangecrab0.2.vhdl
 +litedram_target=orangecrab-85-0.2
 +soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
  endif
  
  # ECP5-EVN
@@@ -221,13 -216,13 +229,13 @@@ fpga_files = fpga/soc_reset.vhdl 
        fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
        nonrandom.vhdl
  
 -synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 +synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
  
  microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
 -      $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
++      $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
  
  microwatt.v: $(synth_files) $(RAM_INIT_FILE)
-       $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
+       $(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
  
  microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
        $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel