re PR target/84845 (ICE: in extract_insn, at recog.c:2304: unrecognizable insn at...

	PR target/84845
	* config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
	to ...
	(*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this.  If pseudos can't
	be created, use lowpart_subreg of operands[0] rather than operands[0]
	itself.
	(*aarch64_reg_<mode>3_minus_mask): Rename to ...
	(*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
	(*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
	and n constraint instead of aarch64_shift_imm_di and Usd.
	(*aarch64_reg_<optab>_minus<mode>3): Rename to ...
	(*aarch64_<optab>_reg_minus<mode>3): ... this.

	* gcc.c-torture/compile/pr84845.c: New test.

From-SVN: r258678

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 239c28ab33736f07a126ee346436a774c50d7284..b90871616df14f713f4ed9e86ff5693ef78a9544 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2018-03-20  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/84845
+       * config/aarch64/aarch64.md (*aarch64_reg_<mode>3_neg_mask2): Rename
+       to ...
+       (*aarch64_<optab>_reg_<mode>3_neg_mask2): ... this.  If pseudos can't
+       be created, use lowpart_subreg of operands[0] rather than operands[0]
+       itself.
+       (*aarch64_reg_<mode>3_minus_mask): Rename to ...
+       (*aarch64_ashl_reg_<mode>3_minus_mask): ... this.
+       (*aarch64_<optab>_reg_di3_mask2): Use const_int_operand predicate
+       and n constraint instead of aarch64_shift_imm_di and Usd.
+       (*aarch64_reg_<optab>_minus<mode>3): Rename to ...
+       (*aarch64_<optab>_reg_minus<mode>3): ... this.
+
 2018-03-20  Sudakshina Das  <sudi.das@arm.com>
 
        PR target/82989

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 3a848f852d1935d820093c74391accbbd2dc68b7..10fcde6a1b6a5251857f2dd623d61c0dbff06993 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4282,7 +4282,7 @@
   [(set_attr "type" "shift_reg")]
 )
 
-(define_insn_and_split "*aarch64_reg_<mode>3_neg_mask2"
+(define_insn_and_split "*aarch64_<optab>_reg_<mode>3_neg_mask2"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
        (SHIFT:GPI
          (match_operand:GPI 1 "register_operand" "r")
@@ -4295,7 +4295,7 @@
   [(const_int 0)]
   {
     rtx tmp = (can_create_pseudo_p () ? gen_reg_rtx (SImode)
-              : operands[0]);
+              : lowpart_subreg (SImode, operands[0], <MODE>mode));
     emit_insn (gen_negsi2 (tmp, operands[2]));
 
     rtx and_op = gen_rtx_AND (SImode, tmp, operands[3]);
@@ -4306,7 +4306,7 @@
   }
 )
 
-(define_insn_and_split "*aarch64_reg_<mode>3_minus_mask"
+(define_insn_and_split "*aarch64_ashl_reg_<mode>3_minus_mask"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
        (ashift:GPI
          (match_operand:GPI 1 "register_operand" "r")
@@ -4340,8 +4340,8 @@
          (match_operand:DI 1 "register_operand" "r")
          (match_operator 4 "subreg_lowpart_operator"
           [(and:SI (match_operand:SI 2 "register_operand" "r")
-                    (match_operand 3 "aarch64_shift_imm_di" "Usd"))])))]
-  "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1)) == 0)"
+                   (match_operand 3 "const_int_operand" "n"))])))]
+  "((~INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode) - 1)) == 0)"
 {
   rtx xop[3];
   xop[0] = operands[0];
@@ -4353,7 +4353,7 @@
   [(set_attr "type" "shift_reg")]
 )
 
-(define_insn_and_split "*aarch64_reg_<optab>_minus<mode>3"
+(define_insn_and_split "*aarch64_<optab>_reg_minus<mode>3"
   [(set (match_operand:GPI 0 "register_operand" "=&r")
        (ASHIFT:GPI
          (match_operand:GPI 1 "register_operand" "r")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9fbaa3fab528b43ddeb96119d30933b77bfe56e9..26b7e58c9865ec4bc3a0d8ee8156f1225ee17c6a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-20  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/84845
+       * gcc.c-torture/compile/pr84845.c: New test.
+
 2018-03-20  Sudakshina Das  <sudi.das@arm.com>
 
        PR target/82989

diff --git a/gcc/testsuite/gcc.c-torture/compile/pr84845.c b/gcc/testsuite/gcc.c-torture/compile/pr84845.c
new file mode 100644 (file)
index 0000000..1d4ef4a
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr84845.c
@@ -0,0 +1,12 @@
+/* PR target/84845 */
+
+int a, b, c;
+unsigned long d;
+
+void
+foo (void)
+{
+  b = -1;
+  b <<= c >= 0;
+  d = d << (63 & (short)-b) | d >> (63 & -(short)-b);
+}