r600g: add initial evergreen integer opcode support

This just adds the opcodes for evergreen, need to work on r600 and cayman
implementations.

don't advertise nativeintegers yet until we work out all the regressions.

Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 523c5313df26b2efbdf876c5a24efc5c7a77bd51..fc792f1cf71f48ae6aac5be5c77ed630b0086570 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -49,6 +49,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                        return 0;
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
@@ -68,6 +69,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
+               case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
                        return 2;
 
                case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
@@ -101,18 +103,34 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                        return 0;
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
@@ -122,6 +140,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
                        return 2;
 
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
@@ -142,6 +161,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
                case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
+               case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
                        return 1;
                default: R600_ERR(
                        "Need instruction operand number for 0x%x.\n", alu->inst);
@@ -403,7 +423,8 @@ static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_a
        return is_alu_reduction_inst(bc, alu) ||
                is_alu_mova_inst(bc, alu) ||
                (bc->chip_class == EVERGREEN &&
-               alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
+               (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
+               alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR));
 }
 
 /* alu instructions that can only execute on the trans unit */
@@ -450,7 +471,7 @@ static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode
                         * on Evergreen, despite what the documentation says. FLT_TO_INT
                         * can do both vector and scalar. */
                        return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
-                               alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
+                               alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
                                alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
                                alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
                                alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index c37bb729ce38d77147e51341dc2e84eca4aa762b..3b7a9497bcaf61da038ec7d13ab5e23ce6ee68e8 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -981,6 +981,32 @@ static int tgsi_last_instruction(unsigned writemask)
        return lasti;
 }
 
+static int tgsi_int_to_flt(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int i, j, r;
+       int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+
+       for (i = 0; i < lasti + 1; i++) {
+               if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+                       continue;
+
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+
+               alu.inst = ctx->inst_info->r600_opcode;
+               for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
+                       r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
+               }
+               alu.last = 1;
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+       return 0;
+}
+
 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
 {
        struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -1035,6 +1061,37 @@ static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
        return tgsi_op2_s(ctx, 1);
 }
 
+static int tgsi_ineg(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int i, r;
+       int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+
+       for (i = 0; i < lasti + 1; i++) {
+
+               if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+                       continue;
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               alu.inst = ctx->inst_info->r600_opcode;
+
+               alu.src[0].sel = V_SQ_ALU_SRC_0;
+
+               r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
+
+               tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+
+               if (i == lasti) {
+                       alu.last = 1;
+               }
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+       return 0;
+
+}
+
 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
 {
        struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -3205,6 +3262,61 @@ static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
        return 0;
 }
 
+static int tgsi_umad(struct r600_shader_ctx *ctx)
+{
+       struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+       struct r600_bytecode_alu alu;
+       int i, j, r;
+       int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+
+       /* src0 * src1 */
+       for (i = 0; i < lasti + 1; i++) {
+               if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+                       continue;
+
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+
+               alu.dst.chan = i;
+               alu.dst.sel = ctx->temp_reg;
+               alu.dst.write = 1;
+
+               alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT;
+               for (j = 0; j < 2; j++) {
+                       r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
+               }
+
+               if (i == lasti) {
+                       alu.last = 1;
+               }
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+
+
+       for (i = 0; i < lasti + 1; i++) {
+               if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+                       continue;
+
+               memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+               tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+
+               alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT;
+
+               alu.src[0].sel = ctx->temp_reg;
+               alu.src[0].chan = i;
+               
+               r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
+               if (i == lasti) {
+                       alu.last = 1;
+               }
+               r = r600_bytecode_add_alu(ctx->bc, &alu);
+               if (r)
+                       return r;
+       }
+       return 0;
+}
+
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_ARL,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
        {TGSI_OPCODE_MOV,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
@@ -3302,7 +3414,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_POPA,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CEIL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_I2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_NOT,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_NOT,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
        {TGSI_OPCODE_SHL,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        /* gap */
@@ -3310,7 +3422,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_AND,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_OR,        0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_MOD,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_XOR,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_XOR,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
        {TGSI_OPCODE_SAD,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXF,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXQ,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3471,16 +3583,16 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_PUSHA,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_POPA,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_int_to_flt},
+       {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
        {TGSI_OPCODE_SHL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        /* gap */
        {88,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_AND,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_OR,        0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_AND,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
+       {TGSI_OPCODE_OR,        0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
        {TGSI_OPCODE_MOD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_XOR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_XOR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
        {TGSI_OPCODE_SAD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXF,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXQ,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3510,28 +3622,28 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_END,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end},  /* aka HALT */
        /* gap */
        {118,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_F2I,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_F2I,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
        {TGSI_OPCODE_IDIV,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_INEG,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_ISGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
+       {TGSI_OPCODE_IMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
+       {TGSI_OPCODE_INEG,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
+       {TGSI_OPCODE_ISGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
        {TGSI_OPCODE_ISHR,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_ISLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_ISLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
        {TGSI_OPCODE_F2U,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_U2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UADD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_U2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
+       {TGSI_OPCODE_UADD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
        {TGSI_OPCODE_UDIV,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMAD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMAD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
+       {TGSI_OPCODE_UMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
+       {TGSI_OPCODE_UMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
        {TGSI_OPCODE_UMOD,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_UMUL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USEQ,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_UMUL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2},
+       {TGSI_OPCODE_USEQ,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
+       {TGSI_OPCODE_USGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
        {TGSI_OPCODE_USHR,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_USNE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_USLT,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
+       {TGSI_OPCODE_USNE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
        {TGSI_OPCODE_SWITCH,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CASE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_DEFAULT,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3642,7 +3754,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_POPA,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
        {TGSI_OPCODE_SHL,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        /* gap */
@@ -3650,7 +3762,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_AND,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_OR,        0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_MOD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_XOR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_XOR,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
        {TGSI_OPCODE_SAD,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXF,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TXQ,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -3682,8 +3794,8 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {118,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_F2I,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_IDIV,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_IMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_IMAX,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
+       {TGSI_OPCODE_IMIN,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
        {TGSI_OPCODE_INEG,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ISGE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ISHR,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},