arch: Fix all override related warnings.

Clang has started(?) reporting override related warnings, something gcc
apparently did before, but was disabled in the SConstruct. Rather than
disable the warnings in for clang as well, this change fixes the
warnings. A future change will re-enable the warnings for gcc.

Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da
Reviewed-on: https://gem5-review.googlesource.com/9343
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index a43efff9c94110db8433d553d89cb61a0e320342..8f641a4b4581b84b7741327ceb406273c25fc097 100644 (file)
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -81,13 +81,14 @@ output header {{
         {
         }
 
-        AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const;
+        AlphaISA::PCState branchTarget(
+                const AlphaISA::PCState &branchPC) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -109,13 +110,13 @@ output header {{
         {
         }
 
-        AlphaISA::PCState branchTarget(ThreadContext *tc) const;
+        AlphaISA::PCState branchTarget(ThreadContext *tc) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index 36bfde2dd421e8bf1fd2e997906ebfe065e157e2..6e03f4654c392fab222861c45b8a0dc51cb39945 100644 (file)
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -126,8 +126,8 @@ output header {{
 
         // This differs from the AlphaStaticInst version only in
         // printing suffixes for non-default rounding & trapping modes.
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
 }};

diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa
index 265b3c4a92146e977f031f7a190d266f9c45bf30..612ad5f049b194d602be76ed3b752d9244eb265f 100644 (file)
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -49,8 +49,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 4f269b3730eafed437ff5cfa915939c48c4735b7..646286605a59f32db77a16ec2e2182135c560931 100644 (file)
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -232,11 +232,11 @@ output header {{
         /// dependence tag number (FP or int).
         void printReg(std::ostream &os, RegId reg) const;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
 
         void
-        advancePC(AlphaISA::PCState &pcState) const
+        advancePC(AlphaISA::PCState &pcState) const override
         {
             pcState.advance();
         }
@@ -263,8 +263,8 @@ output decoder {{
     }
 
     std::string
-    AlphaStaticInst::generateDisassembly(Addr pc,
-                                         const SymbolTable *symtab) const
+    AlphaStaticInst::generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -304,7 +304,7 @@ def template BasicDeclare {{
         /// Constructor.
         %(class_name)s(ExtMachInst machInst);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -383,10 +383,10 @@ output header {{
 
         ~Nop() { }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 
     /// Helper function for decoding nops.  Substitute Nop object

diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 0c8a404f02b68ac9ed0692cfb46b18f2ab8d86ac..3cdab6f47524c14485f599d4391bffb36e5c16df 100644 (file)
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -51,8 +51,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -88,8 +88,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -129,9 +129,10 @@ def template LoadStoreDeclare {{
         /// Constructor.
         %(class_name)s(ExtMachInst machInst);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa
index 3bd3835a154dc827e8815aa0b9acc58445343202..ae17d59a7b6459ba44bb829673e461bb0ee74eee 100644 (file)
--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -48,10 +48,10 @@ output header {{
         {
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 3913fa82d664fb4237fb192fdce38cca8fbe1098..69b8a477b6245486539344882696ebe7196384da 100644 (file)
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -49,8 +49,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -93,8 +93,8 @@ output header {{
         CallPalBase(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass);
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -157,8 +157,8 @@ output header {{
         /// Constructor
         HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass);
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -239,8 +239,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index 39f17766321afd75f451c2f545ddcdcd4408ce7c..e5a773d700f481d17e6863c2a3fa88e43b814255 100644 (file)
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -53,10 +53,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -84,10 +84,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -163,10 +163,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh
index 48881e0c214ea3bd662db0c5d385b7c850e1505a..731c1869cc70a32b72b227a5b7426faa34d3b4e7 100644 (file)
--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -55,12 +55,14 @@ class BranchImm64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
     {}
 
-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with an immediate
@@ -75,7 +77,8 @@ class BranchImmCond64 : public BranchImm64
         BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with a register
@@ -90,7 +93,8 @@ class BranchReg64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Ret instruction
@@ -102,7 +106,8 @@ class BranchRet64 : public BranchReg64
         BranchReg64(mnem, _machInst, __opClass, _op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Eret instruction
@@ -113,7 +118,8 @@ class BranchEret64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with an immediate and a register
@@ -129,12 +135,14 @@ class BranchImmReg64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
     {}
 
-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with two immediates
@@ -153,12 +161,14 @@ class BranchImmImmReg64 : public ArmStaticInst
         imm1(_imm1), imm2(_imm2), op1(_op1)
     {}
 
-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 }

diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh
index 8c0677b3d2be5fa4ddffbfd97668dc5b8d90fa3c..d423802b5fe2558cc3004c189bc8edd0feb65279 100644 (file)
--- a/src/arch/arm/insts/data64.hh
+++ b/src/arch/arm/insts/data64.hh
@@ -57,7 +57,8 @@ class DataXImmOp : public ArmStaticInst
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXImmOnlyOp : public ArmStaticInst
@@ -72,7 +73,8 @@ class DataXImmOnlyOp : public ArmStaticInst
         dest(_dest), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXSRegOp : public ArmStaticInst
@@ -90,7 +92,8 @@ class DataXSRegOp : public ArmStaticInst
         shiftAmt(_shiftAmt), shiftType(_shiftType)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXERegOp : public ArmStaticInst
@@ -108,7 +111,8 @@ class DataXERegOp : public ArmStaticInst
         extendType(_extendType), shiftAmt(_shiftAmt)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX1RegOp : public ArmStaticInst
@@ -121,7 +125,8 @@ class DataX1RegOp : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX1RegImmOp : public ArmStaticInst
@@ -136,7 +141,8 @@ class DataX1RegImmOp : public ArmStaticInst
         imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX1Reg2ImmOp : public ArmStaticInst
@@ -152,7 +158,8 @@ class DataX1Reg2ImmOp : public ArmStaticInst
         imm1(_imm1), imm2(_imm2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX2RegOp : public ArmStaticInst
@@ -166,7 +173,8 @@ class DataX2RegOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX2RegImmOp : public ArmStaticInst
@@ -182,7 +190,8 @@ class DataX2RegImmOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataX3RegOp : public ArmStaticInst
@@ -197,7 +206,8 @@ class DataX3RegOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), op3(_op3)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXCondCompImmOp : public ArmStaticInst
@@ -215,7 +225,8 @@ class DataXCondCompImmOp : public ArmStaticInst
         op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXCondCompRegOp : public ArmStaticInst
@@ -232,7 +243,8 @@ class DataXCondCompRegOp : public ArmStaticInst
         op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataXCondSelOp : public ArmStaticInst
@@ -248,7 +260,8 @@ class DataXCondSelOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 }

diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 412337d06f7538a67814e54db0117970f8473312..b974e268e1755331dce56d072ea9448540492b8c 100644 (file)
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -73,7 +73,7 @@ class MicroOp : public PredOp
 
   public:
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop]) {
             pcState.uEnd();
@@ -94,7 +94,7 @@ class MicroOpX : public ArmStaticInst
 
   public:
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         if (flags[IsLastMicroop]) {
             pcState.uEnd();
@@ -263,7 +263,8 @@ class MicroSetPCCPSR : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -281,7 +282,8 @@ class MicroIntMov : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -300,7 +302,8 @@ class MicroIntImmOp : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MicroIntImmXOp : public MicroOpX
@@ -316,7 +319,8 @@ class MicroIntImmXOp : public MicroOpX
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -334,7 +338,8 @@ class MicroIntOp : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MicroIntRegXOp : public MicroOp
@@ -353,7 +358,8 @@ class MicroIntRegXOp : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -392,7 +398,8 @@ class MicroMemOp : public MicroIntImmOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MicroMemPairOp : public MicroOp
@@ -412,7 +419,8 @@ class MicroMemPairOp : public MicroOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**

diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index ddd1966765e97ba002906d35351bebc80d836f94..da4dac3f344081c5f7d8a23cef88533f75f5ec61 100644 (file)
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -60,7 +60,8 @@ class Swap : public PredOp
           dest(_dest), op1(_op1), base(_base)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MightBeMicro : public PredOp
@@ -118,13 +119,14 @@ class RfeOp : public MightBeMicro
     }
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         assert(uops != NULL && microPC < numMicroops);
         return uops[microPC];
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // The address is a base register plus an immediate.
@@ -158,13 +160,14 @@ class SrsOp : public MightBeMicro
     }
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         assert(uops != NULL && microPC < numMicroops);
         return uops[microPC];
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class Memory : public MightBeMicro
@@ -198,7 +201,7 @@ class Memory : public MightBeMicro
     }
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         assert(uops != NULL && microPC < numMicroops);
         return uops[microPC];

diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 7ad2f52eb1afcd5817a8a9bb9750ec0a277454d5..4f662831d06ce2f8e3aa5aa98ab2dd8b3d5eb7bb 100644 (file)
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -56,7 +56,8 @@ class SysDC64 : public ArmStaticInst
         : ArmStaticInst(mnem, _machInst, __opClass), base(_base),
           dest((IntRegIndex)miscReg), imm(_imm)
     {}
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MightBeMicro64 : public ArmStaticInst
@@ -113,7 +114,7 @@ class Memory64 : public MightBeMicro64
     }
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         assert(uops != NULL && microPC < numMicroops);
         return uops[microPC];
@@ -136,7 +137,8 @@ class MemoryImm64 : public Memory64
         : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryDImm64 : public MemoryImm64
@@ -151,7 +153,8 @@ class MemoryDImm64 : public MemoryImm64
           dest2(_dest2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryDImmEx64 : public MemoryDImm64
@@ -166,7 +169,8 @@ class MemoryDImmEx64 : public MemoryDImm64
                      _base, _imm), result(_result)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryPreIndex64 : public MemoryImm64
@@ -178,7 +182,8 @@ class MemoryPreIndex64 : public MemoryImm64
         : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryPostIndex64 : public MemoryImm64
@@ -190,7 +195,8 @@ class MemoryPostIndex64 : public MemoryImm64
         : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryReg64 : public Memory64
@@ -208,7 +214,8 @@ class MemoryReg64 : public Memory64
           offset(_offset), type(_type), shiftAmt(_shiftAmt)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryRaw64 : public Memory64
@@ -219,7 +226,8 @@ class MemoryRaw64 : public Memory64
         : Memory64(mnem, _machInst, __opClass, _dest, _base)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryEx64 : public Memory64
@@ -233,7 +241,8 @@ class MemoryEx64 : public Memory64
         : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MemoryLiteral64 : public Memory64
@@ -246,7 +255,8 @@ class MemoryLiteral64 : public Memory64
         : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 }
 

diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 5c387a5007a8cbb942d12c806538cebbaed5f35c..a036b2e114b6ecfb76ec3a97925f07e834b3ece0 100644 (file)
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -52,7 +52,8 @@ class MrsOp : public PredOp
         PredOp(mnem, _machInst, __opClass), dest(_dest)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MsrBase : public PredOp
@@ -78,7 +79,8 @@ class MsrImmOp : public MsrBase
         MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MsrRegOp : public MsrBase
@@ -91,7 +93,8 @@ class MsrRegOp : public MsrBase
         MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MrrcOp : public PredOp
@@ -109,7 +112,8 @@ class MrrcOp : public PredOp
         dest2(_dest2), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class McrrOp : public PredOp
@@ -127,7 +131,8 @@ class McrrOp : public PredOp
         dest(_dest), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class ImmOp : public PredOp
@@ -140,7 +145,8 @@ class ImmOp : public PredOp
         PredOp(mnem, _machInst, __opClass), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegImmOp : public PredOp
@@ -154,7 +160,8 @@ class RegImmOp : public PredOp
         PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegOp : public PredOp
@@ -168,7 +175,8 @@ class RegRegOp : public PredOp
         PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegImmRegOp : public PredOp
@@ -184,7 +192,8 @@ class RegImmRegOp : public PredOp
         dest(_dest), imm(_imm), op1(_op1)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegRegImmOp : public PredOp
@@ -202,7 +211,8 @@ class RegRegRegImmOp : public PredOp
         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegRegRegOp : public PredOp
@@ -220,7 +230,8 @@ class RegRegRegRegOp : public PredOp
         dest(_dest), op1(_op1), op2(_op2), op3(_op3)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegRegOp : public PredOp
@@ -236,7 +247,8 @@ class RegRegRegOp : public PredOp
         dest(_dest), op1(_op1), op2(_op2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegImmOp : public PredOp
@@ -253,7 +265,8 @@ class RegRegImmOp : public PredOp
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MiscRegRegImmOp : public PredOp
@@ -270,7 +283,8 @@ class MiscRegRegImmOp : public PredOp
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegMiscRegImmOp : public PredOp
@@ -287,7 +301,8 @@ class RegMiscRegImmOp : public PredOp
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegImmImmOp : public PredOp
@@ -303,7 +318,8 @@ class RegImmImmOp : public PredOp
         dest(_dest), imm1(_imm1), imm2(_imm2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegImmImmOp : public PredOp
@@ -321,7 +337,8 @@ class RegRegImmImmOp : public PredOp
         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegImmRegShiftOp : public PredOp
@@ -341,7 +358,8 @@ class RegImmRegShiftOp : public PredOp
         shiftAmt(_shiftAmt), shiftType(_shiftType)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class UnknownOp : public PredOp
@@ -352,7 +370,8 @@ class UnknownOp : public PredOp
         PredOp(mnem, _machInst, __opClass)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 #endif

diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 3b1347651e3f78d3ea7341b29ab57cd621b29775..961df65d803a045e0bcf7020f04d73976e2a7e3a 100644 (file)
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -52,7 +52,8 @@ class ImmOp64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegImmImmOp64 : public ArmStaticInst
@@ -70,7 +71,8 @@ class RegRegImmImmOp64 : public ArmStaticInst
         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegRegRegImmOp64 : public ArmStaticInst
@@ -88,7 +90,8 @@ class RegRegRegImmOp64 : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class UnknownOp64 : public ArmStaticInst
@@ -99,7 +102,8 @@ class UnknownOp64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class MiscRegRegImmOp64 : public ArmStaticInst
@@ -116,7 +120,8 @@ class MiscRegRegImmOp64 : public ArmStaticInst
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class RegMiscRegImmOp64 : public ArmStaticInst
@@ -133,7 +138,8 @@ class RegMiscRegImmOp64 : public ArmStaticInst
         dest(_dest), op1(_op1), imm(_imm)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 #endif

diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index ce4d41bacfa9a5699f6f2148688a62e0680c0bf3..d2a9f7080e7d0a8e25ff720073abb5a6f37c80d3 100644 (file)
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -223,7 +223,8 @@ class PredImmOp : public PredOp
             rotated_carry = bits(rotated_imm, 31);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -243,7 +244,8 @@ class PredIntOp : public PredOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataImmOp : public PredOp
@@ -261,7 +263,8 @@ class DataImmOp : public PredOp
         dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataRegOp : public PredOp
@@ -279,7 +282,8 @@ class DataRegOp : public PredOp
         shiftAmt(_shiftAmt), shiftType(_shiftType)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class DataRegRegOp : public PredOp
@@ -296,7 +300,8 @@ class DataRegRegOp : public PredOp
         shiftType(_shiftType)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -327,19 +332,20 @@ class PredMacroOp : public PredOp
     }
 
     StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
     {
         assert(microPC < numMicroops);
         return microOps[microPC];
     }
 
     Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
     {
         panic("Execute method called when it shouldn't!");
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**

diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index 5fb7499df4ff1a831e8fc7d3640609d88eb3b0ad..ececbbb86dac1c892c62ad6a752cc76aa9481f0f 100644 (file)
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -56,9 +56,11 @@ class DecoderFaultInst : public ArmStaticInst
   public:
     DecoderFaultInst(ExtMachInst _machInst);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -80,10 +82,11 @@ class FailUnimplemented : public ArmStaticInst
     FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
                       const std::string& _fullMnemonic);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -109,10 +112,11 @@ class WarnUnimplemented : public ArmStaticInst
     WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
                       const std::string& _fullMnemonic);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -131,10 +135,11 @@ class McrMrcMiscInst : public ArmStaticInst
     McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
                    uint64_t _iss, MiscRegIndex _miscReg);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
 };
 
@@ -148,10 +153,11 @@ class McrMrcImplDefined : public McrMrcMiscInst
     McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
                       uint64_t _iss, MiscRegIndex _miscReg);
 
-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;
 
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
 };
 

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 3ed374ab12dc80fed3e418fc56ae890f188e9015..69ae58e66bb56392034d18b00e4dd6fb60fb669f 100644 (file)
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -188,12 +188,13 @@ class ArmStaticInst : public StaticInst
                        uint64_t imm) const;
 
     void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
     {
         pcState.advance();
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
     static inline uint32_t
     cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,

diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index caa22376e9a62061ca5dfdda5a4d647dead07d99..ac20643b84bcbbec126a5da6a138885f53e86bb4 100644 (file)
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -890,7 +890,8 @@ class FpCondCompRegOp : public FpOp
         op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpCondSelOp : public FpOp
@@ -906,7 +907,8 @@ class FpCondSelOp : public FpOp
         dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegOp : public FpOp
@@ -923,7 +925,8 @@ class FpRegRegOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegImmOp : public FpOp
@@ -940,7 +943,8 @@ class FpRegImmOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegImmOp : public FpOp
@@ -958,7 +962,8 @@ class FpRegRegImmOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegOp : public FpOp
@@ -976,7 +981,8 @@ class FpRegRegRegOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegCondOp : public FpOp
@@ -997,7 +1003,8 @@ class FpRegRegRegCondOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegRegOp : public FpOp
@@ -1017,7 +1024,8 @@ class FpRegRegRegRegOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegImmOp : public FpOp
@@ -1038,7 +1046,8 @@ class FpRegRegRegImmOp : public FpOp
         setVfpMicroFlags(mode, flags);
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 }

diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa
index 4db470b1e1cad1cf65566d29ce4fa6a74064f105..4f281e045d0d0d8ccfd34c001fab80575c74f9f2 100644 (file)
--- a/src/arch/arm/isa/formats/breakpoint.isa
+++ b/src/arch/arm/isa/formats/breakpoint.isa
@@ -63,10 +63,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index ebfddb0a67b88adfc01040af46c3c0a9553b33d1..1165a1e2a110e3176594a25efbce34ef06585c14 100644 (file)
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -50,7 +50,8 @@ def template BasicDeclare {{
           public:
                 /// Constructor.
                 %(class_name)s(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
         };
 }};
 

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 54821e7c82118705a976a3a22e04eafc24429e73..440adb4c5947e230910b0daa16e185eb67a81133 100644 (file)
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, int32_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -72,8 +72,9 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, int32_t _imm,
                        ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        ArmISA::PCState branchTarget(
+                const ArmISA::PCState &branchPC) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
@@ -105,7 +106,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -135,7 +136,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                        ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -167,7 +168,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -178,9 +179,10 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 };
 }};
 
@@ -209,8 +211,9 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        int32_t imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        ArmISA::PCState branchTarget(
+                const ArmISA::PCState &branchPC) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;

diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa
index c55d20541d328d71cd9a23e4bdbc99df51f277f6..6eadf3c7c89fcd97ea2e63356b1f7941b0155a8c 100644 (file)
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, int64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, int64_t _imm,
                        ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        int64_t imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
                        IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa
index 85dde6bed9e34cbd66d7019af6b75dd2d59fa7c6..02c0fdd927817172e67326a5321f4a8dac146d5b 100644 (file)
--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, IntRegIndex _op2,
                 int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, IntRegIndex _op2,
                 ArmExtendType _extendType, int32_t _shiftAmt);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                        uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                        IntRegIndex _op2, ConditionCode _condCode,
                        uint8_t _defCc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _op1, IntRegIndex _op2,
                        ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index b0e3d29fded2594abffbc26fa07ef3d6761eae67..37d0608c0c4dd7ef241029a0ee967a1b3176a51b 100644 (file)
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -53,9 +53,10 @@ def template MicroMemDeclare {{
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb, bool _up,
                        uint8_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -85,9 +86,10 @@ def template MicroMemPairDeclare {{
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
                        bool _up, uint8_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -134,9 +136,10 @@ def template MicroNeonMemDeclare {{
             }
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -154,7 +157,7 @@ def template MicroSetPCCPSRDeclare {{
                        IntRegIndex _ura,
                        IntRegIndex _urb,
                        IntRegIndex _urc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -189,7 +192,7 @@ def template MicroIntDeclare {{
       public:
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb, RegIndex _urc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -251,7 +254,7 @@ def template MicroNeonMixDeclare {{
             }
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -304,7 +307,7 @@ def template MicroNeonMixLaneDeclare {{
             }
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -319,7 +322,7 @@ def template MicroIntMovDeclare {{
       public:
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 def template MicroIntMovConstructor {{
@@ -350,7 +353,7 @@ def template MicroIntImmDeclare {{
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb,
                        int32_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -390,7 +393,7 @@ def template MicroIntRegDeclare {{
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb, RegIndex _urc,
                        int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -412,7 +415,7 @@ def template MicroIntXERegDeclare {{
         %(class_name)s(ExtMachInst machInst,
                        RegIndex _ura, RegIndex _urb, RegIndex _urc,
                        ArmExtendType _type, uint32_t _shiftAmt);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 38f5d2051b747892595f187961a81ae0f4764759..aa63d4b57bf15992ea4d3f9c62df4f5cff5c7eed 100644 (file)
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -582,9 +582,10 @@ def template RfeDeclare {{
         %(class_name)s(ExtMachInst machInst,
                 uint32_t _base, int _mode, bool _wb);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -600,9 +601,10 @@ def template SrsDeclare {{
         %(class_name)s(ExtMachInst machInst,
                 uint32_t _regMode, int _mode, bool _wb);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -618,9 +620,10 @@ def template SwapDeclare {{
         %(class_name)s(ExtMachInst machInst,
                 uint32_t _dest, uint32_t _op1, uint32_t _base);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -637,9 +640,10 @@ def template LoadStoreDImmDeclare {{
                 uint32_t _dest, uint32_t _dest2,
                 uint32_t _base, bool _add, int32_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -656,9 +660,10 @@ def template StoreExDImmDeclare {{
                 uint32_t _result, uint32_t _dest, uint32_t _dest2,
                 uint32_t _base, bool _add, int32_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -674,12 +679,14 @@ def template LoadStoreImmDeclare {{
         %(class_name)s(ExtMachInst machInst,
                 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -698,9 +705,10 @@ def template StoreExImmDeclare {{
                 uint32_t _result, uint32_t _dest, uint32_t _base,
                 bool _add, int32_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -719,9 +727,10 @@ def template StoreDRegDeclare {{
                 int32_t _shiftAmt, uint32_t _shiftType,
                 uint32_t _index);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -739,12 +748,14 @@ def template StoreRegDeclare {{
                 int32_t _shiftAmt, uint32_t _shiftType,
                 uint32_t _index);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -765,9 +776,10 @@ def template LoadDRegDeclare {{
                 int32_t _shiftAmt, uint32_t _shiftType,
                 uint32_t _index);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -785,12 +797,14 @@ def template LoadRegDeclare {{
                 int32_t _shiftAmt, uint32_t _shiftType,
                 uint32_t _index);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -808,12 +822,14 @@ def template LoadImmDeclare {{
         %(class_name)s(ExtMachInst machInst,
                 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };

diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index a44a3cd25528f049a1b15797bd4d14db7ae10e90..bb8594cfe02a0af56704bd5d163c8b4e99126965 100644 (file)
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -259,12 +259,14 @@ def template DCStore64Declare {{
         %(class_name)s(ExtMachInst machInst, IntRegIndex _base,
                        MiscRegIndex _dest, uint64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
-
-        virtual void
-        annotateFault(ArmFault *fault) {
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
+
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -342,12 +344,14 @@ def template LoadStoreImm64Declare {{
         %(class_name)s(ExtMachInst machInst,
                 IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -364,12 +368,14 @@ def template LoadStoreImmU64Declare {{
                 bool noAlloc = false, bool exclusive = false,
                 bool acrel = false);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -386,12 +392,14 @@ def template LoadStoreImmDU64Declare {{
                 int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
                 bool acrel = false);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -410,9 +418,10 @@ def template StoreImmDEx64Declare {{
                 IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
                 IntRegIndex _base, int64_t _imm = 0);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -427,12 +436,14 @@ def template LoadStoreReg64Declare {{
                 IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
                 ArmExtendType _type, uint32_t _shiftAmt);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -450,12 +461,14 @@ def template LoadStoreRegU64Declare {{
                 bool noAlloc = false, bool exclusive = false,
                 bool acrel = false);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -470,12 +483,14 @@ def template LoadStoreRaw64Declare {{
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _base);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -490,12 +505,14 @@ def template LoadStoreEx64Declare {{
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        IntRegIndex _base, IntRegIndex _result);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -509,12 +526,14 @@ def template LoadStoreLit64Declare {{
         /// Constructor.
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };
@@ -530,12 +549,14 @@ def template LoadStoreLitU64Declare {{
                 bool noAlloc = false, bool exclusive = false,
                 bool acrel = false);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 
-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
             %(fa_code)s
         }
     };

diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 6d63b8e145bf6ddcde46fc0ddf1b25a6f1f3dbc5..e57b9e4aff8ed6ef1658d231f1022c6e7afe26b9 100644 (file)
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                        uint8_t _sysM, bool _r);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                        uint8_t _sysM, bool _r);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
                        IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
                        MiscRegIndex _dest, uint32_t imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s
     public:
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                        uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1,
                        IntRegIndex _op2, IntRegIndex _op3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1,
                        uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        MiscRegIndex _dest, IntRegIndex _op1,
                        uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, MiscRegIndex _op1,
                        uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1,
                        uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
                        int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -623,9 +623,10 @@ def template MiscRegRegImmMemOpDeclare {{
       %(class_name)s(ExtMachInst machInst,
                      MiscRegIndex _dest, IntRegIndex _op1,
                      uint64_t _imm);
-      Fault execute(ExecContext *, Trace::InstRecord *) const;
-      Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-      Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+      Fault execute(ExecContext *, Trace::InstRecord *) const override;
+      Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+      Fault completeAcc(PacketPtr, ExecContext *,
+                        Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index 3811cb56af729177805c16bed6cf91cd4f33b31b..3c830c858e5a091c6236e08e2929c70d6b3d548b 100644 (file)
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst,uint64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -66,7 +66,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1,
                        uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _dest, IntRegIndex _op1,
                        IntRegIndex _op2, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -117,7 +117,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
                 IntRegIndex _op1, uint64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 MiscRegIndex _op1, uint64_t _imm);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index 87d96f7438b28b1abf707890a21620b7e1da5688..96c61fb28b5863724410d43609b7c22d669ba4d7 100644 (file)
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
                        IntRegIndex _reg1, IntRegIndex _reg2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst,
                        IntRegIndex _reg0, IntRegIndex _reg1,
                        IntRegIndex _reg2, IntRegIndex _reg3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 5cde08dcf81d42ee013835e06d58443f75741f20..35bd3865effb06d1558853ffe979ea5b5a6d4f87 100644 (file)
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s
         }
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s
         }
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s
         }
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s
         }
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s
         }
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa
index 15393361120d04a43f724d8f0928cbfbfb0de19b..26e6d98b53978655d36c5f84e2c4477033fa1b55 100644 (file)
--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s
         %(constructor)s;
     }
 
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -267,9 +267,10 @@ def template MicroNeonMemDeclare64 {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 
@@ -477,7 +478,7 @@ def template MicroNeonMixDeclare64 {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 
@@ -496,7 +497,7 @@ def template MicroNeonMixLaneDeclare64 {{
             %(constructor)s;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index d2060a7cdae74cdd606c46d80e9049108172552c..dccdea60a205c91d9e745e242540d19c12faaca7 100644 (file)
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s
         // Constructor
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, IntRegIndex _op2,
                 int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s
         %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
                 ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index c5765f21e6e0ed965e819e21d15b44ead3aeeac4..c0859e311c6e245bb34c952800831440d85bdfc6 100644 (file)
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s
     %(class_name)s(ExtMachInst machInst,
                    IntRegIndex _dest, IntRegIndex _op1,
                    VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
     // Constructor
     %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
             uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s
     %(class_name)s(ExtMachInst machInst,
                    IntRegIndex _dest, IntRegIndex _op1,
                    uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s
     %(class_name)s(ExtMachInst machInst,
                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                    VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s
                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   ConditionCode _cond,
                    VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa
index 64932336fa154826e99bb57669097525bd17a706..f228356be54824f293c0ee8cec833a6657dbeac3 100644 (file)
--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s
     %(class_name)s(ExtMachInst machInst,
                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                    IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 3759390d152fffaad0d5f2b01de01a1c7fc8c731..e3b0f19d3046be1a07023900c3f939047a6d4f72 100644 (file)
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -55,11 +55,12 @@ output header {{
         /// dependence tag number (FP or int).
         void printReg(std::ostream &os, RegId reg) const;
 
-        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
 
       public:
         void
-        advancePC(MipsISA::PCState &pc) const
+        advancePC(MipsISA::PCState &pc) const override
         {
             pc.advance();
         }

diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index b824fda18cd3994e6c4906ba5548a556b36f6b30..bb974124ef46c4fb466334f0a20b3b3c9a821880 100644 (file)
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -41,7 +41,8 @@ def template BasicDeclare {{
           public:
                 /// Constructor.
                 %(class_name)s(MachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
         };
 }};
 

diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index f826e10831d68e34e462be9d966eb4ab1a8eb2fe..ad54065c2b551f6a48f07a460d4fdb692e45a860 100644 (file)
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -89,13 +89,14 @@ output header {{
             }
         }
 
-        MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
+        MipsISA::PCState branchTarget(
+                const MipsISA::PCState &branchPC) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -119,13 +120,13 @@ output header {{
         {
         }
 
-        MipsISA::PCState branchTarget(ThreadContext *tc) const;
+        MipsISA::PCState branchTarget(ThreadContext *tc) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 00600712c2255837eda9b3ae6cb30ac29dda906c..12d4694014dc7c20d9878bf603a9d03ad458dcc2 100644 (file)
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -47,7 +47,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
         class CP0TLB : public MipsStaticInst
         {
@@ -59,7 +60,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
 
@@ -73,7 +75,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
 }};

diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index eb5e5765a8e17ceddaa757f5307bbf1c9e93559a..f4f05ea48622859e72014ea034816f201a047480 100644 (file)
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -46,8 +46,6 @@ output header {{
                 {
                 }
 
-            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
                 //needs function to check for fpEnable or not
         };
 
@@ -58,8 +56,8 @@ output header {{
                 {
                 }
 
-            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
+            std::string generateDisassembly(
+                    Addr pc, const SymbolTable *symtab) const override;
         };
 }};
 

diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 9f43ac275dfa5b17022485b3d0a6a27ebfe53632..f2867bfcac78adb6b751ace1e19456b26b546059 100644 (file)
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -48,7 +48,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
 
@@ -62,7 +63,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
         class HiLoRsSelOp: public HiLoOp
@@ -75,7 +77,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
         class HiLoRdSelOp: public HiLoOp
@@ -88,7 +91,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
         class HiLoRdSelValOp: public HiLoOp
@@ -101,7 +105,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
         class IntImmOp : public MipsStaticInst
@@ -124,9 +129,8 @@ output header {{
                     }
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
-
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
 }};

diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 4e1009e9c83def2ff6eba5bd0d50c66a8bc09fa0..7349516b68403371dc132612e9ba95315a8e2f54 100644 (file)
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -54,8 +54,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
      /**
@@ -71,8 +71,8 @@ output header {{
         {
         }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 
@@ -142,9 +142,10 @@ def template LoadStoreDeclare {{
         /// Constructor.
         %(class_name)s(ExtMachInst machInst);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(Packet *, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index b9ee07010870049216d51ecc35f34de9644ece85..a68d74ce7438fd0a22a955f5ed7a6e844f6cc8c0 100644 (file)
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -47,7 +47,8 @@ output header {{
                 {
                 }
 
-               std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+               std::string generateDisassembly(
+                       Addr pc, const SymbolTable *symtab) const override;
 
                 bool user_mode;
         };
@@ -62,8 +63,6 @@ output header {{
                 {
                     user_mode = true;
                 }
-
-            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
         };
 }};
 

diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index f33c1130c6fa558827de5200b2bb7d0dd45bd08a..93e58ab34292beaaa5b3f2801a3607649711dc6c 100644 (file)
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -53,10 +53,10 @@ output header {{
 
         ~Nop() { }
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index 4ec1d267e870ab247741cdf2649bd33e607bc00b..58137f29475f7371a04ad505127818e971e2f21f 100644 (file)
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -46,7 +46,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 }};
 

diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 5133899ea0d51e710ff1ea823225a8c0fd66eccc..1fe1a91d0568d3dbee212046056ffac48adbfea3 100644 (file)
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -47,7 +47,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
         class TrapImm : public MipsStaticInst
         {
@@ -61,9 +62,8 @@ output header {{
                 {
                 }
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
-
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
         };
 
 }};

diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index fb0051b4fa0e54192c7052bec773e975d273171c..93760913a3790d422d58103a42371b8ce3c41019 100644 (file)
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -53,10 +53,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
     class CP0Unimplemented : public MipsStaticInst
     {
@@ -70,10 +70,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
     class CP1Unimplemented : public MipsStaticInst
     {
@@ -87,10 +87,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
     class CP2Unimplemented : public MipsStaticInst
     {
@@ -104,10 +104,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -135,10 +135,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index 65fd18f7a8d619d9a2e94f52655d1bc288fc7c9f..83fa4f0c5c64ea7139e1eb949906b4a8e753a748 100644 (file)
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -51,10 +51,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 762e55a66311b8857e11cd9a6f4fde2c61d9fdfe..b368fed888778c0f292630352e6b63ef853b0e63 100644 (file)
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -86,12 +86,13 @@ class BranchPCRel : public PCDependentDisassembly
         }
     }
 
-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -115,12 +116,13 @@ class BranchNonPCRel : public PCDependentDisassembly
         }
     }
 
-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -193,12 +195,13 @@ class BranchPCRelCond : public BranchCond
         }
     }
 
-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -222,12 +225,13 @@ class BranchNonPCRelCond : public BranchCond
         }
     }
 
-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -243,12 +247,13 @@ class BranchRegCond : public BranchCond
     {
     }
 
-    PowerISA::PCState branchTarget(ThreadContext *tc) const;
+    PowerISA::PCState branchTarget(ThreadContext *tc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
index e5112b2c1c585c9032bbce4af296aed1c093da22..f9753f72add817bfe02942d274bc9d983d50ba03 100644 (file)
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -57,7 +57,8 @@ class CondLogicOp : public PowerStaticInst
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -78,7 +79,8 @@ class CondMoveOp : public PowerStaticInst
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
index 65906e507bb504d7256905f0169b9415c4cd2582..551573f3a36429ec28165801cff1ad30f72d8f60 100644 (file)
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -145,7 +145,8 @@ class FloatOp : public PowerStaticInst
         return c;
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index f911eb08aea4a43f38499ec2d392a1cf7466e6ec..1aadd24901c17effacf98fadf08a03579f498c0f 100644 (file)
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -91,7 +91,8 @@ class IntOp : public PowerStaticInst
         return c;
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 
@@ -113,7 +114,8 @@ class IntImmOp : public IntOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 
@@ -133,7 +135,8 @@ class IntShiftOp : public IntOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 
@@ -168,7 +171,8 @@ class IntRotateOp : public IntShiftOp
         return (rs << n) | (rs >> (32 - n));
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index 0a8dc4946666c8144bc52f47cfe37bcea6a53714..6c41b1636e1922b02322887ecd95bc19b003d970 100644 (file)
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -53,7 +53,8 @@ class MemOp : public PowerStaticInst
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 
@@ -72,7 +73,8 @@ class MemDispOp : public MemOp
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
index d6a73d25469f1158f0139dbb989daacca461e29e..4d9e23ab0fb127900ce2a06aaea523150d277ea0 100644 (file)
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -49,7 +49,8 @@ class MiscOp : public PowerStaticInst
     {
     }
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA

diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index f4f1bec7b0d7f1b991ff711e720403f98e89e38a..d154aafb838a857c1f0ca68b5701f90c328a0c62 100644 (file)
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -61,11 +61,11 @@ class PowerStaticInst : public StaticInst
     void
     printReg(std::ostream &os, RegId reg) const;
 
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
     void
-    advancePC(PowerISA::PCState &pcState) const
+    advancePC(PowerISA::PCState &pcState) const override
     {
         pcState.advance();
     }

diff --git a/src/arch/power/isa/formats/basic.isa b/src/arch/power/isa/formats/basic.isa
index 8adce1c7b434ca32c002ff747aab4f44eecfe000..e65fe2df41da891aa955e4bbe25a31e6b2f470d7 100644 (file)
--- a/src/arch/power/isa/formats/basic.isa
+++ b/src/arch/power/isa/formats/basic.isa
@@ -38,7 +38,8 @@ def template BasicDeclare {{
           public:
                 /// Constructor.
                 %(class_name)s(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
         };
 }};
 

diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 719cb39a462f1bfffff5acccd5ac8a74419865f3..47ffc916bfe7df493afed5b8784b3502678942ec 100644 (file)
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -44,9 +44,10 @@ def template LoadStoreDeclare {{
         /// Constructor.
         %(class_name)s(ExtMachInst machInst);
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
     };
 }};
 

diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa
index f9af7f0fc59b3501b3edb62c9b8766dc6e74288e..4c49ffac73a5262fd41f6765987bd2446e11c4c5 100644 (file)
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -55,10 +55,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 
     /**
@@ -86,10 +86,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa
index f8cd3bf43035c13e94869ec0b1ee5004190b26e7..ee4bc2a529cca76ec48a6d9ff543ead94a0990cd 100644 (file)
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -53,10 +53,10 @@ output header {{
             flags[IsNonSpeculative] = true;
         }
 
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
     };
 }};
 

diff --git a/src/arch/riscv/insts/static_inst.hh b/src/arch/riscv/insts/static_inst.hh
index 3f6d58654ffd118c8f0e4fe28d396cda3614bae3..8ceb9849071bd5d9dcf21fdab02d9fe7ad970637 100644 (file)
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -51,11 +51,8 @@ class RiscvStaticInst : public StaticInst
   protected:
     using StaticInst::StaticInst;
 
-    virtual std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
-
   public:
-    void advancePC(PCState &pc) const { pc.advance(); }
+    void advancePC(PCState &pc) const override { pc.advance(); }
 
     size_t
     asBytes(void *buf, size_t size) override
@@ -120,7 +117,7 @@ class RiscvMicroInst : public RiscvStaticInst
         flags[IsMicroop] = true;
     }
 
-    void advancePC(PCState &pcState) const;
+    void advancePC(PCState &pcState) const override;
 };
 
 }

diff --git a/src/arch/sparc/insts/nop.cc b/src/arch/sparc/insts/nop.cc
index d1257907fbf2a836ee3b388c1f3826c0387d5289..a45df64f4b310773959ed0df4983bebc93213d37 100644 (file)
--- a/src/arch/sparc/insts/nop.cc
+++ b/src/arch/sparc/insts/nop.cc
@@ -57,7 +57,7 @@ output header {{
             }
 
             std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
+                    const SymbolTable *symtab) const override;
         };
 }};
 

diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh
index 6530d09f865a835e49cde5caaf92ca934c045ddc..c4681da0738379ecae3273b78715e6aabbc56ce1 100644 (file)
--- a/src/arch/sparc/insts/priv.hh
+++ b/src/arch/sparc/insts/priv.hh
@@ -46,7 +46,8 @@ class Priv : public SparcStaticInst
 {
   protected:
     using SparcStaticInst::SparcStaticInst;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 class PrivReg : public Priv
@@ -66,7 +67,8 @@ class RdPriv : public PrivReg
 {
   protected:
     using PrivReg::PrivReg;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 // This class is for instructions that explicitly write control
@@ -75,7 +77,8 @@ class WrPriv : public PrivReg
 {
   protected:
     using PrivReg::PrivReg;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 
 /**
@@ -103,11 +106,12 @@ class WrPrivImm : public PrivImm
         PrivImm(mnem, _machInst, __opClass), regName(_regName)
     {}
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
     char const *regName;
-}
-;
+};
+
 }
 
 #endif //__ARCH_SPARC_INSTS_PRIV_HH__

diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh
index 9e15c8dab0a899d8bead98efa4c7fc0c098c21fb..32930fb9f3c6984cc0a739b051fbf27c4885a0a0 100644 (file)
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -90,7 +90,8 @@ class SparcStaticInst : public StaticInst
   protected:
     using StaticInst::StaticInst;
 
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 
     static void printMnemonic(std::ostream &os, const char *mnemonic);
     static void printReg(std::ostream &os, RegId reg);
@@ -101,7 +102,7 @@ class SparcStaticInst : public StaticInst
     void printRegArray(std::ostream &os,
         const RegId indexArray[], int num) const;
 
-    void advancePC(PCState &pcState) const;
+    void advancePC(PCState &pcState) const override;
 
     static bool passesFpCondition(uint32_t fcc, uint32_t condition);
     static bool passesCondition(uint32_t codes, uint32_t condition);

diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index a6b15388d38dcafc313515e9194ec40ecbfaf672..7fd6b245c7c79343e177911860d5b40f89522893 100644 (file)
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -38,7 +38,7 @@ class %(class_name)s : public %(base_class)s
   public:
     // Constructor.
     %(class_name)s(ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 
@@ -52,7 +52,7 @@ class %(class_name)s : public %(base_class)s
   public:
     // Constructor.
     %(class_name)s(ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
     Fault doFpOp(ExecContext *, Trace::InstRecord *) const M5_NO_INLINE;
 };
 }};
@@ -67,7 +67,7 @@ class %(class_name)s : public %(base_class)s
   public:
     // Constructor.
     %(class_name)s(const char *mnemonic, ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};
 

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index bc7d033b6c8bcbaa73d2c96878bc3832c70a73a0..aff7d4d73a8fb23f5993e946de108d50ffd81778 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -45,10 +45,11 @@ def template MemDeclare {{
             /// Constructor.
             %(class_name)s(ExtMachInst machInst);
 
-            Fault execute(ExecContext *, Trace::InstRecord *) const;
-            Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+            Fault execute(ExecContext *, Trace::InstRecord *) const override;
+            Fault initiateAcc(ExecContext *,
+                              Trace::InstRecord *) const override;
             Fault completeAcc(PacketPtr, ExecContext *,
-                              Trace::InstRecord *) const;
+                              Trace::InstRecord *) const override;
         };
 }};
 

diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 05ddc63b3a84cb8a28b799870e5f00eec4b537e9..60a72a69b789e80d2489d61137089d6fd50013d8 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -48,10 +48,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_0(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_1 : public %(base_class)sMicro
@@ -59,10 +61,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_1(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_2 : public %(base_class)sMicro
@@ -70,10 +74,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_2(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_3 : public %(base_class)sMicro
@@ -81,10 +87,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_3(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_4 : public %(base_class)sMicro
@@ -92,10 +100,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_4(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_5 : public %(base_class)sMicro
@@ -103,10 +113,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_5(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_6 : public %(base_class)sMicro
@@ -114,10 +126,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_6(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
 
             class %(class_name)s_7 : public %(base_class)sMicro
@@ -125,10 +139,12 @@ def template BlockMemDeclare {{
               public:
                 // Constructor
                 %(class_name)s_7(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                 Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
             };
         };
 }};