r600: fix constant buffer bounds.
authorDave Airlie <airlied@redhat.com>
Wed, 9 May 2018 22:17:09 +0000 (23:17 +0100)
committerDave Airlie <airlied@redhat.com>
Thu, 10 May 2018 01:14:32 +0000 (02:14 +0100)
If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).

If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.

This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
src/gallium/drivers/r600/evergreen_state.c
src/gallium/drivers/r600/r600_state.c

index 48934158bdf926a3bbd3fa884c12ef2a50e7d23d..05f4a65059bf2b1dbbf153b3c0a3e746d7086913 100644 (file)
@@ -2202,7 +2202,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
                radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
                radeon_emit(cs, va); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                            S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
                            S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
index 923817119f710b06e5ac11f318b95fbcde0fdec6..a37a70183717af3871fe529cb1ec3f31b1e0e064 100644 (file)
@@ -1729,7 +1729,7 @@ static void r600_emit_constant_buffers(struct r600_context *rctx,
                radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
                radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
                radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
-               radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
+               radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
                radeon_emit(cs, /* RESOURCEi_WORD2 */
                            S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
                            S_038008_STRIDE(gs_ring_buffer ? 4 : 16));