remove use of _r prefix on CSRs

diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py
index 7146796bf50e5ba46a5ddde0bb32208c96018c67..df56abc55a891d53f141ced11c6a0fd43be52780 100644 (file)
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@@ -33,11 +33,11 @@ class SingleGenerator(Module, AutoCSR):
                        self.trigger = Signal()
                        trigger = self.trigger
                elif mode == MODE_SINGLE_SHOT:
-                       self._r_shoot = CSR()
-                       trigger = self._r_shoot.re
+                       self._shoot = CSR()
+                       trigger = self._shoot.re
                elif mode == MODE_CONTINUOUS:
-                       self._r_enable = CSRStorage()
-                       trigger = self._r_enable.storage
+                       self._enable = CSRStorage()
+                       trigger = self._enable.storage
                else:
                        raise ValueError
                self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger))
@@ -74,10 +74,10 @@ class Collector(Module, AutoCSR):
                self.busy = Signal()
                dw = sum(len(s) for s in self.sink.payload.flatten())
 
-               self._r_wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
-               self._r_wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
-               self._r_ra = CSRStorage(bits_for(depth-1))
-               self._r_rd = CSRStatus(dw)
+               self._wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
+               self._wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
+               self._ra = CSRStorage(bits_for(depth-1))
+               self._rd = CSRStatus(dw)
 
                ###
 
@@ -90,22 +90,22 @@ class Collector(Module, AutoCSR):
                self.comb += [
                        self.busy.eq(0),
 
-                       If(self._r_wc.r != 0,
+                       If(self._wc.r != 0,
                                self.sink.ack.eq(1),
                                If(self.sink.stb,
-                                       self._r_wa.we.eq(1),
-                                       self._r_wc.we.eq(1),
+                                       self._wa.we.eq(1),
+                                       self._wc.we.eq(1),
                                        wp.we.eq(1)
                                )
                        ),
-                       self._r_wa.dat_w.eq(self._r_wa.storage + 1),
-                       self._r_wc.dat_w.eq(self._r_wc.storage - 1),
+                       self._wa.dat_w.eq(self._wa.storage + 1),
+                       self._wc.dat_w.eq(self._wc.storage - 1),
 
-                       wp.adr.eq(self._r_wa.storage),
+                       wp.adr.eq(self._wa.storage),
                        wp.dat_w.eq(self.sink.payload.raw_bits()),
 
-                       rp.adr.eq(self._r_ra.storage),
-                       self._r_rd.status.eq(rp.dat_r)
+                       rp.adr.eq(self._ra.storage),
+                       self._rd.status.eq(rp.dat_r)
                ]
 
 class _DMAController(Module):

diff --git a/migen/flow/isd.py b/migen/flow/isd.py
index a9deb81d0eda20005e5586ff6b8c7d28cc4bbc03..f657e9e4ee6be4d5ce694690eb235da4ccd3ac2e 100644 (file)
--- a/migen/flow/isd.py
+++ b/migen/flow/isd.py
@@ -45,11 +45,11 @@ class EndpointReporter(Module, AutoCSR):
 
 class DFGReporter(DFGHook, AutoCSR):
        def __init__(self, dfg, nbits):
-               self._r_magic = CSRStatus(16)
-               self._r_neps = CSRStatus(8)
-               self._r_nbits = CSRStatus(8)
-               self._r_freeze = CSRStorage()
-               self._r_reset = CSR()
+               self._magic = CSRStatus(16)
+               self._neps = CSRStatus(8)
+               self._nbits = CSRStatus(8)
+               self._freeze = CSRStorage()
+               self._reset = CSR()
 
                ###
 
@@ -58,12 +58,12 @@ class DFGReporter(DFGHook, AutoCSR):
                hooks = list(self.hooks_iter())
 
                self.comb += [
-                       self._r_magic.status.eq(ISD_MAGIC),
-                       self._r_neps.status.eq(len(hooks)),
-                       self._r_nbits.status.eq(nbits)
+                       self._magic.status.eq(ISD_MAGIC),
+                       self._neps.status.eq(len(hooks)),
+                       self._nbits.status.eq(nbits)
                ]
                for h in hooks:
                        self.comb += [
-                               h.freeze.eq(self._r_freeze.storage),
-                               h.reset.eq(self._r_reset.re)
+                               h.freeze.eq(self._freeze.storage),
+                               h.reset.eq(self._reset.re)
                        ]