radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 5f1c69870094044ff0ad5cba9a6c31c734083684..532a6365bf1b000c215e1bc7f9510912b5551beb 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -376,6 +376,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]  = 0x00000000;
                ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK]  = 0xffffffff;
+               ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM]  = 0x00000000;
 
                /* Set all saved registers state to saved. */
                ctx->tracked_regs.reg_saved = 0xffffffffffffffff;

diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 109c70a9f915150c4d037e74dd649c3de708b515..49b1ccd5823f561feb2c816843053776edf38c55 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -686,6 +686,9 @@ struct si_shader {
                        unsigned        cb_shader_mask;
                } ps;
        } ctx_reg;
+
+       /*For save precompute registers value */
+       unsigned vgt_tf_param; /* VGT_TF_PARAM */
 };
 
 struct si_shader_part {

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 878b67f0ed342bea386a87be1c4bfa48c1547311..54b03e0992f258dac1d5db5625e596a4754c9d60 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -312,6 +312,7 @@ enum si_tracked_reg {
        SI_TRACKED_SPI_SHADER_COL_FORMAT,
 
        SI_TRACKED_CB_SHADER_MASK,
+       SI_TRACKED_VGT_TF_PARAM,
 
        SI_NUM_TRACKED_REGS,
 };

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index b074214bbd31a55313f3bcc48443e91575972971..e493f991a1bd8431d83228a4d4079f75559bd0e7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -396,11 +396,11 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
        } else
                distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
 
-       si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
-                      S_028B6C_TYPE(type) |
-                      S_028B6C_PARTITIONING(partitioning) |
-                      S_028B6C_TOPOLOGY(topology) |
-                      S_028B6C_DISTRIBUTION_MODE(distribution_mode));
+       assert(pm4->shader);
+       pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
+                                   S_028B6C_PARTITIONING(partitioning) |
+                                   S_028B6C_TOPOLOGY(topology) |
+                                   S_028B6C_DISTRIBUTION_MODE(distribution_mode);
 }
 
 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
@@ -568,6 +568,12 @@ static void si_emit_shader_es(struct si_context *sctx)
        radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
                                   SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
                                   shader->selector->esgs_itemsize / 4);
+
+       if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
+               radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
+                                          SI_TRACKED_VGT_TF_PARAM,
+                                          shader->vgt_tf_param);
+
 }
 
 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@@ -802,6 +808,11 @@ static void si_emit_shader_gs(struct si_context *sctx)
                radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
                                           SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
                                           shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
+
+               if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
+                       radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
+                                                  SI_TRACKED_VGT_TF_PARAM,
+                                                  shader->vgt_tf_param);
        }
 }
 
@@ -965,6 +976,11 @@ static void si_emit_shader_vs(struct si_context *sctx)
        radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
                                   SI_TRACKED_PA_CL_VTE_CNTL,
                                   shader->ctx_reg.vs.pa_cl_vte_cntl);
+
+       if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
+               radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
+                                          SI_TRACKED_VGT_TF_PARAM,
+                                          shader->vgt_tf_param);
 }
 
 /**