rs6000.c (easy_vector_constant): Accept all vector constant loadable by vsplt*.

      * gcc/config/rs6000/rs6000.c (easy_vector_constant): Accept
      all vector constant loadable by vsplt*.
      (output_vec_const_move): Likewise.

From-SVN: r75534

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9ceffd95190b670284ad5da0b4b2cd08fdc8e2e9..96e10ab6c3714a3b6ef8b9d7f2932278f41b0f22 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2004-01-08  Hartmut Penner  <hpenner@de.ibm.com>
+
+       * gcc/config/rs6000/rs6000.c (easy_vector_constant): Accept 
+       all vector constant loadable by vsplt*.  
+       (output_vec_const_move): Likewise.
+
 2004-01-07  Joseph S. Myers  <jsm@polyomino.org.uk>
 
        PR c/6024

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index bda0777d385e91652929813277b0a5c15b08c14f..bef470f2ebadfc602cd4ff4626eca3b2c35b23fe 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1676,8 +1676,27 @@ easy_vector_constant (rtx op, enum machine_mode mode)
       && cst2 >= -0x7fff && cst2 <= 0x7fff)
     return 1;
 
-  if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode))
-    return 1;
+  if (TARGET_ALTIVEC)
+    switch (mode) 
+      {
+      case V4SImode:
+       if (EASY_VECTOR_15 (cst, op, mode))
+         return 1;
+       if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
+         break;
+       cst = cst >> 16;
+      case V8HImode:
+       if (EASY_VECTOR_15 (cst, op, mode))
+         return 1;
+       if ((cst & 0xff) != ((cst >> 8) & 0xff))
+         break;
+       cst = cst >> 8;
+      case V16QImode:
+       if (EASY_VECTOR_15 (cst, op, mode))
+         return 1;
+      default: 
+       break;
+      }
 
   if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
     return 1;
@@ -1718,23 +1737,37 @@ output_vec_const_move (rtx *operands)
     {
       if (zero_constant (vec, mode))
        return "vxor %0,%0,%0";
-      else if (EASY_VECTOR_15 (cst, vec, mode))
+      else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
+       return "#";
+      else if (easy_vector_constant (vec, mode))
        {
          operands[1] = GEN_INT (cst);
          switch (mode)
            {
            case V4SImode:
-             return "vspltisw %0,%1";
+             if (EASY_VECTOR_15 (cst, vec, mode))
+               {
+                 operands[1] = GEN_INT (cst);
+                 return "vspltisw %0,%1";
+               }
+             cst = cst >> 16;
            case V8HImode:
-             return "vspltish %0,%1";
+             if (EASY_VECTOR_15 (cst, vec, mode))
+               {
+                 operands[1] = GEN_INT (cst);
+                 return "vspltish %0,%1";
+               }
+             cst = cst >> 8;
            case V16QImode:
-             return "vspltisb %0,%1";
+             if (EASY_VECTOR_15 (cst, vec, mode))
+               {
+                 operands[1] = GEN_INT (cst);
+                 return "vspltisb %0,%1";
+               }
            default:
              abort ();
            }
        }
-      else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
-       return "#";
       else
        abort ();
     }